TWI532174B - Semiconductor structure and process thereof - Google Patents

Description

Semiconductor structure and its process

The present invention relates to a semiconductor structure and process, and more particularly to a semiconductor structure for forming a carbon-containing cap layer on an epitaxial layer and a process therefor.

As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster.

Among the currently known strained-silicon techniques, there are MOS transistors using strained silicon as a substrate, for the case of a PMOS transistor, which utilizes the lattice constant of germanium (SiGe). The different characteristics of single crystal Si cause the epitaxial layer to undergo structural strain and form strain enthalpy. Since the lattice constant of the tantalum layer is larger than that of the tantalum, this causes a change in the band structure of the tantalum, which causes an increase in carrier mobility, thereby increasing the speed of the MOS transistor.

However, the composition of the epitaxial layer is complicated, and its composition may diffuse to the periphery in subsequent processes, contaminating the surrounding area.

The present invention provides a semiconductor structure and a process for forming a carbon-containing cap layer on an epitaxial layer to prevent the formation of the epitaxial layer or the cap layer from being analyzed on the surface of the cap layer.

The present invention provides a semiconductor structure comprising a gate structure, an epitaxial layer, and a carbon-containing cap layer. The gate structure is on a substrate. The epitaxial layer is located in the substrate on the side of the gate structure. The carbon-containing ruthenium cap layer is on the epitaxial layer.

The present invention provides a semiconductor process comprising the following steps. First, a gate structure is formed on a substrate. Next, an epitaxial layer is formed in the substrate on the side of the gate structure. Thereafter, an in-situ epitaxial process is performed to form a carbon-containing capping layer on the epitaxial layer.

The present invention provides a semiconductor process comprising the following steps. First, a gate structure is formed on a substrate. Next, an epitaxial layer is formed in the substrate on the side of the gate structure. Then, a cap layer is formed on the epitaxial layer. Thereafter, carbon is doped into the cap layer to form a carbon-containing cap layer on the epitaxial layer.

Based on the above, the present invention provides a semiconductor structure and a process thereof for forming a carbon-containing cap layer on an epitaxial layer, thereby preventing the formation of the epitaxial layer or the cap layer from being analyzed on the surface of the cap layer, thereby suppressing A black spot on the surface of the cap layer is formed.

1 to 1-4 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention. As shown in Fig. 1, first, a substrate 110 is provided. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate. An insulating structure 10 can be formed between the transistors to electrically insulate the transistors. The insulating structure 10 can be, for example, a shallow trench isolation structure, but the invention is not limited thereto. A gate structure G is formed on the substrate 110. The gate structure G can include a stacked structure such as a buffer layer 122, a dielectric layer 124, a gate layer 126, a cap layer 128, and a spacer 129 at the buffer layer 122, the dielectric layer 124, and the gate layer. 126 and the substrate 110 on the side of the cover layer 128. In detail, the method for forming the gate structure G may include: firstly sequentially covering a buffer layer (not shown), a dielectric layer (not shown), a gate layer (not shown), and a A cap layer (not shown) is on the substrate 110, and the dielectric layers are patterned to form a buffer layer 122, a dielectric layer 124, a gate layer 126, and a cap layer 128. Then, a spacer (not shown) is covered on the cap layer 128 and the substrate 110, and the spacer 129 is formed by etching.

The buffer layer 122 may include an oxide layer, and the dielectric layer 124 may include a high-k dielectric layer, such as a metal-containing dielectric layer, which may include hafnium oxide, zirconium oxide. However, the invention is not limited thereto. Furthermore, the high-k dielectric layer may be selected from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride. , HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O _{3 )} Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), Strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (barium strontium titanate, A group consisting of Ba _x Sr _1-x TiO ₃ , BST). The gate layer 126 may comprise a polysilicon layer or a sacrificial layer that is replaced by a metal layer in a subsequent process to form a metal gate. The cap layer 128 can be, for example, a nitride layer. The spacer 129 is, for example, a single layer or a multilayer composite structure composed of a material such as tantalum nitride or tantalum oxide. The materials of the buffer layer 122, the dielectric layer 124, the gate layer 126, and the cap layer 128 are all exemplified, but the invention is not limited thereto.

As shown in FIG. 2, for example, dry etching is performed first and then a wet etching process is performed to form two recesses R in the substrate 110 on the side of the gate structure G. After the cleaning step, as shown in FIG. 3, a selective epitaxial (SEG) process is performed to form an epitaxial layer 130 in the recess R on the side of the gate structure G. Before forming the recess R, after forming the epitaxial layer 130, or even forming the epitaxial layer 130, an ion implantation process or an in-situ doping process may be performed to dope the desired dopant. The epitaxial layer 130 is formed to form the source/drain of the transistor element. In the present embodiment, the top surface S1 of the epitaxial layer 130 is higher than the top surface S2 of the substrate 110 to increase the effect of the epitaxial layer 130 on applying pressure to the gate channel C under the gate structure G, but the present invention Not limited to this. In a preferred embodiment, the recess R has a diamond-shaped cross-sectional structure or a cross-sectional structure of other shapes. In other words, the sidewall of the recess R under the gate structure G has at least one sharp corner, so that the epitaxial layer 130 formed therein also has a diamond-shaped cross-sectional structure, so that the epitaxial layer 130 can be increased therebetween. The stress applied by the gate channel C. In this embodiment, the epitaxial layer 130 is a germanium epitaxial layer, and the germanium concentration may be greater than 36% to form a P-type transistor. However, in other embodiments, the epitaxial layer 130 may also be A carbon epitaxial layer is formed to form an N-type transistor. Alternatively, the epitaxial layer 130 may be only a enamel epitaxial layer, or it may comprise a plurality of epitaxial layers of different materials, for example, the epitaxial layer 130 is composed of a lower layer of epitaxial layer and an upper layer of enamel epitaxial layer. composition. Alternatively, an epitaxial layer (not shown) may be selectively formed in each of the recesses R before the selective epitaxy (SEG) process, and the epitaxial layer is a low germanium concentration. The germanium epitaxial layer may have a germanium concentration of less than 25%, or a tantalum epitaxial layer, in order to avoid sudden occurrence of component starting voltage caused by excessive difference in lattice constant between the epitaxial layer 130 and the substrate 110. Problems such as decline, but the invention is not limited thereto.

As shown in FIG. 4, an epitaxial process is performed to form a germanium epitaxial layer 140a having a low germanium concentration on the epitaxial layer 130 as a reaction site for the subsequent metal telluride process to avoid metal telluride. The problem of agglomeration between metal and tantalum in the process. The epitaxial layer 130 of the present embodiment is a tantalum epitaxial layer, and the tantalum contained therein diffuses upward to the surface S of the tantalum epitaxial layer 140a, thereby causing the surface S of the tantalum epitaxial layer 140a to be black. A black spot is generated.

Therefore, the second embodiment is proposed below to improve the problem of the epitaxial structure formed by the semiconductor process of the first embodiment. 5-10 are schematic cross-sectional views showing a semiconductor process of a second embodiment of the present invention.

As follows, after the epitaxial layer 130 is formed (as in FIG. 3), a carbon-containing cap layer 140b is formed on the epitaxial layer 130. The method of formation may be as shown in FIG. 5 or as shown in FIG. 6-7.

method one:

As shown in FIG. 5, an in-situ epitaxial process P1 is performed to directly form a carbon-containing capping layer 140b on the epitaxial layer 130. In detail, the in-situ epitaxial process P1 is simultaneously doped with carbon in the cap layer when the capping layer is formed by an epitaxial process. The process gas introduced by the in-situ epitaxial process P1 may include monomethyl silane (MMS) or polymethyl decane, and the chemical formula may include (CH3)xSi ₄ -x; X>1 The carbon-containing capping layer 140b is formed by simultaneously doping carbon therein during epitaxial formation of the capping layer, but the invention is not limited thereto.

Method Two:

As shown in FIG. 6, a cap layer 140b' is first formed on the epitaxial layer 130. Next, as shown in FIG. 7, a doping process P2 is performed to dope carbon into the capping layer 140b' to form a carbon-containing capping layer 140b on the epitaxial layer 130. The carbon-doped process gas comprises monomethyl silane (MMS) or polymethyl decane, and the chemical formula thereof may include (CH3)xSi ₄ -x; X>1. In addition, the doped carbon may also utilize an ion cloth. The planting process is carried out, but the invention is not limited thereto.

Regardless of the first method or the second method, a carbon-containing capping layer 140b may be formed on the epitaxial layer 130. In the present embodiment, the carbon-containing cover layer 140b is higher than the top surface S2 of the substrate 110. Since the carbon-containing capping layer 140b contains carbonaceous material, the tantalum located in the epitaxial layer 130 or the tantalum in the carbon-containing capping layer 140b can be prevented from being formed, for example, by forming a nickel/ruthenium metal in a subsequent process. The material diffuses upward to the surface of the carbon-containing cap layer 140b to form a black spot of the enamel, deteriorating the electrical quality of the formed transistor. However, when the carbon content of the carbon-containing cover layer 140b is too high, the carbon cap layer 140b also exerts a tensile stress on the gate channel C, and this stress will form an epitaxial layer 130 with respect to the gate. The application of the compressive stress to the pole channel C cancels the effect of reducing the application of the epitaxial layer 130 to the gate channel C. Therefore, in a preferred embodiment, the carbon-containing cap layer 140b has a chemical formula of SiGe _x C _z , and the Z value of SiGe _x C _z is 0.1% to 1%, and the X value is greater than or equal to 0%. Furthermore, the carbon content distribution in the carbon-containing cover layer 140b may be in a top-down gradient distribution. Thus, by finely adjusting the distribution of the carbon content in the carbon-containing capping layer 140b, on the one hand, the tantalum located in the epitaxial layer 130 or the tantalum in the carbon-containing capping layer 140b can be effectively blocked from diffusing toward the surface. On the one hand, it can reduce the tensile stress generated by the carbon-containing cap layer 140b for the gate channel C due to the inclusion of carbon. For example, in one embodiment, the distribution of carbon content in the carbon-containing cover layer 140b may be a vertical gradient profile that decreases from top to bottom. In addition, the distribution of the carbon content in the carbon-containing capping layer 140b may also be a horizontal gradient distribution decreasing from the far-direction gate structure G, etc., and the invention is not limited thereto. Furthermore, in order to prevent the enamel in the carbon-containing capping layer 140b from diffusing to the surface, the distribution of the cerium content may be a gradient from bottom to top. Alternatively, due to the upward diffusion of the enamel layer of the epitaxial layer 130, the enamel diffuses into the carbon-containing capping layer 140b, and may also have a downwardly decreasing gradient distribution.

As shown in FIG. 8, after the carbon-containing capping layer 140b is formed, a doping process P3 is selectively performed to dope boron into the carbon-containing capping layer 140b to form a boron-containing and carbon-containing layer. Cover layer 140c. When the nickel/bismuth metal telluride is coated with the cap layer 140c containing boron and carbon, the cap layer 140c containing boron and carbon is completely or partially consumed. When the cap layer 140c containing boron and carbon remains, the boron-containing and carbon-containing cap layer 140c containing boron can lower the resistance of the contact surface. In the present embodiment, when the doping process P3 is performed, boron is simultaneously doped in the carbon-containing capping layer 140b and the epitaxial layer 130. The epitaxial layer 130 in this embodiment is a germanium epitaxial layer, and the doped boron is located inside the epitaxial layer 130. Further, a photoresist can be selectively used as a mask (not shown) such that the doped boron is only located inside the epitaxial layer 130, forming an inner epitaxial layer region 132, and forming an undoped layer. An outer epitaxial layer region 134 doped with boron, wherein the outer epitaxial layer region 134 covers the sidewall S3 and the bottom surface S4 of the inner epitaxial layer region 132. In other embodiments, boron may be doped only in the carbon-containing capping layer 140b.

In addition, when the carbon-containing capping layer 140b is formed on the epitaxial layer 130 by the second method, the doping layer 140b' may be doped on the epitaxial layer 130 (as shown in FIG. 6). Process P3 is doped with boron in cap layer 140b' to form a boron-containing cap layer (not shown). Then, the doping process P2 is performed, and carbon is doped into the boron-containing capping layer (not shown) to form a cap layer 140c containing boron and carbon on the epitaxial layer 130. Of course, when boron is doped to the capping layer 140b', boron can be simultaneously doped into the epitaxial layer 130.

In addition, at the time point of doping boron in the cap layer or the epitaxial layer, boron may be doped into the epitaxial layer before the cap layer is formed, or boron may be doped into the cap layer after the cap layer is formed. As shown in FIG. 9, after the epitaxial layer 130 is formed (as shown in FIG. 3), a doping process P4 may be performed to dope boron into the epitaxial layer 130. As shown, a photoresist can be selectively used as a mask (not shown) such that the doped boron is only located inside the epitaxial layer 130 to form an inner epitaxial layer region 132, while the outer portion is formed. An outer epitaxial layer region 134 that is not doped with boron is formed, wherein the outer epitaxial layer region 134 covers the sidewall S3 and the bottom surface S4 of the inner epitaxial layer region 132. Next, as shown in FIG. 10, a carbon-containing capping layer 140b is formed on the epitaxial layer 130 by the first method or the second method. At this time, the carbon-containing cap layer 140b does not contain boron, and thus boron may be additionally doped in the carbon-containing cap layer 140b. Alternatively, since the epitaxial layer 130 already contains boron, the boron in the epitaxial layer 130 can be diffused to the carbon-containing capping layer 140b when the thermal process is performed in a subsequent process. Alternatively, when the carbon-containing cap layer 140b is formed on the epitaxial layer 130, boron is simultaneously doped into the carbon-containing cap layer 140b to directly form a cap layer 140c containing boron and carbon.

In addition, in the present invention, whether the method 1 or the method 2 is used to form the carbon (or boron) capping layer 140b, 140c on the epitaxial layer 130, a capping layer (not shown) may be additionally formed. It is located on the carbon-containing (and boron) capping layer 140b, 140c for further consumption during the nickel/niobium metal telluride process, and maintains the structural integrity below.

In summary, the present invention provides a semiconductor structure and a process thereof for forming a carbon-containing capping layer on an epitaxial layer to prevent the formation of the epitaxial layer or the cap layer from being formed on the surface of the cap layer. The formation of a black spot on the surface of the cap layer is suppressed. Specifically, the method of forming a carbon-containing capping layer on the epitaxial layer may include: (1) performing an in-situ epitaxial process to directly form a carbon-containing capping layer on the epitaxial layer; On the layer; or, (2) first forming a cap layer on the epitaxial layer, and then performing a doping process, doping carbon into the capping layer, and forming a carbon-containing capping layer on the layer On the crystal layer.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Insulation structure

110. . . Base

122. . . The buffer layer

124. . . Dielectric layer

126. . . Gate layer

128. . . Cover

129. . . Clearance wall

130. . . Epitaxial layer

132. . . Inner layer epitaxial layer

134. . . Outer layer of epitaxial layer

140a. . . Tantalum epitaxial layer

140b’. . . Cover layer

140b. . . Carbon-containing cover

140c. . . Boron and carbon-containing capping layer

C. . . Gate channel

G. . . Gate structure

R. . . Groove

P1. . . In-situ epitaxial process

P2, P3, P4. . . Doping process

S. . . surface

S1, S2. . . Top surface

S3. . . Side wall

S4. . . Bottom

1 to 1-4 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention.

5-10 are schematic cross-sectional views showing a semiconductor process of a second embodiment of the present invention.

10. . . Insulation structure

110. . . Base

122. . . The buffer layer

124. . . Dielectric layer

126. . . Gate layer

128. . . Cover

129. . . Clearance wall

130. . . Epitaxial layer

132. . . Inner layer epitaxial layer

134. . . Outer layer of epitaxial layer

140c. . . Boron and carbon-containing capping layer

C. . . Gate channel

G. . . Gate structure

P3. . . Doping process

S2. . . Top surface

S3. . . Side wall

S4. . . Bottom

Claims (20)

A semiconductor structure comprising: a gate structure on a substrate; an epitaxial layer in the substrate on a side of the gate structure; and a carbon-containing cap layer on the epitaxial layer, wherein the The carbon-containing cover layer is higher than a top surface of the substrate. The semiconductor structure of claim 1, wherein the carbon-containing cover layer comprises a cap layer comprising boron and carbon. The semiconductor structure of claim 1, wherein the carbon-containing capping layer has a chemical formula of SiGe _x C _z and the SiGe _x C _{z has} a Z value of 0.1% to 1%. The semiconductor structure of claim 1, wherein the carbon content in the carbon-containing cover layer has a top-down gradient distribution. The semiconductor structure of claim 4, wherein the top-down gradient distribution comprises a gradient distribution that decreases from top to bottom. The semiconductor structure according to claim 1, wherein the distribution of the cerium content in the carbon-containing enamel layer is a gradient from bottom to top. The semiconductor structure of claim 1, wherein the carbon-containing cover layer is higher than the top surface of the substrate. The semiconductor structure of claim 1, further comprising a germanium-containing cap layer on the carbon-containing cap layer. The semiconductor structure of claim 1, wherein the epitaxial layer comprises a tantalum epitaxial layer. The semiconductor structure of claim 1, wherein the epitaxial layer comprises a tantalum epitaxial layer covering a sidewall and a bottom surface of the boron-containing germanium epitaxial layer. The semiconductor structure of claim 1, wherein the surface of the carbon-containing cover layer is higher than the surface of the substrate. A semiconductor process comprising: forming a gate structure on a substrate; forming an epitaxial layer in the substrate on a side of the gate structure; and performing an in-situ epitaxial process to form a A carbon cap layer is on the epitaxial layer, wherein the carbon-containing cap layer is higher than a top surface of the substrate. The semiconductor process of claim 12, wherein forming the carbon-containing cap layer comprises forming a cap layer comprising boron and carbon. The semiconductor process of claim 12, wherein after performing the in-situ epitaxial process, further comprising doping boron into the carbon-containing capping layer to form a germanium-containing layer And a carbon cap layer. The semiconductor process of claim 12, wherein the carbon-containing capping layer has a chemical formula of SiGe _x C _z and the SiGe _x C _{z has} a Z value of 0.1% to 1%. The semiconductor process of claim 12, wherein after forming the epitaxial layer, doping further comprises doping boron inside the epitaxial layer. A semiconductor process comprising: forming a gate structure on a substrate; forming an epitaxial layer in the substrate on a side of the gate structure; forming a capping layer on the epitaxial layer; and doping carbon In the capping layer, a carbon-containing capping layer is formed on the epitaxial layer, wherein the carbon-containing capping layer is higher than a top surface of the substrate. The semiconductor process of claim 17, further comprising doping boron in the cap layer after forming the cap layer. The semiconductor process of claim 17, wherein the carbon-containing capping layer has a chemical formula of SiGe _x C _z and the SiGe _x C _{z has} a Z value of 0.1% to 1%. The semiconductor process of claim 17, wherein after forming the epitaxial layer, doping further comprises doping boron inside the epitaxial layer.