TWI534907B - Semiconductor process - Google Patents

Description

Semiconductor process

This invention relates to a semiconductor process and, more particularly, to a semiconductor process for densifying an oxide layer in a double layer spacer in an oxygen-free plasma process.

As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster. Among the currently known strained-silicon techniques, there are MOS transistors using strained silicon as a substrate, for the case of a PMOS transistor, which utilizes the lattice constant of germanium (SiGe). The different characteristics of single crystal Si cause the epitaxial layer to undergo structural strain and form strain enthalpy. Since the lattice constant of the tantalum layer is larger than that of the tantalum, this causes a change in the band structure of the tantalum, which causes an increase in carrier mobility, thereby increasing the speed of the MOS transistor. For an NMOS transistor, an epitaxial layer such as tantalum carbon (SiC) can be used to form strain enthalpy.

The step of forming the epitaxial layer in the substrate on the side of the gate structure can include: forming a gate layer structure (for example, including a gate dielectric layer, a gate electrode, and a cap layer) by using a single layer of spacers. At the side, at least one groove is automatically aligned in the substrate on the side of the spacer, and an epitaxial layer is formed in the groove. Then, remove the spacers. Thereafter, a semiconductor process such as subsequent source/drain doping is performed on the substrate and the gate structure.

However, when the spacers for forming the epitaxial layer are a single layer, some disadvantages are caused. For example, due to over-etching, the underlying substrate may be damaged when the spacer is removed (the substrate may be formed with a lightly doped source/drain region at this time). Furthermore, before forming the spacers of the single layer, a sidewall may be additionally formed on the side of the gate structure to form, for example, a lightly doped source/drain region. Thus, when the single-layer spacer is removed after the epitaxial layer is formed, since the single-layer spacer is similar to the material of the sidewall, the sidewall is damaged, thereby affecting the electrical properties of the MOS transistor.

The present invention provides a semiconductor process for performing an anaerobic plasma process on a double-layer spacer to densify the oxide layer in the double-layer spacer to prevent the oxide layer from being consumed during subsequent etching processes.

The present invention provides a semiconductor process comprising the steps described below. First, a gate structure is formed on a substrate. Next, an oxide layer is formed to cover the gate structure and the substrate. Then, an anaerobic plasma process is performed to densify the oxide layer. Then, a material layer is formed to cover the oxide layer. Thereafter, the material layer and the oxide layer are etched to form a double-layer spacer.

Based on the above, the present invention provides a semiconductor process in which, when a double-layer spacer having an inner oxide layer and an outer material layer is formed, an anaerobic plasma process is performed immediately after the formation of the oxide layer to densify the oxide layer. In this way, the oxide layer can be prevented from being consumed during the subsequent etching process, particularly the wet etching process. Specifically, the wet etching process is, for example, a pre-cleaning process for the grooves after forming the grooves and before forming the epitaxial layer.

1-9 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention. As shown in Fig. 1, first, a substrate 110 is formed. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate. An insulating structure 20 may be formed between the transistors to electrically insulate each of the transistors. The insulating structure 20 can be, for example, a shallow trench isolation structure, but the invention is not limited thereto. A gate structure G is then formed on the substrate 110. The gate structure G may include a stacked structure such as a buffer layer 122, a dielectric layer 124, a gate layer 126, and a cap layer 128. In detail, the method for forming the gate structure G may include: firstly sequentially covering a buffer layer (not shown), a dielectric layer (not shown), a gate layer (not shown), and a A cap layer (not shown) is on the substrate 110, and the dielectric layers are patterned to form a buffer layer 122, a dielectric layer 124, a gate layer 126, and a cap layer 128.

The buffer layer 122 may include an oxide layer, and the dielectric layer may include a high-k dielectric layer, such as a metal-containing dielectric layer, and may include a hafnium oxide and a zirconium oxide. However, the invention is not limited thereto. Furthermore, the high-k dielectric layer may be selected from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride. , HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O _{3 )} Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), Strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (barium strontium titanate, A group consisting of Ba _x Sr _1-x TiO ₃ , BST). The gate layer 126 may comprise a polysilicon layer or a sacrificial layer to be replaced by a metal layer in a subsequent process to form a metal gate. The cap layer 128 can be, for example, a nitride layer. The materials of the buffer layer 122, the dielectric layer 124, the gate layer 126, and the cap layer 128 are all exemplified, but the invention is not limited thereto.

As shown in FIG. 2, a first spacer 129 is formed on the substrate 110 on the side of the gate structure G. For example, it is formed by oxidation, nitridation, or the like, or a gap layer (not shown) is firstly covered on the cap layer 128 and the substrate 110, and the first spacer 129 is formed by etching. In the present embodiment, the first spacer 129 is a nitride layer which defines and forms a lightly doped source/drain region, but in other embodiments the first spacer 129 may be, for example, tantalum nitride. The single layer or multi-layer composite structure composed of a material such as cerium oxide is not limited thereto. Therefore, after the first spacers 129 are formed, for example, an ion implantation process is performed to form a lightly doped source/drain region 130.

As shown in FIG. 3, an oxide layer 142 is formed to cover the gate structure G and the substrate 110, and the oxide layer 142 is formed, for example, by a deposition process. As shown in Fig. 4, an anaerobic plasma process P1 is performed to densify the oxide layer 142. The anaerobic plasma process P1 may include the introduction of at least one inert gas, such as helium, argon, etc.; or, the oxygen-free plasma process P1 may include the introduction of nitrogen. Furthermore, the anaerobic plasma process P1 can be, for example, a decouple plasma process, but the invention is not limited thereto. In addition, when the process time of the oxygen-free plasma process P1 is too short, the effect of densification of the oxide layer 142 is not good, but when the process time of the oxygen-free plasma process P1 is too long, the oxide layer 142 is The surface will be damaged by the impact of the plasma. Therefore, in a preferred embodiment, the process time of the oxygen-free plasma process P1 is from 20 seconds to 120 seconds.

After the oxygen-free plasma process P1 is completed, as shown in FIG. 5, a material layer 144 is formed to cover the oxide layer 142. In the present embodiment, the material layer 144 is a nitride layer, but the invention is not limited thereto. As shown in FIG. 6, the material layer 144 and the oxide layer 142 are simultaneously etched to form a double-layer spacer 140. As a result, the formed double-layer spacer 140 is a double-layer spacer 140 of an inner oxide layer 142'/outer material layer 144', and the inner oxide layer 142' has an L-shaped cross-sectional structure. Furthermore, in the present embodiment, since the material layer 144 is a nitrided layer, the double-layer spacers 140 of the inner oxide layer 142'/outer material layer 144' are formed as an inner oxide layer. The double-layer spacer 140 of the outer layer nitride layer, and the etching process for etching the nitride layer may be an anisotropic dry etching, but the invention is not limited thereto. In other embodiments, the material layer 144 may be other materials to form an inner oxide layer 142 ′, and the outer layer is a double-layer spacer 140 of other materials, as needed, and used to etch the double-layer spacer 140 or Subsequent to the etchant forming the etching process of the recess or the like.

Furthermore, in this embodiment, after depositing and covering two dielectric layers (the oxide layer 142 and the material layer 144), the two dielectric layers are etched together to form an inner oxide layer having an L-shaped cross-sectional structure. 142'. However, in other embodiments, the oxide layer 142 and the material layer 144 may be covered and etched, respectively. In other words, after the oxide layer 142 is first covered and etched, the material layer 144 is formed and etched, so that the cross-sectional structure of the inner oxide layer 142' and the outer material layer 144' of the formed double-layer spacer 140 can be controlled. . Alternatively, after the oxide layer 142 and the material layer 144 are covered, the material layer 144 and the oxide layer 142 are respectively etched according to the desired cross-sectional structure of the double-layer spacers 140.

As shown in FIG. 7, an etching process P2 is performed to form two grooves R in the substrate 110 outside the double-layer spacers 140. The etching process P2 may include a dry etching process and/or a wet etching process or the like. For example, a predetermined depth of the recess R may be first etched by a dry etching process, and the recess R may be laterally widened by a wet etching process to form a diamond-shaped cross-sectional structure or a cross-sectional structure having other shapes.

Next, a cleaning process P3 is performed to clean the surface S1 of the recess R to remove impurities such as native oxide on the surface S1 of the recess R. The cleaning process P3 can be a cleaning process containing diluted hydrofluoric acid, but the invention is not limited thereto. It is emphasized that since both the native oxide and the inner oxide layer 142' are made of an oxide material, if the cleaning process P3 is performed, if the oxygen-free plasma process P1 of the present invention is not performed first, the dense treatment is performed. A portion of the inner oxide layer 142' is removed along with the native oxide to damage the inner oxide layer 142'. And if a portion of the inner oxide layer 142' is removed, the aforementioned advantages of having the inner oxide layer 142' are greatly reduced or eliminated. For example, the first spacer 129 is prevented from being damaged when the outer layer of material 144' is removed, or the lightly doped source/drain region 130 located below the inner oxide layer 142' is damaged. However, by using the oxygen-free plasma process P1 densified oxide layer 142 of the present invention, the structure of the oxide layer 142 can be strengthened, and the inner oxide layer 142' can be prevented from being combined with the original process during the cleaning process P3. The oxides are removed together.

After the cleaning process P3 is completed, as shown in FIG. 8, an epitaxial process P4 is performed to form an epitaxial structure 150 in the recess R. The epitaxial structure 150 can be, for example, a germanium epitaxial layer or the like for forming a P-type transistor, or can be, for example, a germanium carbon epitaxial layer or the like for forming an N-type transistor.

As shown in Fig. 9, an etching process P5, such as a wet etching process including hot phosphoric acid, is performed to remove the outer layer material layer 144'. Thus, the inner oxide layer 142' underlying the outer material layer 144' is exposed. In a subsequent process, the inner oxide layer 142' is selectively removed, and then a main spacer (not shown) is formed to define and form the source/drain regions. Thereafter, a source/drain region (not shown) is formed in the substrate 110 on the side of the main spacer (not shown). Then, other subsequent semiconductor processes can be continued, such as forming a metal germanide in the source/drain region (not shown); and fully covering a contact Etch Stop Layer (CESL) (not shown) Forming an interlayer dielectric layer (not shown) on the contact hole etch stop layer (not shown); planarizing the interlayer dielectric layer (not shown) and the contact hole etch stop layer (not shown); A metal gate replacement process is formed; a contact hole (not shown) is formed on the interlayer dielectric layer (not shown); and a metal pillar (not shown) is formed in the contact hole (not shown).

In the preferred embodiment, the material layer 144 and the material of the oxide layer 142 must have different etching selectivity ratios, that is, for an etching. In terms of process, both have different etch rates. Because, in general, the material layer 144 and the first spacer 129 are composed of the same or similar materials, although the precursors used to form the two dielectric layers may be different, because the material properties of the two dielectric layers are similar, such as The absence of other material isolation between the materials of the two dielectric layers may result in the etching of the material layer 144 to the first spacer 129, while damaging the structure of the first spacer 129. Therefore, the material of the material layer 144 and the oxide layer 142 must be selected from materials having different etching selectivity ratios, so that the oxide layer 142 can serve as an etch stop layer when the material layer 144 is removed. Moreover, since the material layer 144 and the oxide layer 142 have different etching selectivity ratios, the oxide layer 142 can remain after the material layer 144 is completely removed, and the L-shaped cross-sectional structure can protect the light doping underneath it. Source/drain region 130.

In summary, the present invention provides a semiconductor process for forming a double-layer spacer having an inner oxide layer and an outer material layer, and then performing an anaerobic plasma process after forming the oxide layer to densify the oxide layer. . In this way, the oxide layer can be prevented from being consumed during the subsequent etching process, particularly the wet etching process. Specifically, the wet etching process may be, for example, a pre-cleaning process performed on the surface of the groove after forming the groove and before forming the epitaxial layer, which is to remove the native oxide or the like located on the surface of the groove. Therefore, since the present invention employs an oxygen-free plasma process to densify the oxide layer, the structure of the oxide layer can be strengthened, thereby preventing the oxide layer from being consumed in the etching process. Therefore, the oxide layer of the present invention can fully function to protect the first spacer and the lightly doped source/drain region or substrate below it.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

20. . . Insulation structure

110. . . Base

120. . . First spacer

122. . . The buffer layer

124. . . Dielectric layer

126. . . Gate layer

128. . . Cover

129. . . Clearance wall

130. . . Lightly doped source/drain region

140. . . Double barrier

142. . . Oxide layer

142’. . . Inner oxide layer

144. . . Material layer

144’. . . Outer nitride layer

150. . . Epitaxial structure

G. . . Gate structure

P1. . . Anaerobic plasma process

P2, P5. . . Etching process

P3. . . Cleaning process

P4. . . Epitaxial process

R. . . Groove

S1. . . surface

1-9 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

20. . . Insulation structure

110. . . Base

122. . . The buffer layer

124. . . Dielectric layer

126. . . Gate layer

128. . . Cover

129. . . First spacer

130. . . Lightly doped source/drain region

142. . . Oxide layer

G. . . Gate structure

P1. . . Anaerobic plasma process

Claims (16)

A semiconductor process comprising: forming a gate structure on a substrate; forming an oxide layer over the gate structure and the substrate; performing an anaerobic plasma process to densify the oxide layer; forming a material layer covering the An oxide layer; and simultaneously etching the material layer and the oxide layer to form a double-layer spacer. The semiconductor process of claim 1, wherein the anaerobic plasma process comprises introducing at least one inert gas. The semiconductor process of claim 2, wherein the inert gas comprises helium. The semiconductor process of claim 2, wherein the inert gas comprises argon. The semiconductor process of claim 1, wherein the anaerobic plasma process comprises introducing nitrogen. The semiconductor process of claim 1, wherein the material layer comprises a nitride layer. The semiconductor process of claim 6, wherein the double-layer spacer comprises a double-layer spacer of an inner oxide layer/outer nitride layer. The semiconductor process of claim 7, wherein the inner oxide layer of the double-layer spacer has an L-shaped cross-sectional structure. The semiconductor process of claim 1, wherein the process of the anaerobic plasma process is from 20 seconds to 120 seconds. The semiconductor process of claim 1, wherein the anaerobic plasma process comprises a decouple plasma process. The semiconductor process of claim 1, wherein after forming the double-layer spacer, the method further comprises: performing an etching process to form at least one groove in the substrate outside the double-layer spacer. The semiconductor process of claim 11, wherein the etching process comprises a dry etching process or a wet etching process. The semiconductor process of claim 11, wherein after performing the etching process, further comprising: performing a cleaning process to clean the surface of the groove; An epitaxial process is performed to form an epitaxial structure in the recess. The semiconductor process of claim 13, wherein the cleaning process comprises a cleaning process comprising dilute hydrofluoric acid. The semiconductor process of claim 1, wherein after forming the double-layer spacer, the method further comprises: performing an etching process to remove the material layer remaining after the etching. The semiconductor process of claim 15, wherein the etching process comprises a wet etching process comprising hot phosphoric acid.