TWI575578B - Semiconductor process - Google Patents

Semiconductor process Download PDF

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TWI575578B
TWI575578B TW102118630A TW102118630A TWI575578B TW I575578 B TWI575578 B TW I575578B TW 102118630 A TW102118630 A TW 102118630A TW 102118630 A TW102118630 A TW 102118630A TW I575578 B TWI575578 B TW I575578B
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etching
gas
semiconductor process
semiconductor
deposition
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TW201445622A (en
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張明華
吳俊元
簡金城
余典衞
林鈺書
賴思豪
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聯華電子股份有限公司
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Description

半導體製程 Semiconductor process

本發明係關於一種半導體製程,且特別係關於一種將凹槽之表面改質之半導體製程。 This invention relates to a semiconductor process, and more particularly to a semiconductor process for modifying the surface of a recess.

隨著半導體製程進入到深次微米時代,例如65奈米(nm)以下之製程,對於MOS電晶體元件的驅動電流(drive current)的提昇已顯得日益重要。為了改善元件的效能,目前業界已發展出所謂的「應變矽(strained-silicon)技術」,其原理主要是使閘極通道部分的矽晶格產生應變,使電荷在通過此應變之閘極通道時的移動力增加,進而達到使MOS電晶體運作更快的目的。在目前已知的技術中,已有使用應變矽(strained silicon)作為基底的MOS電晶體,其利用矽鍺(SiGe)或矽碳(SiC)的晶格常數與單晶矽(single crystal Si)不同的特性,使矽鍺磊晶結構產生結構上應變而形成應變矽。由於矽鍺磊晶結構或矽碳磊晶結構的晶格常數(lattice constant)比矽大或比矽小,這使得矽的帶結構(band structure)發生改變,而造成載子移動性增加,因此可增加MOS電晶體的速度。 As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster. Among the currently known techniques, MOS transistors using strained silicon as a substrate have been used which utilize the lattice constant of bismuth (SiGe) or bismuth carbon (SiC) and single crystal Si (single crystal Si). Different characteristics cause the structure of the germanium epitaxial structure to strain and form strain enthalpy. Since the lattice constant of the germanium epitaxial structure or the germanium carbon epitaxial structure is larger than or larger than the germanium, this causes the band structure of the germanium to change, resulting in an increase in carrier mobility. The speed of the MOS transistor can be increased.

再者,除了磊晶結構之種類會影響施加於MOS電晶體之閘極通道的應力之外,磊晶結構之形狀亦會影響施加於MOS電晶體之閘極通道的應力效能,特別是磊晶結構之形狀可控制施加於閘極通道之局部應力,俾能更精確達到或改善MOS電晶體的各種電 性的性能。然而,磊晶結構之形狀卻會在製作過程中,因為製程溫度等製程條件的影響而發生改變,導致最後所形成之磊晶結構之形狀與原先設定且蝕刻之形狀不同,因而難以準確控制所形成之電晶體的品質。 Furthermore, in addition to the type of epitaxial structure that affects the stress applied to the gate channel of the MOS transistor, the shape of the epitaxial structure also affects the stress performance applied to the gate channel of the MOS transistor, particularly epitaxial The shape of the structure controls the local stress applied to the gate channel, and the electric energy of the MOS transistor can be more accurately achieved or improved. Sexual performance. However, the shape of the epitaxial structure changes during the manufacturing process due to process conditions such as process temperature, resulting in the shape of the finally formed epitaxial structure being different from the originally set and etched shape, making it difficult to accurately control the shape. The quality of the formed transistor.

本發明提出一種半導體製程,其藉由進行一表面改質製程於凹槽的表面,以控制所形成之凹槽的形狀,以及其表面的物質含量。 The present invention provides a semiconductor process for performing a surface modification process on the surface of a recess to control the shape of the recess formed and the material content of the surface.

本發明提供一種半導體製程,包含有下述步驟。首先,形成二閘極於一基底上。接著,形成一凹槽於閘極側邊的基底中。然後,進行一表面改質製程於凹槽的一表面,以整修凹槽的形狀並將表面改質。 The present invention provides a semiconductor process comprising the steps described below. First, a second gate is formed on a substrate. Next, a recess is formed in the substrate on the side of the gate. Then, a surface modification process is performed on a surface of the recess to reshape the groove and modify the surface.

基於上述,本發明提出一種半導體製程,其藉由進行一表面改質製程,俾整修凹槽之形狀並將凹槽表面改質。例如,經由表面改質製程可恢復原先所蝕刻出之凹槽形狀,其可能在蝕刻後的各項製程中因各種製程環境所影響而改變;再者,可將凹槽表面改質成具有後續形成於其上的磊晶結構之含量,以促進二者之鍵結並減少介面缺陷。 Based on the above, the present invention proposes a semiconductor process in which the shape of the groove is trimmed and the surface of the groove is modified by performing a surface modification process. For example, the shape of the originally etched groove can be restored through the surface modification process, which may be changed in various processes after etching due to various process environments; further, the groove surface may be modified to have a follow-up The amount of epitaxial structure formed thereon to promote bonding between the two and reduce interface defects.

110‧‧‧基底 110‧‧‧Base

120‧‧‧閘極 120‧‧‧ gate

122‧‧‧介電層 122‧‧‧ dielectric layer

124‧‧‧電極層 124‧‧‧electrode layer

126‧‧‧蓋層 126‧‧‧ cover

130‧‧‧間隙壁 130‧‧‧ spacer

140‧‧‧晶種層 140‧‧‧ seed layer

150‧‧‧磊晶結構 150‧‧‧ epitaxial structure

C‧‧‧閘極通道 C‧‧‧gate channel

d1‧‧‧厚度 D1‧‧‧ thickness

E1‧‧‧氫氣烘烤製程 E1‧‧‧ Hydrogen baking process

E2‧‧‧乾式蝕刻製程 E2‧‧‧dry etching process

E3‧‧‧表面改質製程 E3‧‧‧Surface modification process

P1、P2、P3、P4、P5、P6、P7‧‧‧步驟 P1, P2, P3, P4, P5, P6, P7‧‧‧ steps

R、R1‧‧‧凹槽 R, R1‧‧‧ groove

S、S1‧‧‧表面 S, S1‧‧‧ surface

T‧‧‧尖角 T‧‧‧ sharp corner

第1圖係繪示本發明一實施例之半導體製程之流程圖。 1 is a flow chart showing a semiconductor process according to an embodiment of the present invention.

第2-7圖係繪示本發明一實施例之半導體製程之剖面圖。 2-7 are cross-sectional views showing a semiconductor process in accordance with an embodiment of the present invention.

第1圖係繪示本發明一實施例之半導體製程之流程圖。第2-7圖係繪示本發明一實施例之半導體製程之剖面圖。請同時參閱第1圖以及第2-7圖。 1 is a flow chart showing a semiconductor process according to an embodiment of the present invention. 2-7 are cross-sectional views showing a semiconductor process in accordance with an embodiment of the present invention. Please also refer to Figure 1 and Figure 2-7.

首先,根據第1圖之步驟P1:形成二閘極於一基底上。如第2圖所示,提供一基底110,其中基底110例如是一矽基底、一含矽基底、一三五族覆矽基底(例如GaN-on-silicon)、一石墨烯覆矽基底(graphene-on-silicon)或一矽覆絕緣(silicon-on-insulator,SOI)基底等半導體基底。接著,形成二閘極120於基底110上。每一閘極120可包含由下而上堆疊之一介電層122、一電極層124以及一蓋層126。詳細而言,可先全面且依序覆蓋一介電層(未繪示)、一電極層(未繪示)以及一蓋層(未繪示)於基底110上,然後圖案化蓋層(未繪示)、電極層(未繪示)以及介電層(未繪示),以形成介電層122、電極層124以及蓋層126堆疊於基底110上。在第2-7圖中係繪示二閘極120,以便於清楚揭露本發明,但閘極120之個數非限於此;在其他實施例中,閘極120之個數可為一個或超過兩個,視實際需求而定。 First, according to step P1 of Fig. 1, a second gate is formed on a substrate. As shown in FIG. 2, a substrate 110 is provided, wherein the substrate 110 is, for example, a germanium substrate, a germanium-containing substrate, a tri-five-layered germanium substrate (eg, GaN-on-silicon), and a graphene-coated substrate (graphene). -on-silicon) or a semiconductor substrate such as a silicon-on-insulator (SOI) substrate. Next, two gates 120 are formed on the substrate 110. Each gate 120 can include a dielectric layer 122, an electrode layer 124, and a cap layer 126 stacked from bottom to top. In detail, a dielectric layer (not shown), an electrode layer (not shown), and a cap layer (not shown) on the substrate 110 may be completely and sequentially covered, and then the cap layer is patterned (not An electrode layer (not shown) and a dielectric layer (not shown) are formed to form a dielectric layer 122, an electrode layer 124, and a cap layer 126 stacked on the substrate 110. The second gate 120 is shown in FIGS. 2-7 in order to clearly disclose the present invention, but the number of the gates 120 is not limited thereto; in other embodiments, the number of the gates 120 may be one or more. Two, depending on actual needs.

本發明可適用於一多晶矽閘極製程、一前閘極(Gate-First)製程、一前置高介電常數之後閘極(Gate-Last for High-K-First)製程、一前置緩衝層後置高介電常數之後閘極(Gate-Last for High-K-Last,Buffer Layer-First)製程或一後置緩衝層後置高介電常數之後閘極(Gate-Last for High-K-Last,Buffer Layer-Last)製程等。因此,介電層122可包含一氧化層、一緩衝層或/且一高介電常數介電層,但本發明不以此為限。例如,當本發 明應用於一多晶矽閘極製程時,介電層122則為一適於多晶矽閘極之介電材,例如氧化層;當本發明應用於一前閘極製程或一前置高介電常數後閘極製程時,介電層122則可包含一緩衝層以及一高介電常數介電層;當本發明應用於一前置緩衝層後置高介電常數之後閘極製程時,介電層122則可包含一緩衝層以及一犧牲介電層,其中犧牲介電層會於後續金屬閘極置換(Metal Gate Replacement)製程中被置換為一高介電常數介電層;當本發明應用於一後置緩衝層後置高介電常數之後閘極製程時,介電層122則可為一犧牲介電層,其中犧牲介電層會於後續金屬閘極置換(Metal Gate Replacement)製程中被置換為一緩衝層以及一高介電常數介電層。緩衝層可例如為一氧化層,其例如以一熱氧化(Thermal Oxide)製程或一化學氧化(Chemical Oxide)製程形成,但本發明不以此為限。高介電常數介電層例如為一含金屬介電層,其可包含有鉿(Hafnium)氧化物、鋯(Zirconium)氧化物,但本發明不以此為限。更進一步而言,高介電常數閘極介電層係可選自氧化鉿(hafnium oxide,HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)與鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)所組成之群組。電極層124可例如為一多晶矽層。蓋層126例如為包含氮化層、氧化層等之單層或雙層結構。 The invention can be applied to a polysilicon gate process, a gate-first process, a gate-high-potential constant gate (Gate-Last for High-K-First) process, and a pre-buffer layer. Post-high dielectric constant post gate (Gate-Last for High-K-Last, Buffer Layer-First) process or a post-buffer layer after high dielectric constant post gate (Gate-Last for High-K- Last, Buffer Layer-Last) process. Therefore, the dielectric layer 122 may include an oxide layer, a buffer layer, or/and a high-k dielectric layer, but the invention is not limited thereto. For example, when the hair When applied to a polysilicon gate process, the dielectric layer 122 is a dielectric material suitable for a polysilicon gate, such as an oxide layer; when the invention is applied to a front gate process or a pre-high dielectric constant During the gate process, the dielectric layer 122 may include a buffer layer and a high-k dielectric layer; when the present invention is applied to a pre-buffer layer after a high dielectric constant and then a gate process, the dielectric layer 122 may include a buffer layer and a sacrificial dielectric layer, wherein the sacrificial dielectric layer is replaced with a high-k dielectric layer in a subsequent metal gate replacement (Metal Gate Replacement) process; The dielectric layer 122 can be a sacrificial dielectric layer after a high dielectric constant is followed by a gate dielectric process, wherein the sacrificial dielectric layer is in the subsequent metal gate replacement (Metal Gate Replacement) process. The replacement is a buffer layer and a high-k dielectric layer. The buffer layer may be, for example, an oxide layer, which is formed, for example, by a thermal oxidation process or a chemical oxidation process, but the invention is not limited thereto. The high-k dielectric layer is, for example, a metal-containing dielectric layer, which may contain a hafnium oxide or a zirconium oxide, but the invention is not limited thereto. Furthermore, the high dielectric constant gate dielectric layer may be selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), and hafnium silicon oxynitride. , HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), titanium Strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), zirconium A group consisting of lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST). The electrode layer 124 can be, for example, a polysilicon layer. The cap layer 126 is, for example, a single layer or a two-layer structure including a nitride layer, an oxide layer, or the like.

接著,形成一間隙壁130於閘極120側邊的基底110上,以定義後續所形成之磊晶結構的位置。間隙壁130可例如由氮化矽、氮氧化矽等所組成之單層結構,或者由氧化矽/氮化矽等所組成之雙層結構,但本發明不以此為限。詳細而言,形成間隙壁130的方法可例如為:先沈積一間隙壁材料於各閘極120以及基底110上,再進行一蝕刻製程以形成間隙壁130。本實施例所指之間隙壁130係為用以定義及形成磊晶結構之間隙壁,因此在形成間隙壁130之前或之後,可能會再另外形成其他較薄的間隙壁以形成輕摻雜源/汲極區(未繪示)或另外形成其他較厚的間隙壁以形成源/汲極區(未繪示)等。為能簡化及清楚揭示本發明,第2-7圖僅繪示用以形成磊晶結構之間隙壁130。 Next, a spacer 130 is formed on the substrate 110 on the side of the gate 120 to define the position of the subsequently formed epitaxial structure. The spacer 130 may be a single layer structure composed of tantalum nitride, hafnium oxynitride or the like, or a two-layer structure composed of hafnium oxide/tantalum nitride or the like, but the invention is not limited thereto. In detail, the method of forming the spacers 130 may be, for example, depositing a spacer material on each of the gates 120 and the substrate 110, and performing an etching process to form the spacers 130. The spacer 130 referred to in this embodiment is a spacer for defining and forming an epitaxial structure. Therefore, before or after the spacer 130 is formed, other thin spacers may be additionally formed to form a lightly doped source. / drain region (not shown) or otherwise form other thicker spacers to form a source/drain region (not shown) or the like. In order to simplify and clearly disclose the present invention, FIGS. 2-7 only show the spacers 130 for forming an epitaxial structure.

接續,根據第1圖之步驟P2:形成一凹槽於閘極側邊的基底中。可如第3圖所示,進行一蝕刻製程,蝕刻暴露出的基底110,而於基底110中形成一凹槽R。更進一步而言,蝕刻可包含至少一乾蝕刻步驟或/以及至少一濕蝕刻步驟,例如先以一乾蝕刻步驟蝕刻基底110至一預定深度,然後以一濕蝕刻步驟側向蝕刻以形成所需之凹槽R的輪廓,但本發明不以此為限。因此,間隙壁130底部與基底110接觸之厚度d1會影響凹槽R相對於閘極120的距離,此距離為影響施加於一閘極通道C之應力的一重要因素。在本實施例中,凹槽R具有一鑽石形的剖面結構,但本發明不以此為限,凹槽R可視實際需要具有不同之剖面結構。凹槽R之尖角T可增加後續形成於其中之磊晶結構施加於閘極通道C之局部應力,而此局部應力可提升磊晶結構的效能並能更精確控制所施加於閘極通道C至各部位之應力,進而達到提升元件電性的功能。因此,可藉由調整凹 槽R相對於閘極120的距離,以及凹槽R之形狀(其所能形成之尖角T的數量以及尖角T之位置),而控制形成於凹槽R中之磊晶結構施加於閘極通道C之應力大小以及局力應力之分佈。 Next, according to step P2 of Fig. 1, a groove is formed in the substrate on the side of the gate. As shown in FIG. 3, an etching process is performed to etch the exposed substrate 110, and a recess R is formed in the substrate 110. Still further, the etching may include at least one dry etching step or/and at least one wet etching step, such as etching the substrate 110 to a predetermined depth by a dry etching step, and then laterally etching in a wet etching step to form a desired recess. The outline of the groove R, but the invention is not limited thereto. Therefore, the thickness d1 of the bottom of the spacer 130 contacting the substrate 110 affects the distance of the recess R relative to the gate 120, which is an important factor affecting the stress applied to a gate channel C. In the present embodiment, the groove R has a diamond-shaped cross-sectional structure, but the invention is not limited thereto, and the groove R may have different cross-sectional structures as needed. The sharp corner T of the groove R can increase the local stress applied to the gate channel C by the epitaxial structure formed therein, and the local stress can improve the performance of the epitaxial structure and can more accurately control the applied to the gate channel C. The stress to each part, and thus the function of improving the electrical properties of the component. Therefore, by adjusting the concave The distance of the groove R with respect to the gate 120, and the shape of the groove R (the number of sharp angles T and the position of the sharp angle T which can be formed), and the epitaxial structure formed in the groove R is applied to the gate The stress of the pole channel C and the distribution of the local stress.

之後,可選擇性進行一濕式清洗製程(未繪示),清洗蝕刻後的凹槽R表面S。濕式清洗製程可例如為含稀釋氫氟酸(Dilute Hydrofluoric Acid,DHF)的製程,但本發明不以此為限。 Thereafter, a wet cleaning process (not shown) may be selectively performed to clean the surface S of the etched groove R. The wet cleaning process can be, for example, a process including dilute hydrofluoric acid (DHF), but the invention is not limited thereto.

續之,根據第1圖之步驟P3:進行一氫氣烘烤製程,於凹槽。選擇性進行一氫氣烘烤製程E1於凹槽R中,以形成一凹槽R1,可如第4圖所示。進行氫氣烘烤製程E1的目的,係為進一步清洗凹槽R1的表面S1,揮發位於凹槽R1表面S1之不需要或者會劣化後續製程之物質,例如在第3圖之步驟形成凹槽R的蝕刻製程中,因製程氣體所留下之殘留物等。在一實施例中,氫氣烘烤製程E1的製程溫度為725℃,俾能有效移除不必要的物質。然而,氫氣烘烤製程E1由於具有例如725℃等製程高溫,而會導致凹槽R表面S的物質(例如矽)遷移,而改變原先之凹槽R的形狀,特別是圓弧化凹槽R之各尖角T,而形成凹槽R1,其具有平緩的剖面輪廓。此輪廓因缺乏尖角T而會劣化施加於閘極通道C之局部疊加應力。 Continued, according to step P3 of Figure 1, a hydrogen baking process is performed in the groove. A hydrogen baking process E1 is selectively performed in the recess R to form a recess R1 as shown in FIG. The purpose of performing the hydrogen baking process E1 is to further clean the surface S1 of the groove R1, volatilize the material which is not required on the surface S1 of the groove R1 or which may deteriorate the subsequent process, for example, forming the groove R in the step of FIG. Residues left by process gases during the etching process. In one embodiment, the hydrogen baking process E1 has a process temperature of 725 ° C, and the crucible can effectively remove unnecessary substances. However, the hydrogen baking process E1 has a process temperature of, for example, 725 ° C, which causes a substance (for example, ruthenium) of the surface S of the groove R to migrate, and changes the shape of the original groove R, particularly the arcuate groove R. Each of the sharp corners T forms a groove R1 having a gentle cross-sectional profile. This profile degrades the local superimposed stress applied to the gate channel C due to the lack of the sharp corner T.

根據第1圖之步驟P4:進行一乾式蝕刻製程,於凹槽。選擇性進行一乾式蝕刻製程E2於凹槽R1中,可如第4圖所示。選擇性進行乾式蝕刻製程E2可進一步清洗凹槽R1表面S1的殘留物,並且修補表現缺陷。在一較佳的實施例中,乾式蝕刻製程E2例如可通入氯化氫氣體或氯氣作為蝕刻氣體,並且搭配通入氫氣作為承載氣體,但本發明不以此為限。在其他實施例中,乾式蝕刻製程E2 例如可通入氟化氫(hydrogen fluoride,HF)、氟氣(fluorine,F2)、溴化氫(hydrogen bromide,HBr)、溴氣(bromine,Br2)等可蝕刻矽質材料等氣體作為蝕刻氣體。在一較佳實施例中,乾式蝕刻製程E2的製程溫度為600℃~750℃;在一更佳的實施例中,乾式蝕刻製程E2的製程溫度低於720℃,俾能有足夠高溫有效清洗凹槽R1表面S1的殘留物,並且修補表現缺陷,但又能盡可能減少凹槽R1表面S1圓弧化的問題。甚至,可藉由調整製程溫度(例如671℃)以及所通入之氣體(例如以氯化氫氣體作為蝕刻氣體以及氫氣作為承載氣體),而可使乾式蝕刻製程E2藉由回蝕刻的機制,輔以略微恢復凹槽R之形狀的功能。此外,本實施例係為先進行氫氣烘烤製程E1再進行乾式蝕刻製程E2,但在其他實施例中氫氣烘烤製程E1與乾式蝕刻製程E2可同時進行,意即在進行氫氣烘烤製程E1時,通入乾式蝕刻製程E2之蝕刻氣體。 According to step P4 of Figure 1, a dry etching process is performed in the recess. Optionally, a dry etching process E2 is performed in the recess R1 as shown in FIG. The selective dry etching process E2 further cleans the residue of the surface S1 of the groove R1 and repairs the performance defect. In a preferred embodiment, the dry etching process E2 can be, for example, a hydrogen chloride gas or a chlorine gas as an etching gas, and a hydrogen gas is used as a carrier gas, but the invention is not limited thereto. In other embodiments, the dry etching process E2 can be, for example, hydrogen fluoride (HF), fluorine (F2), hydrogen bromide (HBr), bromine (Br 2 ), or the like. A gas such as a tantalum material is etched as an etching gas. In a preferred embodiment, the dry etching process E2 has a process temperature of 600 ° C to 750 ° C; in a more preferred embodiment, the dry etching process E 2 has a process temperature of less than 720 ° C and can be effectively cleaned at a high temperature. The residue of the surface S1 of the groove R1, and repairing the performance defect, but can minimize the problem of the arc of the surface S1 of the groove R1. Even by adjusting the process temperature (for example, 671 ° C) and the introduced gas (for example, hydrogen chloride gas as an etching gas and hydrogen as a carrier gas), the dry etching process E2 can be supplemented by a etch back mechanism. The function of slightly restoring the shape of the groove R. In addition, in this embodiment, the hydrogen baking process E1 is performed first and then the dry etching process E2 is performed. However, in other embodiments, the hydrogen baking process E1 and the dry etching process E2 can be simultaneously performed, that is, the hydrogen baking process E1 is performed. At the time, the etching gas of the dry etching process E2 is passed.

續之,根據第1圖之步驟P5:形成一晶種層於凹槽的表面。可如第5圖所示,形成一晶種層140於凹槽R1的表面S1。晶種層140可例如為一矽質層,搭配形成於矽質的基底110上,但本發明不以此為限。在一實施例中,矽質層則可例如以通入二氯甲矽烷(dichlorosilane,DCS)氣體之沈積製程形成,但本發明不以此為限。形成晶種層140於凹槽R1的表面S1可降低後續形成於凹槽中之磊晶結構之錯排等微結構上的缺陷。然而,形成晶種層140之製程一般會具有例如735℃的製程溫度,此溫度確足以更圓弧化凹槽R1的形狀。 Further, according to the step P5 of FIG. 1, a seed layer is formed on the surface of the groove. As shown in Fig. 5, a seed layer 140 is formed on the surface S1 of the recess R1. The seed layer 140 can be, for example, a tantalum layer formed on the substrate 110 of the enamel, but the invention is not limited thereto. In an embodiment, the tantalum layer may be formed, for example, by a deposition process of dichlorosilane (DCS) gas, but the invention is not limited thereto. Forming the seed layer 140 on the surface S1 of the recess R1 can reduce defects on microstructures such as staggered epitaxial structures formed in the recesses. However, the process of forming the seed layer 140 will typically have a process temperature of, for example, 735 ° C, which is sufficient to more round the shape of the recess R1.

在於凹槽的表面形成晶種層之後,根據第1圖之步驟P6:進行一表面改質製程於凹槽的一表面,以整修凹槽的形狀並將表面 改質。可如第6圖所示,進行一表面改質製程E3於凹槽R1的表面S1,以使凹槽R1重新形成為原來之第3圖所示之凹槽R的形狀,其具有一鑽石形的剖面結構,且具有複數個完整的尖角T以對於閘極通道C疊加局部應力。在本實施例,進行表面改質製程E3係為將凹槽R1的形狀重新恢復為原來蝕刻後之凹槽R之形狀;換言之,使蝕刻後之凹槽R之形狀,不會因為後續各種製程的影響而變形,但本發明不以此為限。在其他實施例中,表面改質製程E3可用來改變凹槽R1之形狀至另一所需之凹槽形狀,俾使所形成之電晶體等結構能達到所需之電性要求。 After the seed layer is formed on the surface of the groove, according to step P6 of FIG. 1 , a surface modification process is performed on a surface of the groove to reshape the shape of the groove and to surface Upgraded. As shown in FIG. 6, a surface modification process E3 is performed on the surface S1 of the groove R1 to reform the groove R1 into the shape of the groove R shown in the original figure 3, which has a diamond shape. The cross-sectional structure has a plurality of complete sharp corners T to superimpose local stress on the gate channel C. In this embodiment, the surface modification process E3 is performed to restore the shape of the groove R1 to the shape of the groove R after the original etching; in other words, the shape of the groove R after etching is not caused by subsequent processes. The effect is deformed, but the invention is not limited thereto. In other embodiments, the surface modification process E3 can be used to change the shape of the recess R1 to another desired groove shape so that the formed transistor or the like can achieve the desired electrical requirements.

具體而言,本實施例之表面改質製程為一同步蝕刻暨沈積製程;也就是說,此製程在蝕刻凹槽R1之表面S1的同時,也進行沈積製程。蝕刻的主要目的係為恢復為凹槽R的形狀(或將凹槽R1改變為其他所需之形狀),而沈積的主要目的是為將所需之成分形成於凹槽R的表面S,進而將表面S改質。當然,此二效應亦彼此具有輔助之功能。在一較佳的實施例中,同步蝕刻暨沈積製程對於表面S1的蝕刻率大於沈積率,如此則在表面改質製程E3中不會因沈積作用而額外形成其他之材料層,反而會蝕刻掉被圓弧化(特別是尖角處)的部分,並搭配適度的修補作用,以使凹槽R1之形狀轉變回原先之凹槽R之形狀。因此,表面改質製程E3較佳不會在凹槽R上產生額外之材料厚度。 Specifically, the surface modification process of the embodiment is a synchronous etching and deposition process; that is, the process performs a deposition process while etching the surface S1 of the groove R1. The main purpose of the etching is to restore the shape of the groove R (or change the groove R1 to other desired shape), and the main purpose of the deposition is to form the desired component on the surface S of the groove R, thereby Surface S is modified. Of course, these two effects also have an auxiliary function to each other. In a preferred embodiment, the etching rate of the surface S1 is greater than the deposition rate of the synchronous etching and deposition process. Thus, in the surface modification process E3, no additional material layers are formed by the deposition, but the etching is performed. The portion that is arcuate (especially at the sharp corners) with a moderate repair effect to transform the shape of the groove R1 back to the shape of the original groove R. Therefore, the surface modification process E3 preferably does not create an additional material thickness on the recess R.

詳細而言,一般同步蝕刻暨沈積製程可通入至少一沈積氣體以及至少一蝕刻氣體,在製程的過程中則藉由調整沈積氣體及蝕刻氣體所通入的比例,以控制凹槽R1所欲轉變的形狀,以及改質的成分的濃度。在一較佳的實施例中,蝕刻氣體可例如包含氯化氫 氣體,而沈積氣體可例如包含鍺氣體(或者更包含二氯甲矽烷氣體),用以搭配後續形成矽鍺磊晶結構於凹槽R中。例如,鍺氣體:二氯甲矽烷氣體:氯化氫氣體的比例可介於1:1:1或0:1:1之間。如此一來,可一方面以氯化氫氣體蝕刻表面S1之圓弧化後多餘的部分,另一方面又微量地沈積含鍺成分於表面S1,如此可改變表面S1之物質含量,進而使表面S含鍺,而可作為後續形成矽鍺磊晶結構之緩衝。在其他實施例中,蝕刻氣體例如可通入氟化氫(hydrogen fluoride,HF)、氟氣(fluorine,F2)、溴化氫(hydrogen bromide,HBr)、溴氣(bromine,Br2)等可蝕刻矽質材料等氣體。另外,表面改質製程E3可再包含以氫氣作為承載氣體,俾控制製程氣體總壓,調整製程速率及蝕刻暨沈積的均勻度。在一較佳的實施例中,表面改質製程E3的製程溫度為600℃~750℃,俾能維持製程速率以有效改質但又不會影響所欲形成之凹槽R之形狀,但本發明不以此為限。 In detail, the general synchronous etching and deposition process can pass at least one deposition gas and at least one etching gas, and the ratio of the deposition gas and the etching gas is adjusted during the process to control the groove R1. The shape of the transformation, as well as the concentration of the modified components. In a preferred embodiment, the etching gas may, for example, comprise hydrogen chloride gas, and the deposition gas may, for example, comprise helium gas (or more methylene chloride gas) for use in conjunction with subsequent formation of a germanium epitaxial structure in the recess R. in. For example, the ratio of helium gas: methylene chloride gas: hydrogen chloride gas may be between 1:1:1 or 0:1:1. In this way, on the one hand, the excess portion of the arc of the surface S1 can be etched with hydrogen chloride gas, and on the other hand, the strontium-containing component is deposited on the surface S1 in a trace amount, so that the content of the surface S1 can be changed, thereby making the surface S contain锗, but can be used as a buffer for the subsequent formation of 矽锗 epitaxial structure. In other embodiments, the etching gas may be etched by, for example, hydrogen fluoride (HF), fluorine (F2), hydrogen bromide (HBr), bromine (Br 2 ), or the like. Gas such as material. In addition, the surface modification process E3 may further comprise hydrogen as a carrier gas, and control the total process gas pressure, adjust the process rate and the uniformity of etching and deposition. In a preferred embodiment, the process temperature of the surface modification process E3 is 600 ° C ~ 750 ° C, and the process can maintain the process rate to effectively modify without affecting the shape of the groove R to be formed, but The invention is not limited to this.

再者,如前所述當形成晶種層140之製程為通入二氯甲矽烷氣體之沈積製程,則可繼續在同一製程腔體中通入氯化氫氣體以及鍺氣體,即可原位(in-situ)進行表面改質製程E3。換言之,較佳者將形成晶種層140之製程與表面改質製程E3以在同一製程腔體中進行可提升製程效率,其又更佳包含在形成晶種層140與進行表面改質製程E3時僅藉由通入不同氣體即可達成。 Furthermore, as described above, when the process for forming the seed layer 140 is a deposition process for introducing methylene chloride gas, the hydrogen chloride gas and the helium gas may continue to be introduced into the same process chamber, thereby being in situ (in -situ) Perform a surface modification process E3. In other words, the process of forming the seed layer 140 and the surface modification process E3 are preferably performed to improve the process efficiency in the same process cavity, and more preferably included in the formation of the seed layer 140 and the surface modification process E3. This can only be achieved by introducing different gases.

繼之,根據第1圖之步驟P7:形成一磊晶結構於凹槽中。可如第7圖所示,形成一磊晶結構150於凹槽R中。在本實施例中,磊晶結構150為一矽鍺磊晶結構,其如前所述,較佳為搭配含鍺氣的表面改質製程E3,俾使凹槽R表面S含有鍺成分,可更易於磊晶結構150與凹槽R之表層成分鍵結,並降低介面缺陷,但本發明不 以此為限。在其他實施例中,如為形成例如矽碳磊晶結構或矽磷磊晶結構等其他磊晶結構,則較佳使沈積氣體與磊晶結構之組成物至少之一相同,則可有助於後續磊晶結構之形成。另外,磊晶結構150可藉由所通入之鍺等成分的濃度不同,由內至外或/且由下至上具有多層濃度不同的包覆結構。之後,可再進行後續之半導體製程,例如金屬閘極置換製程等。 Then, according to step P7 of FIG. 1, an epitaxial structure is formed in the recess. As shown in FIG. 7, an epitaxial structure 150 may be formed in the recess R. In the present embodiment, the epitaxial structure 150 is a tantalum epitaxial structure. As described above, it is preferably matched with the surface modification process E3 containing helium, so that the surface S of the groove R contains a germanium component. It is easier to bond the epitaxial structure 150 to the surface layer of the recess R and reduce interface defects, but the present invention does not This is limited to this. In other embodiments, if other epitaxial structures such as a germanium carbon epitaxial structure or a germanium phosphorite epitaxial structure are formed, it is preferred that at least one of the deposition gas and the epitaxial structure be the same, which may contribute to Subsequent formation of epitaxial structures. In addition, the epitaxial structure 150 may have a plurality of cladding structures having different layers from the inside to the outside or/and from the bottom to the top by different concentrations of the components such as the enthalpy. Thereafter, subsequent semiconductor processes, such as metal gate replacement processes, can be performed.

縱上所述,本發明提出一種半導體製程,其藉由進行一表面改質製程,俾整修凹槽之形狀並將凹槽表面改質。例如,經由表面改質製程可恢復原先所蝕刻出之凹槽形狀,其可能在蝕刻後的各項製程中因各種製程環境所影響而改變;再者,可將凹槽表面改質成至少具有部分之磊晶結構之含量,則可方便二者之鍵結並減少介面缺陷。然而,改質之目的亦可能為其他之考量,本發明不限於此,視實際所需而定。 In the above, the present invention proposes a semiconductor process in which the shape of the groove is trimmed and the surface of the groove is modified by performing a surface modification process. For example, the shape of the originally etched groove can be restored through a surface modification process, which may be changed in various processes after etching due to various process environments; further, the groove surface may be modified to have at least The content of part of the epitaxial structure facilitates the bonding of the two and reduces interface defects. However, the purpose of the modification may also be other considerations, and the present invention is not limited thereto, and may be determined according to actual needs.

在一較佳實施例中,表面改質製程為一同步蝕刻暨沈積製程,其通入至少一沈積氣體以及至少一蝕刻氣體,並在製程中可藉由調整沈積氣體以及蝕刻氣體的比例,以控制所形成之凹槽形狀以及凹槽表面的物質含量。舉例而言,可先選擇性通入二氯甲矽烷氣體以形成晶種層覆蓋凹槽的表面;然後在同一製程中又通入鍺氣作為沈積氣體,以及氯化氫作為蝕刻氣體,以進行表面改質製程;之後再形成矽鍺磊晶結構於凹槽中。如此搭配,由於形成晶種層以及進行表面改質製程在同一製程腔體中進行,故可提升製程速率。再者,由於在進行表面改質製程時通入鍺氣使凹槽表面已含有鍺成分,故可促進磊晶結構之成長,減少介面缺陷以及改善介面鍵結,進而增進所形成之元件可靠度。 In a preferred embodiment, the surface modification process is a synchronous etching and deposition process, in which at least one deposition gas and at least one etching gas are introduced, and in the process, the ratio of the deposition gas and the etching gas can be adjusted by The shape of the groove formed and the substance content of the surface of the groove are controlled. For example, the methylene chloride gas can be selectively introduced to form a seed layer covering the surface of the groove; then, in the same process, helium gas is introduced as a deposition gas, and hydrogen chloride is used as an etching gas to perform surface modification. The quality process is followed by the formation of a germanium epitaxial structure in the recess. In this way, since the seed layer is formed and the surface modification process is performed in the same process chamber, the process rate can be improved. Furthermore, since the surface of the groove already contains a bismuth component during the surface modification process, the growth of the epitaxial structure can be promoted, the interface defects can be reduced, and the interface bonding can be improved, thereby improving the reliability of the formed component. .

110‧‧‧基底 110‧‧‧Base

120‧‧‧閘極 120‧‧‧ gate

122‧‧‧介電層 122‧‧‧ dielectric layer

124‧‧‧電極層 124‧‧‧electrode layer

126‧‧‧蓋層 126‧‧‧ cover

130‧‧‧間隙壁 130‧‧‧ spacer

C‧‧‧閘極通道 C‧‧‧gate channel

E3‧‧‧表面改質製程 E3‧‧‧Surface modification process

R‧‧‧凹槽 R‧‧‧ groove

S‧‧‧表面 S‧‧‧ surface

T‧‧‧尖角 T‧‧‧ sharp corner

Claims (19)

一種半導體製程,包含有:形成一閘極於一基底上;形成一凹槽於該閘極側邊的該基底中;進行一表面改質製程於該凹槽的一表面,以整修該凹槽的形狀並將該表面改質;以及在進行該表面改質製程之前,形成一晶種層於該凹槽的該表面。 A semiconductor process includes: forming a gate on a substrate; forming a recess in the substrate on a side of the gate; performing a surface modification process on a surface of the recess to refurbish the recess Shape and modifying the surface; and forming a seed layer on the surface of the recess prior to performing the surface modification process. 如申請專利範圍第1項所述之半導體製程,在進行該表面改質製程之後,更包含:形成一磊晶結構於該凹槽中。 The semiconductor process of claim 1, after performing the surface modification process, further comprising: forming an epitaxial structure in the recess. 如申請專利範圍第2項所述之半導體製程,其中該磊晶結構包含一矽鍺磊晶結構。 The semiconductor process of claim 2, wherein the epitaxial structure comprises a germanium epitaxial structure. 如申請專利範圍第1項所述之半導體製程,其中該表面改質製程包含一同步蝕刻暨沈積製程。 The semiconductor process of claim 1, wherein the surface modification process comprises a synchronous etching and deposition process. 如申請專利範圍第4項所述之半導體製程,其中該同步蝕刻暨沈積製程對於該表面的蝕刻率大於沈積率。 The semiconductor process of claim 4, wherein the simultaneous etching and deposition process has an etch rate for the surface greater than a deposition rate. 如申請專利範圍第4項所述之半導體製程,其中該同步蝕刻暨沈積製程係通入至少一沈積氣體以及至少一蝕刻氣體。 The semiconductor process of claim 4, wherein the synchronous etching and deposition process is coupled to at least one deposition gas and at least one etching gas. 如申請專利範圍第6項所述之半導體製程,在進行該表面改質製程之後,更包含: 形成一磊晶結構於該凹槽中,且該沈積氣體與該磊晶結構之組成物之一相同。 The semiconductor process as described in claim 6 of the patent application, after performing the surface modification process, further comprises: An epitaxial structure is formed in the recess, and the deposition gas is the same as one of the constituents of the epitaxial structure. 如申請專利範圍第6項所述之半導體製程,其中該同步蝕刻暨沈積製程係通入鍺氣體及氯化氫氣體。 The semiconductor process of claim 6, wherein the synchronous etching and deposition process is performed by introducing helium gas and hydrogen chloride gas. 如申請專利範圍第8項所述之半導體製程,其中在進行該同步蝕刻暨沈積製程時,藉由調整該鍺氣體及該氯化氫氣體所通入的比例,以控制該凹槽的形狀。 The semiconductor process of claim 8, wherein during the synchronous etching and deposition process, the shape of the groove is controlled by adjusting a ratio of the helium gas and the hydrogen chloride gas. 如申請專利範圍第4項所述之半導體製程,其中該同步蝕刻暨沈積製程更包含通入二氯甲矽烷氣體。 The semiconductor process of claim 4, wherein the synchronous etching and deposition process further comprises introducing methylene chloride gas. 如申請專利範圍第4項所述之半導體製程,其中該同步蝕刻暨沈積製程的製程溫度為600℃~750℃。 The semiconductor process of claim 4, wherein the process temperature of the synchronous etching and deposition process is 600 ° C to 750 ° C. 如申請專利範圍第1項所述之半導體製程,其中形成該晶種層與進行該表面改質製程於同一製程腔體。 The semiconductor process of claim 1, wherein the seed layer is formed and the surface modification process is performed in the same process chamber. 如申請專利範圍第12項所述之半導體製程,其中形成該晶種層與進行該表面改質製程係通入不同氣體。 The semiconductor process of claim 12, wherein the seed layer is formed and a different gas is introduced into the surface modification process. 如申請專利範圍第1項所述之半導體製程,其中該晶種層包含一矽質層。 The semiconductor process of claim 1, wherein the seed layer comprises a tantalum layer. 如申請專利範圍第1項所述之半導體製程,在進行該表面改質製程之前,更包含: 進行一氫氣烘烤製程,於該凹槽。 The semiconductor process as described in claim 1 of the patent application, before performing the surface modification process, further comprises: A hydrogen baking process is performed in the groove. 如申請專利範圍第15項所述之半導體製程,在進行該氫氣烘烤製程之後,更包含:進行一蝕刻製程,於該凹槽。 The semiconductor process of claim 15, wherein after performing the hydrogen baking process, further comprising: performing an etching process on the recess. 如申請專利範圍第16項所述之半導體製程,其中該蝕刻製程係包含通入氯化氫氣體或氯氣。 The semiconductor process of claim 16, wherein the etching process comprises introducing hydrogen chloride gas or chlorine gas. 如申請專利範圍第16項所述之半導體製程,其中該蝕刻製程的製程溫度低於720℃。 The semiconductor process of claim 16, wherein the process temperature of the etching process is lower than 720 °C. 如申請專利範圍第1項所述之半導體製程,其中該凹槽具有一鑽石形的剖面結構。 The semiconductor process of claim 1, wherein the groove has a diamond-shaped cross-sectional structure.
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