TWI615888B - 非對稱半導體裝置及其形成方法 - Google Patents

非對稱半導體裝置及其形成方法 Download PDF

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TWI615888B
TWI615888B TW105123413A TW105123413A TWI615888B TW I615888 B TWI615888 B TW I615888B TW 105123413 A TW105123413 A TW 105123413A TW 105123413 A TW105123413 A TW 105123413A TW I615888 B TWI615888 B TW I615888B
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安東尼Ｉ 邱
朱德尚Ｒ 侯爾特
艾維恩德 卡瑪
亨利Ｋ 烏托摩
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格羅方德半導體公司
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Abstract

本發明的態樣提供非對稱半導體裝置。該非對稱半導體裝置可包括：基板；以及設於該基板上的鰭式場效電晶體(FINFET)，該FINFET包括：鄰近閘極設置的一組鰭片；設於該組鰭片的源極區上的第一磊晶區，該第一磊晶區具有第一高度；以及設於該組鰭片的汲極區上的第二磊晶區，該第二磊晶區具有第二高度，其中，該第一高度不同於該第二高度。

Description

非對稱半導體裝置及其形成方法
本發明關於非對稱半導體裝置，尤其關於非對稱鰭式場效電晶體(fin-shaped field effect transistor；FINFET)及其形成方法。
外部電阻及邊緣電容降低FINFET裝置的性能。磊晶區設於FINFET裝置的源極及汲極上方。通常，這些磊晶區具有相同的尺寸(例如寬度及高度)。然而，基於該磊晶區的尺寸，在裝置電阻與裝置電容之間有權衡取捨。尤其，當磊晶區的尺寸增加時，其具有較低的擴散電阻但較高的擴散電容。當磊晶區的尺寸減小時，其具有較高的擴散電阻但較低的擴散電容。
本發明的第一態樣提供一種非對稱半導體裝置。該非對稱半導體裝置可包括：基板；以及設於該基板上的鰭式場效電晶體(FINFET)，該FINFET包括：鄰近閘極設置的一組鰭片；設於該組鰭片的源極區上的第一磊晶區，該第一磊晶區具有第一高度；以及設於該組鰭片的汲 極區上的第二磊晶區，該第二磊晶區具有第二高度，其中，該第一高度不同於該第二高度。
本發明的第二態樣提供一種形成非對稱半導體裝置的方法。該方法可包括：在基板上形成鰭式場效電晶體(FINFET)，該FINFET具有與一組鰭片垂直的閘極，各鰭片具有位於該閘極的相對側上的源極區及汲極區；以及形成位於各鰭片的該源極區上的第一磊晶區以及位於各鰭片的該汲極區上的第二磊晶區，其中，該第一磊晶區具有第一高度，該第一高度不同於該第二磊晶區的第二高度。
本發明的第三態樣提供一種形成非對稱半導體裝置的方法。該方法可包括：在基板上形成鰭片；垂直於該基板上的該鰭片形成閘極堆疊；形成一對間隔物，各間隔物位於該閘極堆疊的相對側上；形成位於該閘極堆疊的一側上的源極區以及位於該閘極堆疊的相對側上的汲極區；以及形成位於該源極上的第一磊晶區以及位於該汲極上的第二磊晶區，其中，該第一磊晶區具有第一高度，該第一高度不同於該第二磊晶區的第二高度。
102、202‧‧‧基板
104、204‧‧‧埋置氧化物層
106‧‧‧矽層
110、210‧‧‧FINFET
120、220‧‧‧鰭片
130、230‧‧‧閘極堆疊
138、238‧‧‧間隔物
142、242‧‧‧源極
144、244‧‧‧汲極
150‧‧‧遮罩
152、252‧‧‧第一區
154‧‧‧第一材料
160‧‧‧磊晶層
162、262‧‧‧第一磊晶區
164、264‧‧‧第二磊晶區
206‧‧‧SOI層
250‧‧‧第一遮罩
254‧‧‧第二遮罩
256‧‧‧第二區
將通過參照下面的附圖來詳細說明本發明的實施例，該些附圖中相同的元件符號表示類似的元件，以及其中：第1圖顯示FINFET的頂視圖。
第2圖顯示第1圖的FINFET沿線A-A所作的剖視圖。
第3至7圖顯示經歷本文中所述的方法的態樣的第2圖的剖視圖。
第8圖顯示在經歷本文中所述的方法的態樣以後，第1圖的FINFET沿線B-B所作的剖視圖。
第9圖顯示在經歷本文中所述的方法的態樣以後，第1圖的FINFET沿線C-C所作的剖視圖。
第10至12圖顯示經歷本文中所述的另一種方法的態樣的第2圖的剖視圖。
本發明的態樣提供非對稱半導體裝置，尤其是非對稱鰭式場效電晶體(FINFET)。已發現，與較低的汲極電阻相比，較低的源極電阻對於裝置性能更為重要，而與較低的閘極-源極電容相比，較低的閘極-汲極電容對於裝置性能更為重要。當磊晶區的尺寸增加時，具有較低的源極-汲極電阻但較高的閘極-源極以及較高的閘極-汲極電容。當磊晶區的尺寸減小時，具有較高的源極-汲極電阻但較低的閘極-源極以及較低的閘極-汲極電容。具體地說，本發明的實施例提供與汲極上方的磊晶區相比，位於源極上方的磊晶區具有較大的高度，從而形成非對稱結構。如本文中所述的FINFET的該非對稱結構，因該源極相對該汲極上的外部電阻及邊緣電容的不同優化而導致該FINFET具有較好的裝置性能。
第1圖示意顯示包括FINFET 110的基板102的部分(例如積體電路的部分)(以虛線表示)的頂視圖， FINFET 110包括與閘極130垂直並連接的多個鰭片120。第2圖顯示FINFET 110沿第1圖的線A-A(平行於鰭片120)所作的剖視圖。本文中將說明的形成非對稱半導體裝置的方法可開始於在基板102上形成FINFET 110。如本文中將說明的那樣，FINFET 110可具有與多個鰭片120垂直的多個閘極堆疊130，且各鰭片可具有源極142及汲極144。
FINFET 110可通過現有技術中已知的任意方法形成。例如，FINFET 110可通過形成基板102來形成。基板102可包括任意傳統半導體基板材料，包括但不限於矽、鍺、矽鍺、碳化矽以及基本由具有由式AlX1GaX2InX3AsY1PY2NY3SbY4定義的組成的一種或多種III-V族化合物半導體組成的物質，其中，X1、X2、X3、Y1、Y2、Y3及Y4表示相對比例，分別大於或等於0且X1+X2+X3+Y1+Y2+Y3+Y4=1(1是總的相對摩爾量)。其它合適的基板包括具有組成ZnA1CdA2SeB1TeB2的II-VI族化合物半導體，其中，A1、A2、B1及B2是相對比例，分別大於或等於零，且A1+A2+B1+B2=1(1是總的摩爾量)。而且，半導體基板102的部分或全部可經應變。
在基板102上方可為埋置氧化物層104，其可由任意傳統氧化物材料形成，例如二氧化矽(SiO2)。在埋置氧化物層104上方可為絕緣體上矽(silicon-on-insulator；SOI)層106，其可包括矽、矽鍺、或任意合適的半導體。在依據本發明的各種實施例所述的製造方法之前，依據傳統的SOI晶圓形成技術(例如晶圓結合或氧注入等)可分別 在埋置氧化物層104上方形成SOI層106以及在基板102上方形成埋置氧化物層104。應當理解，當作為層、區或基板的元件被稱為在另一個元件“上”或“上方”時，它可直接位於該另一個元件上或者可存在中間元件。還應當理解，當一個元件被稱為與另一個元件“連接”或“耦接”時，它可與該另一個元件直接連接或耦接，或者可存在中間元件。如本文中所使用的那樣，且除非另外指出，否則術語“沉積”可包括適於材料沉積的任意當前已知或以後開發的技術，包括但不限於例如：化學氣相沉積(chemical vapor deposition；CVD)、低壓CVD(low-pressure CVD；LPCVD)、電漿增強型CVD(plasma-enhanced CVD；PECVD)、半大氣壓CVD(semi-atmosphere CVD；SACVD)以及高密度電漿CVD(high density plasma CVD；HDPCVD)、快速加熱CVD(rapid thermal CVD；RTCVD)、超高真空CVD(ultra-high vacuum CVD；UHVCVD)、限制反應處理CVD(limited reaction processing CVD；LRPCVD)、金屬有機CVD(metalorganic CVD；MOCVD)、濺鍍沉積、離子束沉積、電子束沉積、鐳射輔助沉積、熱氧化、熱氮化、旋塗方法、物理氣相沉積(physical vapor desposition；PVD)、原子層沉積(atomic layer deposition；ALD)、化學氧化、分子束磊晶(molecular beam epitaxy；MBE)、電鍍、蒸鍍。
在基板102上方(尤其在埋置氧化物層104上方)可形成一組鰭片120。該組鰭片120可例如通過現有技術中已知的和/或本文中所述的傳統蝕刻及遮罩技術自 SOI層106形成。在該組鰭片120上方可形成閘極堆疊130。閘極堆疊130將包覆各鰭片120，以形成三閘極結構，該結構為現有技術所已知。閘極堆疊130可包括閘極介電質(未圖示)以及位於該閘極介電質上方的閘極電極(未圖示)。閘極介電質可包括但不限於：二氧化矽、氮氧化矽、金屬氧化物、金屬氮氧化物、金屬矽氧化物、金屬矽氮氧化物、金屬鍺氧化物、金屬鍺氮氧化物，及其合金、混合物或多層，其中，該金屬可選自鋁(Al)、鋇(Ba)、鈹(Be)、鉍(Bi)、碳(C)、鈣(Ca)、鈰(Ce)、鈷(Co)、鉻(Cr)、鏑(Dy)、銪(Eu)、鐵(Fe)、鎵(Ga)、釓(Gd)、鉿(Hf)、銦(In)、鑭(La)、鋰(Li)、鎂(Mg)、錳(Mn)、鉬(Mo)、鈮(Nb)、鎳(Ni)、鐠(Pr)、鈧(Sc)、鍶(Sr)、鉭(Ta)、鈦(Ti)、釩(V)、鎢(W)、釔(Y)、鋅(Zn)以及鋯(Zr)。閘極電極可包括但不限於：多晶矽，或金屬例如鎢(W)、鋁(Al)或其組合，或全矽化(fully silicided；FUSI)閘極。閘極堆疊130可通過現有技術中已知的和/或本文中所述的任意沉積技術形成。應當理解，閘極堆疊130可在先閘極流程中充當實際(最終)閘極堆疊，或者替代地，充當偽(dummy)閘極堆疊，後續適時地以實際閘極堆疊替代該偽閘極堆疊(在後閘極流程中)。
另外，在閘極堆疊130的側壁上方可形成間隔物138，使各鰭片120的側壁及頂部暴露。間隔物138可通過現有技術中已知的任意沉積技術形成。間隔物138可包括但不限於：氧化物或氮化物，例如氮化矽(SiN)或二氧化矽(SiO2)。
在各暴露鰭片120上方可生長磊晶區。FINFET 110還可包括位於各鰭片120中的各閘極堆疊130的相對側上的源極區142及汲極區144。也就是說，源極區142與汲極區144可交替位於FINFET 110的各閘極堆疊130之間。
此時，在包括源極區142及汲極區144的各暴露鰭片上方可生長磊晶區。對於NFET裝置，該磊晶的源極與汲極區可包括但不限於矽(Si)、具有碳濃度約0.1%至約50%的碳化矽(SiC)。這裡所使用的“約”意圖包括例如在所述值的10%範圍內的值。另外，該NFET磊晶區可摻雜有n型摻雜物，例如磷或砷。對於PFET裝置，該磊晶的源極與汲極區可包括但不限於矽(Si)、鍺濃度在約1%至約50%範圍內變化的矽鍺(SiGe)。另外，該PFET磊晶區可摻雜有p型摻雜物，例如硼或銦。不過，傳統技術導致該磊晶區在該源極與汲極區上具有相同的尺寸(例如寬度及高度)。本發明的態樣包括非對稱FINFET，其中，位於源極上方的磊晶區可具有與汲極上方的磊晶區的高度不同的高度。因此，本發明的態樣包括形成位於各鰭片120的源極142上的第一磊晶區162(第7圖)、以及位於各鰭片120的汲極144上的第二磊晶區164(第7圖)，其中，第一磊晶區162具有第一高度H1(第7圖)，該第一高度H1不同於第二磊晶區164的第二高度H2(第7圖)。
請參照第3圖，形成第一及第二磊晶區162、164(第7圖)可包括形成暴露該組鰭片120的第一區 152的遮罩。形成該遮罩可包括在FINFET 110上沉積標準的覆被光阻遮罩150並圖案化遮罩150以暴露FINFET的第一區152。如第3圖中所示，可形成該遮罩以暴露源極142。也就是說，暴露第一區152可包括暴露源極142。不過，在另一個實施例中，如第4圖中所示，可形成該遮罩以暴露汲極144。也就是說，暴露第一區152可包括暴露汲極144。
在任一實施例中，可向第一區152引入第一材料154，如第5至6圖中所示。請參照第5圖，可向源極142引入第一材料154。在此實施例中，第一材料154可為用於源極142的頂部上的後續磊晶生長的促進劑。也就是說，第一材料154可包括促進磊晶區的生長的任意材料。第一材料154可通過離子注入引入，以使源極142注入有第一材料154。例如，第一材料154可包括於通過離子注入引入時破壞源極區142的鍺(Ge)、氙(Xe)或其它種類。此離子注入破壞可部分地非晶化源極區142，且在暴露於約500℃至約1100℃的高溫時可再結晶，以形成多晶矽區，已知該多晶矽區在磊晶沉積期間可促進層的生長。在此實施例中，閘極堆疊130、間隔物138及汲極144被遮罩152覆蓋，因此沒有遭受第一材料154的注入。
請參照第6圖，可向汲極144引入第一材料154。在此實施例中，第一材料154可為抑制劑。也就是說，第一材料154可包括抑制磊晶區的生長的任意材料。例如，當生長PFET矽鍺(SiGe)磊晶區時，第一材料154可包 括硼(B)，因為硼(B)減慢矽鍺(SiGe)磊晶生長。當生長NFET磊晶區時，第一材料154可包括磷(P)，因為磷減慢矽(Si)磊晶生長。第一材料154可通過離子注入引入，以使汲極144注入有第一材料154。在此實施例中，閘極堆疊130、間隔物138及源極142被遮罩152覆蓋，因此沒有遭受第一材料154的注入。
如第7至9圖中所示，可移除遮罩150並可形成磊晶區162、164。依據本發明的實施例，第7圖顯示形成磊晶區162、164以後的第6圖中所示的實施例。第8至9圖顯示第7圖中所示的實施例垂直於FINFET 110的鰭片120並在閘極堆疊130之間所作的剖視圖。第8圖的剖視圖是在FINFET 110已經歷本文中所述的方法的態樣以後沿線B-B(沿第1圖的FINFET 110的源極區142)所作。第9圖的剖視圖是在FINFET 110已經歷本文中所述的方法的態樣以後沿線C-C(沿第1圖的FINFET 110的汲極區144)所作。磊晶區162、164可通過磊晶生長磊晶層160形成。磊晶層160可包括但不限於：用於NFET的矽(Si)，以及用於PFET的矽(Si)或矽鍺(SiGe)。不過，設於源極142上方的第一磊晶區162具有第一高度H1，且設於汲極144上方的第二磊晶區164具有第二高度H2。如這裡所述，“高度”可指從與基板最接近的磊晶區的部分至離基板最遠的磊晶區的部分的距離。第一高度H1可不同於第二高度H2。第一高度H1可大於第二高度H2。例如，第一高度H1可等於約30奈米(nm)至約70奈米。尤其，第一高度H1可為約 50奈米。第二高度H2可等於約20奈米至約60奈米。尤其，第一高度H1可為約40奈米。第一磊晶區162可具有較大的高度，因為源極142注入有促進劑而汲極144沒有，或者汲極144注入有抑制劑而源極142沒有。也就是說，無論在源極142中注入促進劑還是在汲極144中注入抑制劑，磊晶層160都將在第一磊晶區162中以比第二磊晶區164快的速率生長，從而導致較大的高度H1。這樣，FINFET 110因磊晶區162、164的不一致的高度H1、H2而被稱為非對稱。因此，如第7圖中所示，所得的結構可包括設於基板102(尤其是埋置氧化物層104)上的FINFET 110。FINFET可包括鄰近閘極堆疊130設置的一組鰭片120、設於該組鰭片120的源極142上的第一磊晶區162，以及設於該組鰭片120的汲極144上的第二磊晶區164，其中，第一磊晶區162具有第一高度H1，該第一高度H1不同於第二磊晶區164的第二高度H2。
現在將參照第10至12圖說明本發明的另一個態樣。如第10圖中所示，FINFET 210可如現有技術中已知的那樣形成。例如，FINFET 210可如參照第1至2圖所述形成。如第10圖中所示，FINFET 210可包括來自基板202(尤其是埋置氧化物層204)上的SOI層206的一組鰭片220、與鰭片組220垂直並重疊的閘極堆疊230，以及設於閘極堆疊230的相對側上的間隔物238。另外，各鰭片220的源極242及汲極244可設於閘極堆疊230的相對側上。
另外，依據此實施例的揭露的態樣提供形成位於各鰭片220的源極242上的第一磊晶區262以及位於各鰭片220的汲極244上的第二磊晶區264(第11圖)，其中，第一磊晶區262具有第一高度H1a，該第一高度H1a不同於第二磊晶區264的第二高度H2a(第11圖)。磊晶區262、264可通過磊晶生長磊晶層260形成。如第10圖中所示，形成第一及第二磊晶區262、264可包括在FINFET 210上形成第一遮罩250。形成該第一遮罩可包括在FINFET 210上形成第一遮罩250並圖案化第一遮罩250以暴露該組鰭片220的第一區252。如第10圖中所示，第一區252可包括源極242。第一區252一經暴露，即可在源極242上生長第一磊晶區262。可如現有技術中已知的那樣磊晶生長第一磊晶區262。第一磊晶區262可生長至第一高度H1a。第一高度H1a可基本等於約30奈米至約70奈米，或者尤其約50奈米。
第一磊晶區262一經形成，即可移除第一遮罩250並可形成第二遮罩254，如第11圖所示。形成該第二遮罩可包括在FINFET 210上方形成第二遮罩254並圖案化第二遮罩254以暴露FINFET 210的第二區256。如第11圖中所示，第二區256可包括汲極244。第二區256一經暴露，即可在汲極244上生長第二磊晶區264。可如現有技術已知的那樣磊晶生長第二磊晶區264。不過，第二磊晶區264可生長至第二高度H2a。第二高度H2a可等於約20奈米至約60奈米，或者尤其約40奈米。在任何情況下， 第二高度H2a小於第一高度H1a。
如第12圖中所示，可移除遮罩254。因此，所得的結構可包括設於基板202(尤其埋置氧化物層204)上的FINFET 210。FINFET 210可包括鄰近閘極堆疊230設置的一組鰭片220、設於該組鰭片220的源極242上的第一磊晶區262，以及設於該組鰭片220的汲極244上的第二磊晶區264。第一磊晶區262可具有第一高度H1a，該第一高度H1a不同於第二磊晶區264的第二高度H2a。
應當理解，在與參照第9至12圖所述的實施例類似的替代實施例中(未圖示)，可形成第一遮罩以暴露汲極244而不是源極242，且可形成第二遮罩以暴露源極242而不是汲極244。在此實施例中，汲極上方的磊晶區264可生長至第一高度，該第一高度小於源極上方的磊晶區262的生長。不過，在任一實施例中，源極242會具有大於H2a的高度H1a。也就是說，無論遮罩步驟採用哪種順序，源極242上方的第一磊晶區262的磊晶生長將使第一磊晶區262具有大於第二磊晶區264的高度H2a。
本文中所使用的術語僅是出於說明特定實施例的目的，並非意圖限制本發明。除非上下文中另外明確指出，否則本文中所使用的單數形式“一”、“一個”以及“該”也意圖包括複數形式。另外，應當理解，術語“包括”或“包含”用於本說明書中時表明所述特徵、整體、步驟、操作、元件和/或元件的存在，但不排除存在或添加一個或多個其它特徵、整體、步驟、操作、元件、元 件、和/或其群組。
對本發明的各種實施例的說明是出於示例目的，而非意圖詳盡無遺或限於所揭露的實施例。許多修改及變更將對於本領域的普通技術人員顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理，實際應用或在市場已知技術上的技術改進，或者使本領域的普通技術人員能夠理解本文中所揭露的實施例。
102‧‧‧基板
104‧‧‧埋置氧化物層
106‧‧‧矽層
110‧‧‧FINFET
120‧‧‧鰭片
130‧‧‧閘極堆疊
138‧‧‧間隔物
142‧‧‧源極
144‧‧‧汲極
160‧‧‧磊晶層
162‧‧‧第一磊晶區
164‧‧‧第二磊晶區

Claims (9)

  1. 一種非對稱半導體裝置，包括：基板；以及鰭式場效電晶體(FINFET)，設於該基板上，該FINFET包括：一組鰭片，鄰近閘極設置；第一磊晶區，設於該組鰭片的源極區上，該第一磊晶區具有第一高度；以及第二磊晶區，設於該組鰭片的汲極區上，該第二磊晶區具有第二高度，其中，該第一高度等於約30奈米(nm)至約70奈米，且該第二高度等於約20奈米至約60奈米。
  2. 如申請專利範圍第1項所述的非對稱半導體裝置，其中，該汲極區離子注入有抑制劑。
  3. 如申請專利範圍第1項所述的非對稱半導體裝置，其中，該源極區離子注入有促進劑。
  4. 一種形成非對稱半導體裝置的方法，該方法包括：在基板上形成鰭式場效應電晶體(FINFET)，該FINFET具有與一組鰭片垂直的閘極，各鰭片具有位於該閘極的相對側上的源極區及汲極區；以及在各鰭片的該源極區上形成第一磊晶區以及在各鰭片的該汲極區上形成第二磊晶區，其中，該第一磊晶區具有第一高度，該第一高度不同於該第二磊晶區的第二高度，其中，所述形成該第一磊晶區及第二磊晶區包 括：在該組鰭片上形成第一遮罩，以暴露該組鰭片的第一區；在該暴露第一區上生長第一磊晶層；自該組鰭片移除該第一遮罩；在該組鰭片上形成第二遮罩，以暴露該組鰭片的第二區；以及在該暴露第二區上生長第二磊晶層。
  5. 如申請專利範圍第4項所述的方法，其中，所述生長該第一磊晶層包括生長該第一磊晶層至第一高度，以及所述生長該第二磊晶層包括生長該第二磊晶層至第二高度，該第一高度大於該第二高度。
  6. 如申請專利範圍第4項所述的方法，其中，所述生長該第一磊晶層包括生長該第一磊晶層至第一高度，以及所述生長該第二磊晶層包括生長該第二磊晶層至第二高度，該第一高度小於該第二高度。
  7. 一種形成非對稱半導體裝置的方法，該方法包括：在基板上形成鰭片；垂直於該基板上的該鰭片形成閘極堆疊；形成一對間隔物，各間隔物位於該閘極堆疊的相對側上；形成位於該閘極堆疊的一側上的源極區以及位於該閘極堆疊的相對側上的汲極區；以及在該源極上形成第一磊晶區以及在該汲極上形成 第二磊晶區，其中，該第一磊晶區具有第一高度，該第一高度不同於該第二磊晶區的第二高度，其中，所述形成該第一磊晶區及第二磊晶區包括：在該鰭片上形成第一遮罩，以暴露該鰭片的第一區；在該暴露第一區上生長第一磊晶層；自該鰭片移除該第一遮罩；在該鰭片上形成第二遮罩，以暴露該鰭片的第二區；以及在該暴露第二區上生長第二磊晶層。
  8. 如申請專利範圍第7項所述的方法，其中，所述生長該第一磊晶層包括生長該第一磊晶層至第一高度，以及所述生長該第二磊晶層包括生長該第二磊晶層至第二高度，該第一高度大於該第二高度。
  9. 如申請專利範圍第7項所述的方法，其中，所述生長該第一磊晶層包括生長該第一磊晶層至第一高度，以及所述生長該第二磊晶層包括生長該第二磊晶層至第二高度，該第一高度小於該第二高度。
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