CN107068752A - 不对称半导体装置及其形成方法 - Google Patents

不对称半导体装置及其形成方法 Download PDF

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CN107068752A
CN107068752A CN201610818441.1A CN201610818441A CN107068752A CN 107068752 A CN107068752 A CN 107068752A CN 201610818441 A CN201610818441 A CN 201610818441A CN 107068752 A CN107068752 A CN 107068752A
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CN107068752B (zh
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A·I·朱
J·R·霍尔特
A·库马尔
H·K·乌托莫
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GlobalFoundries US Inc
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Abstract

本发明的态样提供不对称半导体装置及其形成方法。该不对称半导体装置可包括：衬底；以及设于该衬底上的鳍式场效应晶体管(FINFET)，该FINFET包括：邻近栅极设置的一组鳍片；设于该组鳍片的源极区上的第一外延区，该第一外延区具有第一高度；以及设于该组鳍片的漏极区上的第二外延区，该第二外延区具有第二高度，其中，该第一高度不同于该第二高度。

Description

不对称半导体装置及其形成方法
技术领域
本发明涉及不对称半导体装置，尤其涉及不对称鳍式场效应晶体管(fin-shapedfield effect transistor；FINFET)及其形成方法。
背景技术
外部电阻及边缘电容降低FINFET装置的性能。外延区设于FINFET装置的源极及漏极上方。通常，这些外延区具有相同的尺寸(例如宽度及高度)。然而，基于该外延区的尺寸，在装置电阻与装置电容之间有权衡取舍。尤其，当外延区的尺寸增加时，其具有较低的扩散电阻但较高的扩散电容。当外延区的尺寸减小时，其具有较高的扩散电阻但较低的扩散电容。
发明内容
本发明的第一态样提供一种不对称半导体装置。该不对称半导体装置可包括：衬底；以及设于该衬底上的鳍式场效应晶体管(FINFET)，该FINFET包括：邻近栅极设置的一组鳍片；设于该组鳍片的源极区上的第一外延区，该第一外延区具有第一高度；以及设于该组鳍片的漏极区上的第二外延区，该第二外延区具有第二高度，其中，该第一高度不同于该第二高度。
本发明的第二态样提供一种形成不对称半导体装置的方法。该方法可包括：在衬底上形成鳍式场效应晶体管(FINFET)，该FINFET具有与一组鳍片垂直的栅极，各鳍片具有位于该栅极的相对侧上的源极区及漏极区；以及形成位于各鳍片的该源极区上的第一外延区以及位于各鳍片的该漏极区上的第二外延区，其中，该第一外延区具有第一高度，该第一高度不同于该第二外延区的第二高度。
本发明的第三态样提供一种形成不对称半导体装置的方法。该方法可包括：在衬底上形成鳍片；垂直于该衬底上的该鳍片形成栅极堆叠；形成一对间隙壁，各间隙壁位于该栅极堆叠的相对侧上；形成位于该栅极堆叠的一侧上的源极区以及位于该栅极堆叠的相对侧上的漏极区；以及形成位于该源极上的第一外延区以及位于该漏极上的第二外延区，其中，该第一外延区具有第一高度，该第一高度不同于该第二外延区的第二高度。
附图说明
将通过参照下面的附图来详细说明本发明的实施例，该些附图中类似的附图标记表示类似的元件，以及其中：
图1显示FINFET的顶视图。
图2显示图1的FINFET沿线A-A所作的剖视图。
图3至7显示经历本文中所述的方法的态样的图2的剖视图。
图8显示在经历本文中所述的方法的态样以后，图1的FINFET沿线B-B所作的剖视图。
图9显示在经历本文中所述的方法的态样以后，图1的FINFET沿线C-C所作的剖视图。
图10至12显示经历本文中所述的另一种方法的态样的图2的剖视图。
具体实施方式
本发明的态样提供不对称半导体装置，尤其是不对称鳍式场效应晶体管(FINFET)。已发现，与较低的漏极电阻相比，较低的源极电阻对于装置性能更为重要，而与较低的栅极-源极电容相比，较低的栅极-漏极电容对于装置性能更为重要。当外延区的尺寸增加时，具有较低的源极-漏极电阻但较高的栅极-源极以及较高的栅极-漏极电容。当外延区的尺寸减小时，具有较高的源极-漏极电阻但较低的栅极-源极以及较低的栅极-漏极电容。具体地说，本发明的实施例提供与漏极上方的外延区相比，位于源极上方的外延区具有较大的高度，从而形成不对称结构。如本文中所述的FINFET的该不对称结构，因该源极相对该漏极上的外部电阻及边缘电容的不同优化而导致该FINFET具有较好的装置性能。
图1示意显示包括FINFET 110的衬底102的部分(例如集成电路的部分)(以虚线表示)的顶视图，FINFET 110包括与栅极130垂直并连接的多个鳍片120。图2显示FINFET 110沿图1的线A-A(平行于鳍片120)所作的剖视图。本文中将说明的形成不对称半导体装置的方法可开始于在衬底102上形成FINFET 110。如本文中将说明的那样，FINFET 110可具有与多个鳍片120垂直的多个栅极堆叠130，且各鳍片可具有源极142及漏极144。
FINFET 110可通过现有技术中已知的任意方法形成。例如，FINFET 110可通过形成衬底102来形成。衬底102可包括任意传统半导体衬底材料，包括但不限于硅、锗、硅锗、碳化硅以及基本由具有由式AlX1GaX2InX3AsY1PY2NY3SbY4定义的组成的一种或多种III-V族化合物半导体组成的物质，其中，X1、X2、X3、Y1、Y2、Y3及Y4表示相对比例，分别大于或等于0且X1+X2+X3+Y1+Y2+Y3+Y4＝1(1是总的相对摩尔量)。其它合适的衬底包括具有组成ZnA1CdA2SeB1TeB2的II-VI族化合物半导体，其中，A1、A2、B1及B2是相对比例，分别大于或等于零，且A1+A2+B1+B2＝1(1是总的摩尔量)。而且，半导体衬底102的部分或全部可经应变。
在衬底102上方可为埋置氧化物层104，其可由任意传统氧化物材料形成，例如二氧化硅(SiO2)。在埋置氧化物层104上方可为绝缘体上硅(silicon-on-insulator；SOI)层106，其可包括硅、硅锗、或任意合适的半导体。在依据本发明的各种实施例所述的制造方法之前，依据传统的SOI晶圆形成技术(例如晶圆结合或氧注入等)可分别在埋置氧化物层104上方形成SOI层106以及在衬底102上方形成埋置氧化物层104。应当理解，当作为层、区或衬底的元件被称为在另一个元件“上”或“上方”时，它可直接位于该另一个元件上或者可存在中间元件。还应当理解，当一个元件被称为与另一个元件“连接”或“耦接”时，它可与该另一个元件直接连接或耦接，或者可存在中间元件。如本文中所使用的那样，且除非另外指出，否则术语“沉积”可包括适于材料沉积的任意当前已知或以后开发的技术，包括但不限于例如：化学气相沉积(chemical vapor deposition；CVD)、低压CVD(low-pressure CVD；LPCVD)、等离子体增强型CVD(plasma-enhanced CVD；PECVD)、半大气压CVD(semi-atmosphere CVD；SACVD)以及高密度等离子体CVD(high density plasma CVD；HDPCVD)、快速加热CVD(rapid thermal CVD；RTCVD)、超高真空CVD(ultra-high vacuum CVD；UHVCVD)、限制反应处理CVD(limited reaction processing CVD；LRPCVD)、金属有机CVD(metalorganic CVD；MOCVD)、溅镀沉积、离子束沉积、电子束沉积、激光辅助沉积、热氧化、热氮化、旋涂方法、物理气相沉积(physical vapor desposition；PVD)、原子层沉积(atomic layer deposition；ALD)、化学氧化、分子束外延(molecular beam epitaxy；MBE)、电镀、蒸镀。
在衬底102上方(尤其在埋置氧化物层104上方)可形成一组鳍片120。该组鳍片120可例如通过现有技术中已知的和/或本文中所述的传统蚀刻及掩膜技术自SOI层106形成。在该组鳍片120上方可形成栅极堆叠130。栅极堆叠130将包覆各鳍片120，以形成三栅极结构，该结构为现有技术所已知。栅极堆叠130可包括栅极介电质(未图示)以及位于该栅极介电质上方的栅极电极(未图示)。栅极介电质可包括但不限于：二氧化硅、氮氧化硅、金属氧化物、金属氮氧化物、金属硅氧化物、金属硅氮氧化物、金属锗氧化物、金属锗氮氧化物，及其合金、混合物或多层，其中，该金属可选自铝(Al)、钡(Ba)、铍(Be)、铋(Bi)、碳(C)、钙(Ca)、铈(Ce)、钴(Co)、铬(Cr)、镝(Dy)、铕(Eu)、铁(Fe)、镓(Ga)、钆(Gd)、铪(Hf)、铟(In)、镧(La)、锂(Li)、镁(Mg)、锰(Mn)、钼(Mo)、铌(Nb)、镍(Ni)、镨(Pr)、钪(Sc)、锶(Sr)、钽(Ta)、钛(Ti)、钒(V)、钨(W)、钇(Y)、锌(Zn)以及锆(Zr)。栅极电极可包括但不限于：多晶硅，或金属例如钨(W)、铝(Al)或其组合，或全硅化(fully silicided；FUSI)栅极。栅极堆叠130可通过现有技术中已知的和/或本文中所述的任意沉积技术形成。应当理解，栅极堆叠130可在先栅极流程中充当实际(最终)栅极堆叠，或者替代地，充当伪(dummy)栅极堆叠，后续适时地以实际栅极堆叠替代该伪栅极堆叠(在后栅极流程中)。
另外，在栅极堆叠130的侧壁上方可形成间隙壁138，使各鳍片120的侧壁及顶部暴露。间隙壁138可通过现有技术中已知的任意沉积技术形成。间隙壁138可包括但不限于：氧化物或氮化物，例如氮化硅(SiN)或二氧化硅(SiO2)。
在各暴露鳍片120上方可生长外延区。FINFET 110还可包括位于各鳍片120中的各栅极堆叠130的相对侧上的源极区142及漏极区144。也就是说，源极区142与漏极区144可交替位于FINFET 110的各栅极堆叠130之间。
此时，在包括源极区142及漏极区144的各暴露鳍片上方可生长外延区。对于NFET装置，该外延的源极与漏极区可包括但不限于硅(Si)、具有碳浓度约0.1％至约50％的碳化硅(SiC)。这里所使用的“约”意图包括例如在所述值的10％范围内的值。另外，该NFET外延区可掺杂有n型掺杂物，例如磷或砷。对于PFET装置，该外延的源极与漏极区可包括但不限于硅(Si)、锗浓度在约1％至约50％范围内变化的硅锗(SiGe)。另外，该PFET外延区可掺杂有p型掺杂物，例如硼或铟。不过，传统技术导致该外延区在该源极与漏极区上具有相同的尺寸(例如宽度及高度)。本发明的态样包括不对称FINFET，其中，位于源极上方的外延区可具有与漏极上方的外延区的高度不同的高度。因此，本发明的态样包括形成位于各鳍片120的源极142上的第一外延区162(图7)、以及位于各鳍片120的漏极144上的第二外延区164(图7)，其中，第一外延区162具有第一高度H1(图7)，该第一高度H1不同于第二外延区164的第二高度H2(图7)。
请参照图3，形成第一及第二外延区162、164(图7)可包括形成暴露该组鳍片120的第一区152的掩膜。形成该掩膜可包括在FINFET110上沉积标准的覆被光阻掩膜150并图案化掩膜150以暴露FINFET的第一区152。如图3中所示，可形成该掩膜以暴露源极142。也就是说，暴露第一区152可包括暴露源极142。不过，在另一个实施例中，如图4中所示，可形成该掩膜以暴露漏极144。也就是说，暴露第一区152可包括暴露漏极144。
在任一实施例中，可向第一区152引入第一材料154，如图5至6中所示。请参照图5，可向源极142引入第一材料154。在此实施例中，第一材料154可为用于源极142的顶部上的后续外延生长的促进剂。也就是说，第一材料154可包括促进外延区的生长的任意材料。第一材料154可通过离子注入引入，以使源极142注入有第一材料154。例如，第一材料154可包括于通过离子注入引入时破坏源极区142的锗(Ge)、氙(Xe)或其它种类。此离子注入破坏可部分地非晶化源极区142，且在暴露于约500℃至约1100℃的高温时可再结晶，以形成多晶硅区，已知该多晶硅区在外延沉积期间可促进层的生长。在此实施例中，栅极堆叠130、间隙壁138及漏极144被掩膜152覆盖，因此没有遭受第一材料154的注入。
请参照图6，可向漏极144引入第一材料154。在此实施例中，第一材料154可为抑制剂。也就是说，第一材料154可包括抑制外延区的生长的任意材料。例如，当生长PFET硅锗(SiGe)外延区时，第一材料154可包括硼(B)，因为硼(B)减慢硅锗(SiGe)外延生长。当生长NFET外延区时，第一材料154可包括磷(P)，因为磷减慢硅(Si)外延生长。第一材料154可通过离子注入引入，以使漏极144注入有第一材料154。在此实施例中，栅极堆叠130、间隙壁138及源极142被掩膜152覆盖，因此没有遭受第一材料154的注入。
如图7至9中所示，可移除掩膜150并可形成外延区162、164。依据本发明的实施例，图7显示形成外延区162、164以后的图6中所示的实施例。图8至9显示图7中所示的实施例垂直于FINFET 110的鳍片120并在栅极堆叠130之间所作的剖视图。图8的剖视图是在FINFET110已经历本文中所述的方法的态样以后沿线B-B(沿图1的FINFET 110的源极区142)所作。图9的剖视图是在FINFET 110已经历本文中所述的方法的态样以后沿线C-C(沿图1的FINFET 110的漏极区144)所作。外延区162、164可通过外延生长外延层160形成。外延层160可包括但不限于：用于NFET的硅(Si)，以及用于PFET的硅(Si)或硅锗(SiGe)。不过，设于源极142上方的第一外延区162具有第一高度H1，且设于漏极144上方的第二外延区164具有第二高度H2。如这里所述，“高度”可指从与衬底最接近的外延区的部分至离衬底最远的外延区的部分的距离。第一高度H1可不同于第二高度H2。第一高度H1可大于第二高度H2。例如，第一高度H1可等于约30纳米(nm)至约70纳米。尤其，第一高度H1可为约50纳米。第二高度H2可等于约20纳米至约60纳米。尤其，第一高度H1可为约40纳米。第一外延区162可具有较大的高度，因为源极142注入有促进剂而漏极144没有，或者漏极144注入有抑制剂而源极142没有。也就是说，无论在源极142中注入促进剂还是在漏极144中注入抑制剂，外延层160都将在第一外延区162中以比第二外延区164快的速率生长，从而导致较大的高度H1。这样，FINFET 110因外延区162、164的不一致的高度H1、H2而被称为不对称。因此，如图7中所示，所得的结构可包括设于衬底102(尤其是埋置氧化物层104)上的FINFET 110。FINFET可包括邻近栅极堆叠130设置的一组鳍片120、设于该组鳍片120的源极142上的第一外延区162，以及设于该组鳍片120的漏极144上的第二外延区164，其中，第一外延区162具有第一高度H1，该第一高度H1不同于第二外延区164的第二高度H2。
现在将参照图10至12说明本发明的另一个态样。如图10中所示，FINFET 210可如现有技术中已知的那样形成。例如，FINFET 210可如参照图1至2所述形成。如图10中所示，FINFET 210可包括来自衬底202(尤其是埋置氧化物层204)上的SOI层206的一组鳍片220、与鳍片组220垂直并重叠的栅极堆叠230，以及设于栅极堆叠230的相对侧上的间隙壁238。另外，各鳍片220的源极242及漏极244可设于栅极堆叠230的相对侧上。
另外，依据此实施例的揭露的态样提供形成位于各鳍片220的源极242上的第一外延区262以及位于各鳍片220的漏极244上的第二外延区264(图11)，其中，第一外延区262具有第一高度H1a，该第一高度H1a不同于第二外延区264的第二高度H2a(图11)。外延区262、264可通过外延生长外延层260形成。如图10中所示，形成第一及第二外延区262、264可包括在FINFET 210上形成第一掩膜250。形成该第一掩膜可包括在FINFET 210上形成第一掩膜250并图案化第一掩膜250以暴露该组鳍片220的第一区252。如图10中所示，第一区252可包括源极242。第一区252一经暴露，即可在源极242上生长第一外延区262。可如现有技术中已知的那样外延生长第一外延区262。第一外延区262可生长至第一高度H1a。第一高度H1a可基本等于约30纳米至约70纳米，或者尤其约50纳米。
第一外延区262一经形成，即可移除第一掩膜250并可形成第二掩膜254，如图11所示。形成该第二掩膜可包括在FINFET 210上方形成第二掩膜254并图案化第二掩膜254以暴露FINFET 210的第二区256。如图11中所示，第二区256可包括漏极244。第二区256一经暴露，即可在漏极244上生长第二外延区264。可如现有技术已知的那样外延生长第二外延区264。不过，第二外延区264可生长至第二高度H2a。第二高度H2a可等于约20纳米至约60纳米，或者尤其约40纳米。在任何情况下，第二高度H2a小于第一高度H1a。
如图12中所示，可移除掩膜254。因此，所得的结构可包括设于衬底202(尤其埋置氧化物层204)上的FINFET 210。FINFET 210可包括邻近栅极堆叠230设置的一组鳍片220、设于该组鳍片220的源极242上的第一外延区262，以及设于该组鳍片220的漏极244上的第二外延区264。第一外延区262可具有第一高度H1a，该第一高度H1a不同于第二外延区264的第二高度H2a。
应当理解，在与参照图9至12所述的实施例类似的替代实施例中(未图示)，可形成第一掩膜以暴露漏极244而不是源极242，且可形成第二掩膜以暴露源极242而不是漏极244。在此实施例中，漏极上方的外延区264可生长至第一高度，该第一高度小于源极上方的外延区262的生长。不过，在任一实施例中，源极242会具有大于H2a的高度H1a。也就是说，无论掩膜步骤采用哪种顺序，源极242上方的第一外延区262的外延生长将使第一外延区262具有大于第二外延区264的高度H2a。
本文中所使用的术语仅是出于说明特定实施例的目的，并非意图限制本发明。除非上下文中另外明确指出，否则本文中所使用的单数形式“一”、“一个”以及“该”也意图包括复数形式。另外，应当理解，术语“包括”或“包含”用于本说明书中时表明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件、和/或其群组。
对本发明的各种实施例的说明是出于示例目的，而非意图详尽无遗或限于所揭露的实施例。许多修改及变更将对于本领域的普通技术人员显而易见，而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理，实际应用或在市场已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文中所揭露的实施例。

Claims (20)

1.一种不对称半导体装置，包括：
衬底；以及
鳍式场效应晶体管(FINFET)，设于该衬底上，该FINFET包括：
一组鳍片，邻近栅极设置；
第一外延区，设于该组鳍片的源极区上，该第一外延区具有第一高度；以及
第二外延区，设于该组鳍片的漏极区上，该第二外延区具有第二高度，
其中，该第一高度不同于该第二高度。
2.如权利要求1所述的半导体装置，其中，该第一高度大于该第二高度。
3.如权利要求2所述的半导体装置，其中，该第一高度等于约30纳米(nm)至约70纳米，且该第二高度等于约20纳米至约60纳米。
4.如权利要求1所述的半导体装置，其中，该漏极区离子注入有抑制剂。
5.如权利要求1所述的半导体装置，其中，该源极区离子注入有促进剂。
6.一种形成不对称半导体装置的方法，该方法包括：
在衬底上形成鳍式场效应晶体管(FINFET)，该FINFET具有与一组鳍片垂直的栅极，各鳍片具有位于该栅极的相对侧上的源极区及漏极区；以及
形成位于各鳍片的该源极区上的第一外延区以及位于各鳍片的该漏极区上的第二外延区，其中，该第一外延区具有第一高度，该第一高度不同于该第二外延区的第二高度。
7.如权利要求6所述的方法，其中，所述形成该第一外延区及第二外延区包括：
在该组鳍片上形成掩膜，以暴露该组鳍片的第一区；
在该暴露第一区上引入第一材料；
自该组鳍片移除该掩膜的其余部分；
在该组鳍片的该第一区及该第二区上方生长外延层。
8.如权利要求7所述的方法，其中：
所述形成该掩膜包括暴露该漏极区，
所述引入该第一材料包括在该漏极区上引入抑制剂，以及
该第一高度大于该第二高度。
9.如权利要求7所述的方法，其中：
所述形成该掩膜包括暴露该源极区，
所述引入该第一材料包括在该源极区上沉积促进剂，以及
其中，该第一高度大于该第二高度。
10.如权利要求6所述的方法，其中，所述形成该第一外延区及第二外延区包括：
在该组鳍片上形成第一掩膜，以暴露该组鳍片的第一区；
在该暴露第一区上生长第一外延层；
自该组鳍片移除该第一掩膜；
在该组鳍片上形成第二掩膜，以暴露该组鳍片的第二区；以及
在该暴露第二区上生长第二外延层。
11.如权利要求10所述的方法，其中，所述生长该第一外延层包括生长该第一外延层至第一高度，以及所述生长该第二外延层包括生长该第二外延层至第二高度，该第一高度大于该第二高度。
12.如权利要求10所述的方法，其中，所述生长该第一外延层包括生长该第一外延层至第一高度，以及所述生长该第二外延层包括生长该第二外延层至第二高度，该第一高度小于该第二高度。
13.一种形成不对称半导体装置的方法，该方法包括：
在衬底上形成鳍片；
垂直于该衬底上的该鳍片形成栅极堆叠；
形成一对间隙壁，各间隙壁位于该栅极堆叠的相对侧上；
形成位于该栅极堆叠的一侧上的源极区以及位于该栅极堆叠的相对侧上的漏极区；以及
形成位于该源极上的第一外延区以及位于该漏极上的第二外延区，其中，该第一外延区具有第一高度，该第一高度不同于该第二外延区的第二高度。
14.如权利要求13所述的方法，其中，所述形成该第一外延区及第二外延区包括：
在该鳍片上形成掩膜，以暴露鳍片的第一区；
在该暴露第一区上引入第一材料；
自该鳍片的第二区移除该掩膜；
在该鳍片的该第一区及该第二区上方生长外延层。
15.如权利要求14所述的方法，其中：
所述形成该掩膜包括暴露该漏极区，
所述引入该第一材料包括在该漏极区上沉积抑制剂，以及
该第一高度大于该第二高度。
16.如权利要求14所述的方法，其中：
所述形成该掩膜包括暴露该源极区，
所述引入该第一材料包括在该源极区上沉积促进剂，以及
该第一高度大于该第二高度。
17.如权利要求14所述的方法，其中，所述引入该第一材料包括执行离子注入。
18.如权利要求13所述的方法，其中，所述形成该第一外延区及第二外延区包括：
在该鳍片上形成第一掩膜，以暴露该鳍片的第一区；
在该暴露第一区上生长第一外延层；
自该鳍片移除该第一掩膜；
在该鳍片上形成第二掩膜，以暴露该鳍片的第二区；以及
在该暴露第二区上生长第二外延层。
19.如权利要求18所述的方法，其中，所述生长该第一外延层包括生长该第一外延层至第一高度，以及所述生长该第二外延层包括生长该第二外延层至第二高度，该第一高度大于该第二高度。
20.如权利要求18所述的方法，其中，所述生长该第一外延层包括生长该第一外延层至第一高度，以及所述生长该第二外延层包括生长该第二外延层至第二高度，该第一高度小于该第二高度。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109427783A (zh) * 2017-08-22 2019-03-05 三星电子株式会社 集成电路装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11239368B2 (en) * 2019-08-30 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US20210249307A1 (en) * 2020-02-06 2021-08-12 Globalfoundries U.S. Inc. Transistors with asymmetrically-positioned source/drain regions
US11545575B2 (en) 2020-07-02 2023-01-03 Globalfoundries U.S. Inc. IC structure with fin having subfin extents with different lateral dimensions
US11211453B1 (en) 2020-07-23 2021-12-28 Globalfoundries U.S. Inc. FinFET with shorter fin height in drain region than source region and related method
US20220238521A1 (en) * 2021-01-22 2022-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Device and Method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187643B1 (en) * 1999-06-29 2001-02-13 Varian Semiconductor Equipment Associates, Inc. Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)
US20090221123A1 (en) * 2008-02-29 2009-09-03 Uwe Griebenow Method for increasing penetration depth of drain and source implantation species for a given gate height
US20100285650A1 (en) * 2009-05-08 2010-11-11 GlobalFoundries, Inc. Method of fabricating semiconductor transistor devices with asymmetric extension and/or halo implants
US20130049115A1 (en) * 2011-08-24 2013-02-28 International Business Machines Corporation Mosfet including asymmetric source and drain regions
CN103681652A (zh) * 2012-08-31 2014-03-26 台湾积体电路制造股份有限公司 用于应力优化的鳍式场效应晶体管布局

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7737501B2 (en) 2007-07-11 2010-06-15 International Business Machines Corporation FinFET SRAM with asymmetric gate and method of manufacture thereof
US20110049582A1 (en) * 2009-09-03 2011-03-03 International Business Machines Corporation Asymmetric source and drain stressor regions
US8138030B2 (en) 2009-09-15 2012-03-20 International Business Machines Corporation Asymmetric finFET device with improved parasitic resistance and capacitance
US7989297B2 (en) 2009-11-09 2011-08-02 International Business Machines Corporation Asymmetric epitaxy and application thereof
US9087725B2 (en) 2009-12-03 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with different fin height and EPI height setting
US8592916B2 (en) * 2012-03-20 2013-11-26 International Business Machines Corporation Selectively raised source/drain transistor
US20130320429A1 (en) 2012-05-31 2013-12-05 Asm Ip Holding B.V. Processes and structures for dopant profile control in epitaxial trench fill
US8896030B2 (en) 2012-09-07 2014-11-25 Intel Corporation Integrated circuits with selective gate electrode recess
US8969932B2 (en) 2012-12-12 2015-03-03 Globalfoundries Inc. Methods of forming a finfet semiconductor device with undoped fins
US8815659B2 (en) 2012-12-17 2014-08-26 Globalfoundries Inc. Methods of forming a FinFET semiconductor device by performing an epitaxial growth process
US8981493B2 (en) 2013-01-09 2015-03-17 International Business Machines Corporation FinFET and method of fabrication
US9231106B2 (en) 2013-03-08 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with an asymmetric source/drain structure and method of making same
US8906789B2 (en) 2013-03-13 2014-12-09 Taiwan Semiconductor Manufacturing Co., Ltd. Asymmetric cyclic desposition etch epitaxy
US9153694B2 (en) 2013-09-04 2015-10-06 Globalfoundries Inc. Methods of forming contact structures on finfet semiconductor devices and the resulting devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187643B1 (en) * 1999-06-29 2001-02-13 Varian Semiconductor Equipment Associates, Inc. Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)
US20090221123A1 (en) * 2008-02-29 2009-09-03 Uwe Griebenow Method for increasing penetration depth of drain and source implantation species for a given gate height
US20100285650A1 (en) * 2009-05-08 2010-11-11 GlobalFoundries, Inc. Method of fabricating semiconductor transistor devices with asymmetric extension and/or halo implants
US20130049115A1 (en) * 2011-08-24 2013-02-28 International Business Machines Corporation Mosfet including asymmetric source and drain regions
CN103681652A (zh) * 2012-08-31 2014-03-26 台湾积体电路制造股份有限公司 用于应力优化的鳍式场效应晶体管布局

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109427783A (zh) * 2017-08-22 2019-03-05 三星电子株式会社 集成电路装置
CN109427783B (zh) * 2017-08-22 2023-05-16 三星电子株式会社 集成电路装置

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