CN104124165A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN104124165A
CN104124165A CN201310156840.2A CN201310156840A CN104124165A CN 104124165 A CN104124165 A CN 104124165A CN 201310156840 A CN201310156840 A CN 201310156840A CN 104124165 A CN104124165 A CN 104124165A
Authority
CN
China
Prior art keywords
along
stress liner
gate stack
stress
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310156840.2A
Other languages
English (en)
Other versions
CN104124165B (zh
Inventor
许杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201310156840.2A priority Critical patent/CN104124165B/zh
Publication of CN104124165A publication Critical patent/CN104124165A/zh
Application granted granted Critical
Publication of CN104124165B publication Critical patent/CN104124165B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种半导体器件及其制造方法，包括：在衬底上形成沿第一方向延伸的多个鳍片和鳍片之间的沟槽；在沟槽中填充成应力衬层；在应力衬层中形成沿第二方向延伸的开口；在开口中形成沿第二方向延伸并且跨越多个鳍片的栅极堆叠。依照本发明的半导体器件及其制造方法，在鳍片之间、栅极堆叠两侧填充了应力衬层，有效增大了沟道区载流子迁移率，提高了器件性能。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，特别是涉及一种在体Si衬底上形成的具有应力的三维多栅FinFET及其制造方法。
背景技术
在当前的亚20nm技术中，三维多栅器件（FinFET或Tri--gate）是主要的器件结构，这种结构增强了栅极控制能力、抑制了漏电与短沟道效应。
例如，双栅SOI结构的MOSFET与传统的单栅体Si或者SOI MOSFET相比，能够抑制短沟道效应（SCE）以及漏致感应势垒降低（DIBL）效应，具有更低的结电容，能够实现沟道轻掺杂，可以通过设置金属栅极的功函数来调节阈值电压，能够得到约2倍的驱动电流，降低了对于有效栅氧厚度（EOT）的要求。而三栅器件与双栅器件相比，栅极包围了沟道区顶面以及两个侧面，栅极控制能力更强。进一步地，全环绕纳米线多栅器件更具有优势。
现有的FinFET结构以及制造方法通常包括：在体Si或者SOI衬底中刻蚀形成多个平行的沿第一方向延伸的鳍片和沟槽；对鳍片执行离子注入或者沉积掺杂层并退火，在鳍片中部形成穿通阻挡层（PTSL）以抑制寄生沟道效应；在沟槽中填充绝缘材料，回刻以露出部分鳍片，形成浅沟槽隔离（STI）；在鳍片顶部以及侧壁沉积通常为氧化硅的较薄（例如仅1～5nm）假栅极绝缘层，在假栅极绝缘层上沉积通常为多晶硅、非晶硅的假栅极层；刻蚀假栅极层和假栅极绝缘层，形成沿第二方向延伸的假栅极堆叠，其中第二方向优选地垂直于第一方向；以假栅极堆叠为掩模，对鳍片进行浅掺杂形成轻掺杂漏结构（LDD）以抑制漏致感应势垒降低效应；在假栅极堆叠的沿第一方向的两侧沉积并刻蚀形成栅极侧墙；在栅极侧墙的沿第一方向的两侧的鳍片上外延生长相同或者相近材料形成源漏区，优选采用SiGe、SiC等高于Si应力的材料以提高载流子迁移率；优选地，在源漏区上形成接触刻蚀停止层（CESL）；在晶片上沉积层间介质层（ILD）；刻蚀去除假栅极堆叠，在ILD中留下栅极沟槽；在栅极沟槽中沉积高k材料（HK）的栅极绝缘层以及金属/金属合金/金属氮化物（MG）的栅极导电层，并优选包括氮化物材质的栅极盖层以保护金属栅极。进一步地，利用掩模刻蚀ILD形成源漏接触孔，暴露源漏区；可选地，为了降低源漏接触电阻，在源漏接触孔中形成金属硅化物。填充金属/金属氮化物形成接触塞，通常优选填充率较高的金属W、Ti。由于CESL、栅极侧墙的存在，填充的金属W、Ti会自动对准源漏区，最终形成接触塞。此种接触塞结构也称作自对准接触（SAC）。
然而，鉴于FinFET尺寸日益缩减（例如22nm以下乃至10nm左右），通过应力层向沟道区施加应力从而提高载流子迁移率、器件驱动能力的方法变得日益困难，这是由于在微细尺寸上氮化硅、类金刚石无定形碳（DLC）等应力衬层的保形性不再良好，容易与下层结构发生剥离，导致局部或者整体应力失效。
因此综上所示，现有的体Si衬底制作的FinFET难以有效提高器件的驱动能力。
发明内容
由上所述，本发明的目的在于克服上述技术困难，提出一种新的FinFET结构及其制造方法，能有效增大沟道区应力从而提升载流子迁移率，并最终增强器件的驱动能力。
为此，本发明提供了一种半导体器件制造方法，包括：在衬底上形成沿第一方向延伸的多个鳍片和鳍片之间的沟槽；在沟槽中填充成应力衬层；在应力衬层中形成沿第二方向延伸的开口；在开口中形成沿第二方向延伸并且跨越多个鳍片的栅极堆叠。
其中，应力衬层的材质包括氮化硅、DLC及其组合。
其中，对于PFET而言应力衬层具有张应力，对于NFET而言应力衬层具有压应力。
其中，形成栅极堆叠之后进一步包括：在栅极堆叠沿第一方向的两侧形成栅极侧墙；在栅极侧墙沿第一方向两侧的鳍片顶部形成源漏区；在源漏区上形成金属硅化物。
其中，栅极堆叠包括高k材料的栅极绝缘层、功函数调节层以及电阻调节层。
本发明还提供了一种半导体器件，包括：衬底上沿第一方向延伸的多个鳍片；沿第二方向延伸并且跨越了每个鳍片的栅极堆叠；位于栅极沿第一方向的两侧的鳍片上的源漏区；其中，多个鳍片之间、栅极堆叠沿第一方向的两侧具有应力衬层。
其中，应力衬层的材质包括氮化硅、DLC及其组合。
其中，对于PFET而言应力衬层具有张应力，对于NFET而言应力衬层具有压应力。
其中，栅极堆叠包括高k材料的栅极绝缘层、功函数调节层以及电阻调节层。
其中，源漏区上具有金属硅化物。
依照本发明的半导体器件及其制造方法，在鳍片之间、栅极堆叠两侧填充了应力衬层，有效增大了沟道区载流子迁移率，提高了器件性能。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1至图8为依照本发明的FinFET的制造方法各步骤的示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了能有效增大沟道区应力从而提升载流子迁移率的三维多栅FinFET及其制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
如图1的透视图所示，在衬底1上形成沿第一方向延伸的多个鳍片结构1F以及鳍片结构之间的沟槽1G，其中第一方向为未来器件沟道区延伸方向。提供衬底1，衬底1依照器件用途需要而合理选择，可包括单晶体硅（Si）、单晶体锗（Ge）、应变硅（Strained Si）、锗硅（SiGe），或是化合物半导体材料，例如氮化镓（GaN）、砷化镓（GaAs）、磷化铟(InP)、锑化铟（InSb），以及碳基半导体例如石墨烯、SiC、碳纳管等等。出于与CMOS工艺兼容的考虑，衬底1优选地为体Si。优选地，在衬底1上通过旋涂、喷涂、丝网印刷等工艺沉积形成光刻胶层2，并以沿第一方向延伸分布的掩模板图形曝光/显影形成光刻胶图形2。以光刻胶2为掩模，刻蚀衬底1，在衬底1中形成多个沿第一方向平行分布的沟槽1G以及沟槽1G之间剩余的衬底1材料所构成的鳍片1F。刻蚀优选各向异性的刻蚀，例如等离子体干法刻蚀、反应离子刻蚀（RIE）或者四甲基氢氧化铵（TMAH）湿法腐蚀，使得沟槽1G的深宽比优选地大于5:1。
此外，也可以采用侧墙图形转移方法来形成鳍片。例如，先在衬底上通过CVD或PVD方法沉积材质例如多晶硅、非晶硅、非晶碳、氧化硅等材质的牺牲层，然后通过i线曝光、紫外线曝光等方法在牺牲层上形成较大尺寸的光刻胶掩模，以该大尺寸光刻胶为掩模刻蚀牺牲层先形成较大尺寸的牺牲层图形，接着在牺牲层图形线条的两侧沉积并刻蚀形成氮化硅、DLC等材质的侧墙，去除牺牲层留下侧墙，侧墙构成了较小尺寸的线条。以这些小尺寸线条为掩模，刻蚀衬底得到小尺寸鳍片。
如图2的透视图所示，去除光刻胶图形2，在多个鳍片1F之间的沟槽1G中形成应力衬层3。例如通过PECVD、HDPCVD、MOCVD、MBE、ALD、磁控溅射等工艺，形成应力衬层3以完全填充鳍片1F之间的沟槽1G。应力衬层3的材质例如氮化硅、DLC及其组合。对于PFET而言，应力衬层3具有张应力，对于NFET而言，应力衬层3具有压应力。应力衬层3的应力类型和绝对值大小可以通过控制工艺参数来实现，例如控制PECVD或磁控溅射的气压、温度、等离子体功率等参数使得应力绝对值大于1GPa，并优选介于2～4GPa之间。随后优选地，采用CMP、回刻（etch--back）等工艺平坦化应力衬层3直至暴露鳍片1F顶部。值得注意的是，与以往鳍片之间沟槽内填充氧化硅等绝缘介质形成浅沟槽隔离（STI）不同，本发明技术方案采用氮化硅、DLC及其组合作为应力衬层以向沟道区提供应力，并且同时该应力衬层也能绝缘隔离鳍片沟道区，进一步提高了器件性能。
如图3的透视图以及图4和图5的剖面透视图所示，图形化并刻蚀应力衬层3，在应力衬层3中形成沿第二方向（优选垂直于前述第一方向）的开口3G。在应力衬层3上形成光刻胶图形（未示出），暴露出应力衬层3沿第一方向的中部。以光刻胶图形为掩模，采用各向异性的等离子干法刻蚀或者RIE，刻蚀应力衬层3，在中部形成开口3G，将应力衬层3沿第一方向分为左右两块3A和3B，开口3G露出了鳍片1F的中部。图4为沿图3的A--A’线剖得，图5为沿图3的B--B’线剖得。
如图6的透视图所示，在应力衬层3的开口3G中形成栅极堆叠。图7的剖视图为沿图6的A--A’线剖得到，图8的剖视图为沿图6的C--C’线剖得。
通过PECVD、HDPCVD、UHVCVD、MOCVD、MBE、ALD、蒸发、溅射等工艺依次在开口3G中沉积栅极绝缘层4、功函数调节层5、以及电阻调节层6。栅极绝缘层4优选高k材料，包括但不限于包括选自HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx的铪基材料（其中，各材料依照多元金属组分配比以及化学价不同，氧原子含量x可合理调整，例如可为1～6且不限于整数），或是包括选自ZrO2、La2O3、LaAlO3、TiO2、Y2O3的稀土基高K介质材料，或是包括Al2O3，以其上述材料的复合层。功函数调节层5则可为金属，其中金属可包括Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物。电阻调节层6可以包括多晶硅、多晶锗硅、上述金属单质、金属合金以及金属氮化物，并且优选地掺杂C、F、N、O、B、P、As等元素以调节电阻。优选地，层3与层4之间、和/或层4与层5之间还具有氮化物的阻挡层（未示出），阻挡层材质为MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz，其中M为Ta、Ti、Hf、Zr、Mo、W或其它元素或其组合。随后如图7所示，沿第一方向刻蚀去除部分上述叠层，仅在沟槽3G中留下沿第二方向延伸分布的栅极堆叠4/5/6。
随后优选地，在上述栅极堆叠4/5/6的沿第一方向的两侧形成栅极侧墙7。例如通过PECVD、磁控溅射等工艺形成氮化硅、DLC材质的介质层并刻蚀形成侧墙7。接着，以栅极侧墙7为掩模，对沿第一方向两侧的鳍片1F顶部进行注入掺杂，形成源漏区（图8中虚线框所示）。
其中，源漏区可以是单一的重掺杂区，也可以是包括轻掺杂源漏（LDD）结构的掺杂区，LDD结构通过以栅极堆叠4/5/6为掩模垂直离子注入得到，或者还可以包括倾斜离子注入得到的晕状（halo）源漏掺杂区（图7中椭圆虚线框所示）。进一步地，还可以先刻蚀鳍片1F顶部形成源漏沟槽，然后在沟槽中外延生长更高应力的SiGe、Si:C、Si:H、SiSn、GeSn、SiGe:C等材料及其组合，以进一步提高沟道区应力。优选地，在外延生长源漏的同时进行原位掺杂或者外延之后进行离子注入而重掺杂，使得源漏具有高于轻掺杂源漏的杂质浓度。随后，退火以激活掺杂的杂质。
随后，在源漏区上蒸发、溅射、MOCVD、MBE、ALD形成金属层（未示出），其材质例如Ni、Pt、Co、Ti、W等金属以及金属合金。在250～1000摄氏度下退火1ms～10min，使得金属或金属合金与源漏区中所含的Si元素反应形成金属硅化物8，以降低接触电阻。
此后，可以在整个器件上形成层间介质层并刻蚀形成源漏接触孔以完成最终器件制造。
最终形成的器件结构透视图如图5所示，剖视图如图6、7所示，器件包括：衬底上沿第一方向延伸的多个鳍片，沿第二方向延伸（与第一方向相交并且优选地垂直）并且跨越了每个鳍片的栅极，位于栅极沿第一方向的两侧的鳍片上的源漏区，源漏区上具有金属硅化物。其中，鳍片之间、栅极沿第一方向的两侧具有应力衬层，用于提高沟道区应力和载流子迁移率。其余各个部件结构以及参数、材料均在方法中详述，在此不再赘述。
实施例1
依照上述方法制造的器件结构中，鳍片高度为80nm，宽度（沿第二方向）为20nm，（沿第一方向）栅极堆叠的宽度（也即沟槽3G的宽度、沟道区长度）为40nm。如表1所示，申请人尝试了不同的应力类型和大小，获得了器件的各种性能参数，例如最大漏电流Idmax、关断电流Ioff以及灵敏度SS。
表1
由表1可见，依照本发明的应力衬层3（NMOS压应力、PMOS张应力）可以明显提高器件最大漏电流以增大器件驱动能力，同时关断电流基本保持不变，而灵敏度略有提升，总体而言大大提高了器件性能。
依照本发明的半导体器件及其制造方法，在鳍片之间、栅极堆叠两侧填充了应力衬层，有效增大了沟道区载流子迁移率，提高了器件性能。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (10)

1.一种半导体器件制造方法，包括：
在衬底上形成沿第一方向延伸的多个鳍片和鳍片之间的沟槽；
在沟槽中填充成应力衬层；
在应力衬层中形成沿第二方向延伸的开口；
在开口中形成沿第二方向延伸并且跨越多个鳍片的栅极堆叠。
2.如权利要求1的半导体器件制造方法，其中，应力衬层的材质包括氮化硅、DLC及其组合。
3.如权利要求1的半导体器件制造方法，其中，对于PFET而言应力衬层具有张应力，对于NFET而言应力衬层具有压应力。
4.如权利要求1的半导体器件制造方法，其中，形成栅极堆叠之后进一步包括：
在栅极堆叠沿第一方向的两侧形成栅极侧墙；
在栅极侧墙沿第一方向两侧的鳍片顶部形成源漏区；
在源漏区上形成金属硅化物。
5.如权利要求1的半导体器件制造方法，其中，栅极堆叠包括高k材料的栅极绝缘层、功函数调节层以及电阻调节层。
6.一种半导体器件，包括：
衬底上沿第一方向延伸的多个鳍片；
沿第二方向延伸并且跨越了每个鳍片的栅极堆叠；
位于栅极沿第一方向的两侧的鳍片上的源漏区；
其中，多个鳍片之间、栅极堆叠沿第一方向的两侧具有应力衬层。
7.如权利要求6的半导体器件，其中，应力衬层的材质包括氮化硅、DLC及其组合。
8.如权利要求6的半导体器件，其中，对于PFET而言应力衬层具有张应力，对于NFET而言应力衬层具有压应力。
9.如权利要求6的半导体器件，其中，栅极堆叠包括高k材料的栅极绝缘层、功函数调节层以及电阻调节层。
10.如权利要求6的半导体器件，其中，源漏区上具有金属硅化物。
CN201310156840.2A 2013-04-28 2013-04-28 半导体器件及其制造方法 Active CN104124165B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310156840.2A CN104124165B (zh) 2013-04-28 2013-04-28 半导体器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310156840.2A CN104124165B (zh) 2013-04-28 2013-04-28 半导体器件及其制造方法

Publications (2)

Publication Number Publication Date
CN104124165A true CN104124165A (zh) 2014-10-29
CN104124165B CN104124165B (zh) 2018-09-18

Family

ID=51769534

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310156840.2A Active CN104124165B (zh) 2013-04-28 2013-04-28 半导体器件及其制造方法

Country Status (1)

Country Link
CN (1) CN104124165B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158662A (zh) * 2015-05-15 2016-11-23 台湾积体电路制造股份有限公司 用于半导体器件的双氮化物应力源和制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030189228A1 (en) * 2002-04-05 2003-10-09 International Business Machines Corporation Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
CN1797736A (zh) * 2004-12-03 2006-07-05 台湾积体电路制造股份有限公司 调整晶体管的浅沟渠隔离结构应力的方法
US20070190708A1 (en) * 2006-01-31 2007-08-16 Akio Kaneko Semiconductor device and method manufacturing semiconductor device
CN101681842A (zh) * 2007-05-14 2010-03-24 英特尔公司 具有无尖端外延源极/漏极区的半导体器件
US20110171805A1 (en) * 2007-10-15 2011-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Source/Drain Contact Processing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030189228A1 (en) * 2002-04-05 2003-10-09 International Business Machines Corporation Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
CN1797736A (zh) * 2004-12-03 2006-07-05 台湾积体电路制造股份有限公司 调整晶体管的浅沟渠隔离结构应力的方法
US20070190708A1 (en) * 2006-01-31 2007-08-16 Akio Kaneko Semiconductor device and method manufacturing semiconductor device
CN101681842A (zh) * 2007-05-14 2010-03-24 英特尔公司 具有无尖端外延源极/漏极区的半导体器件
US20110171805A1 (en) * 2007-10-15 2011-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. System and Method for Source/Drain Contact Processing

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158662A (zh) * 2015-05-15 2016-11-23 台湾积体电路制造股份有限公司 用于半导体器件的双氮化物应力源和制造方法
CN106158662B (zh) * 2015-05-15 2019-09-27 台湾积体电路制造股份有限公司 用于半导体器件的双氮化物应力源和制造方法
US10483262B2 (en) 2015-05-15 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Dual nitride stressor for semiconductor device and method of manufacturing
US10872893B2 (en) 2015-05-15 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Dual nitride stressor for semiconductor device and method of manufacturing

Also Published As

Publication number Publication date
CN104124165B (zh) 2018-09-18

Similar Documents

Publication Publication Date Title
US10930764B2 (en) Extension region for a semiconductor device
US10515966B2 (en) Enhanced channel strain to reduce contact resistance in NMOS FET devices
US9196613B2 (en) Stress inducing contact metal in FinFET CMOS
US9653581B2 (en) Semiconductor device and method of making
US9601598B2 (en) Method of manufacturing a fin-like field effect transistor (FinFET) device
CN103311247B (zh) 半导体器件及其制造方法
US9275907B2 (en) 3D transistor channel mobility enhancement
CN103311281B (zh) 半导体器件及其制造方法
US8735993B2 (en) FinFET body contact and method of making same
US8652891B1 (en) Semiconductor device and method of manufacturing the same
US8853024B2 (en) Method of manufacturing semiconductor device
CN103632973B (zh) 半导体器件及其制造方法
CN103066122B (zh) Mosfet及其制造方法
CN103579314B (zh) 半导体器件及其制造方法
CN104112667B (zh) 半导体器件及其制造方法
US8461650B2 (en) Semiconductor device and method for manufacturing the same
CN103325787B (zh) Cmos器件及其制造方法
CN104112666A (zh) 半导体器件及其制造方法
CN104124165B (zh) 半导体器件及其制造方法
CN103515233B (zh) 半导体器件及其制造方法
KR102501422B1 (ko) 반도체 디바이스 및 그 제조 방법
CN104217949A (zh) 半导体器件及其制造方法
CN103681279A (zh) 半导体器件及其制造方法
WO2014059565A1 (zh) Cmos制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant