TWI597828B - 非揮發性記憶體結構及其形成方法 - Google Patents
非揮發性記憶體結構及其形成方法 Download PDFInfo
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- TWI597828B TWI597828B TW105135368A TW105135368A TWI597828B TW I597828 B TWI597828 B TW I597828B TW 105135368 A TW105135368 A TW 105135368A TW 105135368 A TW105135368 A TW 105135368A TW I597828 B TWI597828 B TW I597828B
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- Prior art keywords
- crystalline semiconductor
- gate
- transistors
- layer
- doped crystalline
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Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Description
本揭露是關於一種半導體結構及其形成方法。
非揮發性記憶體應用在各種電子裝置上,例如電腦。非揮發性記憶體是一種即便在電源不開啟時,仍能儲存資料的記憶體存儲器。非揮發性記憶體可以被電性定址。被電性定址的非揮發性記憶體的例子包括快閃記憶體、可抹除可程式唯讀記憶體(erasable programmable read only memory;EPROM)、電子式可抹除可程式唯讀記憶體(electrically erasable programmable read only memory;EEPROM)。非揮發性記憶體的功能包括擁有信息編程至其中、於其中讀取信息及/或抹除信息。
非揮發性記憶經常包括電子元件諸如二極體、電容器和電阻器,其中每一個都可以與電晶體結合以形成一電子電路。
本揭露的一實施例的一種形成非揮發性記憶胞陣
列的方法包括以下步驟。提供一基板,其具有一上介電層與位於所述上介電層下方的多個電晶體。基板是大塊晶圓。形成一多層互連在這些電晶體上。形成一摻雜晶狀半導體層。設置所述摻雜晶狀半導體層在所述上介電層上。蝕刻所述摻雜晶狀半導體層以形成相對於所述基板表面的水平定向的多個奈米線。形成一電荷俘獲堆疊層,在所述多個奈米線上。形成多個閘極電極,在所述電荷俘獲堆疊層上。形成一第一互連,在所述多個奈米線的一第一奈米線和所述多個電晶體中的一第一電晶體之間。形成一第二互連,在所述多個閘極電極的一第一閘極電極和所述多個電晶體中的一第二電晶體之間。
本揭露的另一實施例的一種形成無接面式場效電晶體基的非揮發性記憶體的方法包括以下步驟。提供一基板,其具有一第一介電層與位於所述第一介電層下方的多個電晶體。形成一多層互連在這些電晶體上。設置一摻雜晶狀半導體層在所述第一介電層上。蝕刻所述摻雜晶狀半導體層以在所述第一介電層上形成多個摻雜晶狀半導體結構。形成多個閘極結構在所述多個摻雜晶狀半導體結構的每一個上。形成一第一電性連接互連,在所述多個摻雜晶狀半導體結構的一第一摻雜晶狀半導體結構和所述多個電晶體中的一第一電晶體之間。形成一第二電性連接互連,在所述多個閘極結構的一第一閘極結構和所述多個電晶體中的一第二電晶體之間。所述多個閘極結構的各閘極結構包括一閘極電極。
本揭露的又一實施例的一種無接面式場效電晶體基的非揮發性記憶體結構包括一基板、一多層互連、多個摻雜晶狀半導體結構、多個閘極結構、一第一互連以及一第二互
連。基板具有一第一介電層與位於所述第一介電層下方的多個電晶體。多層互連位在這些電晶體上。摻雜晶狀半導體結構位在所述第一介電層上。閘極結構位在所述多個摻雜晶狀半導體結構的每一個上。第一互連電性耦接在所述多個摻雜晶狀半導體結構的一第一摻雜晶狀半導體結構和所述多個電晶體中的一第一電晶體之間。第二互連電性耦接在所述多個閘極結構的一第一閘極結構和所述多個電晶體中的一第二電晶體之間。
104D‧‧‧汲極
104S‧‧‧源極
106、206、306‧‧‧閘極介電質
108、208、308‧‧‧閘極電極
204C、304C‧‧‧通道
204D‧‧‧汲極
204S‧‧‧源極
206'、306'‧‧‧閘極介電層
304S‧‧‧第一源極/汲極端子
304D‧‧‧第二源極/汲極端子
500‧‧‧晶種晶圓
502‧‧‧第一基板
504‧‧‧奈米線
504'‧‧‧晶狀半導體層
510‧‧‧裝置晶圓
512‧‧‧第二基板
514‧‧‧隔離層
520‧‧‧晶圓組件
700‧‧‧非揮發性儲存記憶體陣列
702、704‧‧‧截面
803‧‧‧金屬互連
803B‧‧‧位元線互連
803W‧‧‧字元線互連
804‧‧‧第二隔離層
805‧‧‧電晶體
900‧‧‧方法
902、904、906、908、910‧‧‧操作步驟
閱讀以下詳細敘述並搭配對應之圖式,可了解本揭露之多個態樣。應注意,根據業界中的標準做法,多個特徵並非按比例繪製。事實上,多個特徵之尺寸可任意增加或減少以利於討論的清晰性。
第1圖為依據部分實施例的無接面式場效電晶體結構的等角視圖。
第2圖為依據本揭露的n型矽無接面式場效電晶體的剖視圖。
第3圖為依據本揭露的p型矽無接面式場效電晶體的剖視圖。
第4A圖至第4C圖繪示了依據部分實施例的n型矽無接面式場效電晶體的示例操作狀態。
第5A圖至第5C圖繪示了依據部分實施例的n型矽無接面式場效電晶體的不同製造步驟下的剖視圖。
第5D圖至第5F圖繪示了依據部分實施例的n型矽無接面式場效電晶體的不同製造步驟下的等角視圖。
第6圖為依據部分實施例的p型矽無接面式場效電晶體的等角視圖。
第7圖為依據部分實施例的非揮發性記憶體陣列的上視圖。
第8A圖至第8F圖繪示了依據部分實施例的三維交錯型非揮發性記憶體陣列的示例性結構。
第9圖為一半導體結構形成方法的流程圖。
以下揭露提供眾多不同的實施例或範例,用於實施本案提供的主要內容之不同特徵。下文描述一特定範例之組件及配置以簡化本揭露。當然,此範例僅為示意性,且並不擬定限制。舉例而言,以下描述「第一特徵形成在第二特徵之上方或之上」,於實施例中可包括第一特徵與第二特徵直接接觸,且亦可包括在第一特徵與第二特徵之間形成額外特徵使得第一特徵及第二特徵無直接接觸。此外,本揭露可在各範例中重複使用元件符號及/或字母。此重複之目的在於簡化及釐清,且其自身並不規定所討論的各實施例及/或配置之間的關係。並且,為使說明簡化及明確,不同特徵亦將任意地以不同尺度繪製。
此外,空間相對術語,諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等等在本文中用於簡化描述,以描述如附圖中所圖示的一個元件或特徵結構與另一元件或特徵結構的關係。除
了描繪圖示之方位外,空間相對術語也包含元件在使用中或操作下之不同方位。舉例而言,如果在附圖中的裝置被翻轉,則被描述為「下方(beneath)」或「以下(below)」的其它元件或特徵將會被轉向為「上方(above)」的其它元件或特徵。因此,示例性術語「以下(below)」可以包含上方和下方的方位。此裝置可以其他方式定向(旋轉90度或處於其他方位上),而本案中使用之空間相對描述詞可相應地進行解釋。
在本文中所使用的「FET」縮寫,指的是場效電晶體。一種非常普遍的場效電晶體的類型被被稱為金氧半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor;MOSFET)。歷史性地說,金氧半導體場效電晶體是建構在與一基板的平面表面上的平面結構,基板例如是半導體晶圓。但近來半導體製造業上的進展已經導致垂直結構的使用。
術語「源/汲極(S/D)」當用於金氧半導體場效電晶體的脈絡下時,指的是場效電晶體所形成的四個端子的其中之二的源/汲極接點。
術語「源/汲極(S/D)」當用於無接面式場效電晶體的脈絡下時,指的是依據部分實施例的無接面式場效電晶體所形成的三個端子的其中之二的源/汲極接點。
術語「無接面式電晶體(junctionless transistor)」指的是具有一第一源/汲極端子,一第二源/汲極端子和一設置在第一和第二源/汲極端子之間的通道的電晶體架構。無接面式電晶體的通道具有高摻雜濃度,並且具有與第
一和第二源/汲極端子相同的導電類型。無接面式電晶體在本文中被稱為「無接面式場效電晶體(JLFET)」。在部分實施例中,超高摻雜是大於或等於每立方公分5×1018個原子(atoms/cm3)的摻雜濃度。當其第一和第二源/汲極端子和通道都是n型時,無接面式場效電晶體被稱為n型無接面式場效電晶體。同樣地,當其第一和第二源/汲極端子和通道都是p型時,無接面式場效電晶體被稱為p型無接面式場效電晶體。無接面式場效電晶體還包括設置在通道上並由閘極介電質分離的閘極電極。
「晶狀層」的表述在此指的是單晶半導體材料的一種層或結構。類似地,「磊晶成長」的表述在此指的是成長單晶半導體材料的一種層或結構。磊晶成長材料可以是摻雜的或不摻雜的。
術語「垂直的」在此指的是名義上垂直於基板的表面。
本揭露的各種相關實施例提供了製造具有三維交錯型非揮發性記憶體的積體電路的方法。根據部份實施例的方法是在相對低的熱預算內,將晶狀無接面式場效電晶體結合到三維交錯型非揮發性記憶體中。具體而言,摻雜的晶狀半導體材料層會從晶種晶圓轉移以形成無接面式場效電晶體的源極、汲極和連接通道。製造三維非揮發性記憶體的其它方法是在摻雜製程之後使用高溫退火步驟以結晶摻雜的源極和汲極區。習知退火製程不是在600℃下以數小時的固相結晶退火,就是在高溫(例如1100℃)下以幾納秒的短退火。這些過程需要
高的熱預算。使用轉移的摻雜結晶層來形成無接面式場效電晶體的一個好處是退火製程可以在無接面式場效電晶體結構轉移到基板上之前被執行,或者藉由直接將摻雜晶狀半導體層合併到無接面式場效電晶體結構中而被免除。
在描述與三維單片交錯型非揮發性記憶體結構的設計和製造有關的實施例之前,無接面式場效電晶體操作過程的一實施例先說明如下。
第1圖繪示了依據本揭露的一無接面式場效電晶體1的等角視圖。半導體奈米線結構,例如奈米線、鰭或奈米帶,形成一源極104S、一汲極104D和一被閘極電極108部分地圍繞的通道(由閘極介電質覆蓋並且在第1圖中不可見)。源極104S和汲極104D是半導體奈米線未被閘極電極108圍繞的部分。一閘極介電質106設置在閘極電極108和通道之間。因此,通道由閘極電極108和閘極介電質106覆蓋,而在第1圖中不可見。
在習知的金氧半導體場效電晶體中,源/汲極接點自對準到閘極結構。類似地,無接面式場效電晶體的源/汲極端子自對準到無接面式場效電晶體的閘極結構。
第2圖繪示了一實施例的n型無接面式場效電晶體。一第一源極/汲極端子(如源極204S)、一通道204C和一第二源極/汲極端子(如汲極204D)是由n型晶體矽半導體材料所圖案化。一閘極電極208是p摻雜的多晶矽。一閘極介電質206被設置在閘極電極208與通道204C之間。
第3圖繪示了一實施例的p型無接面式場效電晶
體。一第一源極/汲極端子304S、一通道304C和一第二源極/汲極端子304D是由p型晶體矽半導體材料所圖案化。一閘極電極308是n型的多晶矽。一閘極介電質306被設置在閘極電極308與通道304C之間。
第4A圖至第4C圖繪示了依據部分實施例的n型的示例操作狀態的多個視圖。具有各種閘極電壓VG(A)<VG(B)<VG(C)的裝置(以n型裝置為例)的操作如下:
如第4A圖所示,對於低閘極電壓,例如0伏特,在閘極電極208下方的通道204C耗盡載子,且沒有電流可在源極204S與汲極204D之間流動。此裝置實際上處於關閉狀態。
如第4B圖所示,對於較高的閘極電壓,例如0.4伏特,閘極電極208下方的通道204C部分地耗盡載子,且一些電流可在源極204S與汲極204D之間流動。
如第4C圖所示,對於更高的閘極電壓,例如1伏特,閘極電極208下的區域不再耗盡載子,並且可以在源極204S和汲極204D之間流動。裝置處於開啟狀態。
可理解的是,如果閘極電壓經由閘極下方的區域中的電子濃度的增加而增加到超過VG(C),則電流可進一步增加。
第5A圖至第5F圖繪示了包括無接面式場效電晶體的一半導體裝置在各個製造階段期間的各種視圖。這裡提供的製程是示例性的,並且未在這些圖中示出的許多其它步驟亦可以被執行。
如第5A圖所示,製程開始於一晶種晶圓500和一
裝置晶圓510。晶種晶圓500包括第一基板502和晶狀半導體層504'。晶種晶圓500還可以包括其它適合的層,例如其它介電層或注入層。其它適合的層可以放置在第一基板502和晶狀半導體層504'之間,或嵌入在第一基板502內。第一基板502作為一用以機械地支撐晶狀半導體層504'的晶種晶圓,且可包括任何適合的材料,例如矽。在部分實施例中,晶狀半導體層504'是一矽基材料。舉例而言,晶狀半導體層504'由晶體矽構成,並且可以具有各種不同的晶體取向,例如具有(100),(110)或(111)晶體取向。在一實施例中,晶狀半導體層504'經由磊晶成長製程直接形成在第一基板502上。舉例而言,晶狀半導體層504'可以是磊晶成長的矽或鍺化矽。在另一實施例中,晶狀半導體層504'的晶體結構經由固相磊晶(solid-phase epitaxial;SPE)再生長方法獲得。在另一實施例中,晶狀半導體層504'的晶體結構經由離子注入和退火或任何其它摻雜技術獲得。晶狀半導體層504'的頂表面可以由諸如二氧化矽層的氧化物層(圖中未示出)覆蓋。
在一實施例中,晶狀半導體層504'是摻雜半導體層。晶狀半導體層504'可以是摻雜有磷(Si:P)或摻雜有磷和碳(Si:CP)的n型摻雜矽層。碳可以阻礙磷從矽基材料向外擴散。在部分實施例中,晶狀半導體層504'可以是摻雜有砷的n型摻雜矽層。也可以包括其它類型的摻雜劑。在部分實施例中,磷摻雜劑濃度在每立方公分5×1018至5×1019個原子(atoms/cm3)的範圍內。在部分實施例中,碳摻雜劑濃度約在自0%至5%(原子百分比)的範圍內。晶狀半導體層504'也可以是p
型重摻雜矽層。舉例而言,晶狀半導體層504'可以用硼重摻雜。其它用於形成p型摻雜矽層的摻雜劑的類型亦可被包括,例如鎵或銦。離子注入已經被用作許多技術節點的摻雜製程。本揭露的實施例並不限於以離子注入作為晶狀半導體層504'的摻雜製程。一退火製程可在摻雜工藝之後被執行。
裝置晶圓510包括第二基板512和隔離層514。第二基板512可以是矽基板。可變地是,第二基板512可以包括另一種基本的半導體材料,諸如鍺;含有碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體;含有鍺化矽、磷砷化鎵、砷銦化鋁、砷鎵化鋁、磷銦化鎵、磷銦化鎵和/或磷砷銦化鎵的合金半導體;或其組合。第二基板512也可以是n型或p型摻雜的矽層。第二基板512可以是經處理的積體電路晶圓,例如包含多個電晶體被配置以形成互補式金氧半電晶體電路。這些電路可以包括由各種電晶體、電容器、電阻器和互連構成的邏輯、模擬、射頻(radio-frequency;RF)部件。隔離層514可以是層間介電質(inter-layer dielectric;ILD)或金屬間介電質(inter-metallization dielectric;IMD)層。舉例而言,隔離層514包括介電材料,如磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、氧碳化矽(SiOxCy)、旋塗式玻璃、旋塗式聚合物、矽碳材料及其化合物,藉由本領域中已知的任何適合方法,例如旋塗、化學氣相沉積(CVD)和電漿增強化學氣相沉積(PECVD),可以形成這些材料及其組合等。還應注意的是,隔離層514可以包括嵌入有金屬互連的多個介電層,例如銅互連和鎢、鈷或氮化鈦通孔。
裝置晶圓510還可以包括邏輯電路、互補式金氧半電晶體電路、類比數位轉換器、數據處理電路、記憶體電路、偏壓電路、參考電路及其類似電路。
第5B圖繪示了用於接合晶種晶圓500和裝置晶圓510的接合製程。舉例而言,在來自晶種晶圓500的晶狀半導體層504'和來自裝置晶圓510的隔離層514彼此面對時,晶種晶圓500和裝置晶圓510使用直接接合製程,諸如介電質到介電質接合(例如氧化物到氧化物接合)、金屬到介電質接合(例如氧化物到銅的接合)、其任何組合及/或類似物。接合發生在晶種晶圓500的頂表面(即晶狀半導體層504'的表面)與裝置晶圓510的頂表面(即隔離層514的表面)之間。在接合之前,要接合的晶圓的表面會被清潔以從晶圓表面去除任何殘留的液體或顆粒。接合製程會形成一晶圓組件520。
接合可以在一晶圓階段,其中晶種晶圓500和裝置晶圓510結合在一起,然後分離。或者,可以處於晶粒到晶粒階段,或者晶粒到晶圓階段執行接合。
如第5C圖所示,一薄化製程被執行,以從晶圓組件520移除第一基板502。薄化製程藉由使用諸如研磨和化學機械拋光(CMP)的適當技術來實施。除了薄化製程之外,還需要結合和分離製程。作為薄化製程的結果,第一基板502被移除或分離,且晶狀半導體層504'被暴露出來。
晶狀半導體層504'被進一步處理以形成奈米線、鰭或奈米帶(以下稱為「奈米線」504)。奈米線504用以作為無接面式場效電晶體的源極/汲極和通道區域。奈米線504自晶狀
半導體層504'微影蝕刻地被圖案化,其使用包括但不限於形成和圖案化抗蝕劑層、蝕刻暴露的部分以及剝離圖案化的抗蝕劑的熟知製程操作。儘管第5C圖繪示了奈米線504具有矩形的橫截面面積,奈米線504可以以任何適合的形狀形成。
第5D圖至第5F圖繪示了由製造n型無接面式場效電晶體的一實施例過程產生的各種中間結構的等角視圖。一n型無接面式場效電晶體可以使用前述的晶圓組件520製造。在本示例性實施例中,奈米線504是摻雜的n型晶體矽材料,隔離層514包括嵌入有銅互連的層間介電層,且第二基板512包括摻雜的p型矽材料。第二基板512和隔離層514可以包括邏輯電路、互補式金氧半電晶體電路、類比數位轉換器、數據處理電路、記憶體電路、記憶體控制電路、偏壓電路、參考電路及其類似電路。在部分實施例中,晶圓組件520包括位於奈米線504和隔離層514之間的界面處的絕緣體層(未在第5D圖至第5F圖中示出)。
在第5E圖中,一閘極介電層206'被形成而圍繞奈米線504的至少一部分。在一實施例中,閘極介電層206'最初沉積在奈米線504和隔離層514的暴露表面上。對於一電荷俘獲非揮發性記憶體陣列而言,閘極介電層206'是材料例如但不限於氧化物-氮化物-氧化物(ONO)的堆疊。ONO堆疊在矽表面上是可靠的,並且通常用作電容器絕緣體。ONO堆疊可藉由熱氧化矽表面以形成超薄底部氧化物層、沉積一低壓化學氣相沉積氮化矽層以及氧化氮化矽層以形成頂部氧化物層而形成。其它材料諸如氧化氮、氧化鉭、二氧化鈦、鋯鈦酸鉛(PZT)
或鋇鍶(BST)可被用以作為閘極介電層206'。
如第5F圖所示,一個或多個閘極電極208被形成而圍繞閘極介電層206'的一部分,以形成n型無接面式場效電晶體。閘極介電層206'與閘極電極208接觸的部分形成多個閘極介電質206,由於其被閘極電極208所覆蓋,因此未見於第6圖中。閘極介電質206和閘極電極208共同包括了閘極區域,其被配置以控制連接源極/汲極區的通道區域的導電性。閘極電極208可以形成自任何適合的金屬或導電材料,例如一氮化鈦、鉑、鎳、矽化物、摻雜的p型矽材料、或其他材料,或其組合。閘極電極208可以使用微影蝕刻閘極優先製程或鑲嵌製程形成。在一實施例中,閘極介電層206'可被進一步處理以僅在閘極電極208下保留,如此,源極/集流極區域將被暴露以進行進一步處理。因此,n型無接面式場效電晶體包括源極/汲極區域,通道區域和包括閘極介電質206和閘極電極208的閘極區域。第5F圖繪示了多個無接面式場效電晶體,其與多個具有一對源/汲極端子的每一個無接面式場效電晶體以串聯形式連接。
在第6圖中,p型無接面式場效電晶體使用與前述參照第5A圖至第5F圖的類似製程而形成。在本示例性實施例中,奈米線504是以諸如硼、鎵或銦的p型摻雜劑重摻雜。第二基板512也可以是摻雜有n型、p型或H型摻雜劑的矽層。第二基板512也可以是未摻雜的矽層。此外,第二基板512可以是例如互補式金氧半電晶體電路的處理過的積體電路晶圓。這些電路可以包括由各種電晶體、電容器、電阻器和互連構成的
邏輯、模擬、射頻部件。因此,n型無接面式場效電晶體包括源極/汲極區域,通道區域和包括閘極介電質306和閘極電極308的閘極區域。由於閘極介電質306被閘極電極308所覆蓋,因此僅有閘極介電層306'見於第6圖中。
前述參照第1圖至第6圖的無接面式場效電晶體可被用形成各種結構,例如但不限於下述參照第7圖至第8F圖的三維非揮發性記憶體陣列。
第7圖繪示了包括無接面式場效電晶體的電荷俘獲非揮發性記憶體陣列700的上視圖。在本示例性實施例中,奈米線504和閘極電極108分別作為位元線和字元線,以形成具有交錯型結構的非揮發性記憶體陣列。如此,非揮發性記憶體陣列700的記憶胞位於字元線和位元線的交叉處,而允許記憶胞個別地被定址。閘極介電質106(未示於圖7中)也形成在每個無接面式場效電晶體處。閘極介電質106可以是適合的電荷俘獲堆疊材料,例如氧化物-氮化物-氧化物(ONO)。非揮發性記憶體陣列700可以形成在裝置晶圓510上(未示於圖7中),而如下所詳述。
第8A圖描繪了一實施例在晶狀半導體層504'轉移之前的裝置晶圓510沿圖7的截面702截取的橫截面圖。如前參照第5A圖之所述,裝置晶圓510可以包括在其中及/或其上形成的一個或多個裝置或特徵。此種一個或多個裝置或特徵的例子被繪示於第8A圖中,其包括在第二基板512和隔離層514中形成的金屬互連803和電晶體805。可以存在多個與金屬互連803和電晶體805鑲嵌的隔離層514'。金屬互連803,如銅通
孔,提供用於裝置晶圓510不同部分的電性連接。在一示例性實施例中,隔離層514可以是嵌有銅通孔的層間介電層。
第8B圖繪示了具有轉移的晶狀半導體層504'形成在頂表面上的裝置晶圓510沿圖7的截面702截取的橫截面圖。如前參照第5A圖至第5C圖之所述,晶狀半導體層504'可以藉由適合的晶圓接合方法自晶種晶圓500轉移。舉例而言,直接接合製程、金屬至介電質接合製程,它們的任何組合及/或類似物。晶狀半導體層504'被所需類型和濃度的摻雜劑摻雜,以在轉移製程之前用於製造n型或p型無接面式場效電晶體。
第8C圖繪示了已進一步處理以形成奈米線504之後的晶狀半導體層504'。如第8C圖所示,多個奈米線504形成在隔離層514上。奈米線504是用以作為無接面式場效電晶體的源極、汲極和通道區域。藉由包括微影和蝕刻製程的適合製程,奈米線504自晶狀半導體層504'被圖案化。多個奈米線504是用以作為三維非揮發性記憶體陣列700的位元線。
在第8D圖中,類似於前述參照第5A圖的製程,閘極區域,其包括閘極介電質106(未示出)和閘極電極108,形成在多個奈米線504上。如第7圖和第8D圖所示,每個閘極電極108可以用於控制對應的無接面式場效電晶體。在本示例性實施例中,每個無接面式場效電晶體用以作為非揮發性記憶胞。一第二隔離層804被示出形成在多個無接面式場效電晶體上。在進一步的實施例中,第二隔離層804提供用以堆疊額外記憶體陣列的表面。類似於隔離層514,第二隔離層804可以
是藉由本領域已知的任何適合方法例如旋塗、化學氣相沉積和電漿增強化學氣相沉積,而由低介電係數介電材料形成的層間介電層。第二隔離層804可以類似地包括嵌入有金屬互連的多個介電層。
在第8E圖中,連接閘極電極108與金屬互連803的字元線互連803W形成在隔離層514與第二隔離層804中,提供在裝置晶圓510中的非揮發性記憶體陣列700與電晶體805之間的垂直電性連接。與每平方毫米2.5十億位元(gigabits)相較,這種三維交錯型架構創建了具有更高的儲存密度和更小的裝置訊號足跡的結構。字元線互連803W可以是金屬互連,例如導電通孔或導線,並且也可以是一多層互連(multilayer interconnection;MLI),其包括垂直和水平互連,如習知通孔或接點,以及水平互連,如金屬線。多層互連結構可以包括導線、導電通孔及/或插入介電層,例如層間介電質。多層互連結構還提供至電晶體與在電晶體之間的電性連接。各種級別的導線可以包括銅、鋁、鎢、鉭、鈦、鎳、鈷、金屬矽化物、金屬氮化物、多晶矽、其組合,及/或可能包括一個或多個層或襯層的其它材料。襯層包括黏合層、阻障層、蝕刻停止層和抗反射塗層。插入層或層間介電層(例如ILD層)可以包括二氧化矽、氟化矽玻璃(FSG)或至少一種低介電係數介電材料。多層互連可以藉由製造互補式金氧半電晶體電路的典型適合製程形成,例如但不限於化學氣相沉積、物理氣相沉積、原子層沉積、電鍍、旋轉式塗佈及/或其它製程。在一個例子中,金屬嵌入製程用於形成銅多層互連結構。在一示例性金屬嵌入製
程中,一開口形成在介電層中,其分離垂直間隔的金屬化層。開口通常使用習知的微影和蝕刻技術形成。在形成之後,開口被氮化鈦、鎢或其它金屬、金屬合金或金屬及/或金屬合金的疊層填充以形成通孔。然後藉由化學機械拋光去除介電層表面上的過量金屬材料。銅或導電材料形成連接到通孔的互連線。
第8F圖繪示了示例性非揮發性記憶體陣列700和裝置晶圓510在形成位元線互連803B後沿圖7的截面704截取的橫截面圖。位元線互連803B也提供在裝置晶圓510中的非揮發性記憶體陣列700與電晶體805之間的垂直電性連接。位元線互連803B也可以是金屬互連,例如但不限於鎢通孔或導線。位元線互連803B的不同層可以用於連接上述各種特徵。位元線互連803B也可以是一多層互連,其包括垂直和水平互連,如習知通孔或接點,以及水平互連,如金屬線。在一個例子中,金屬嵌入製程用於形成銅基多層互連結構。
第9圖是使用晶狀無接面式場效電晶體形成三維交錯型非揮發性記憶體陣列的說明性方法900的流程圖。其它操作可以在方法900的各種操作之間被執行。
方法900開始於操作步驟902,提供一基板,具有一個或多個裝置或特徵形成於其中或其上。基板可以包括多層,例如層間介電層、介電層或注入層,並且可以具有嵌入其中的裝置或電性互連。在部分實施例中,基板是具有一個或多個裝置或特徵形成在其中或其上的大塊矽晶圓。
方法900繼續進行操作步驟904,將半導體層轉移到基板,其中半導體層是摻雜的晶狀半導體層。晶狀半導體層
可以是晶種晶圓的一部分或附接到一種子層。晶狀半導體層在轉移製程之前,是用適於n型或p型無接面式場效電晶體的所需摻雜劑類型和濃度來摻雜。轉移製程可以從把半導體層接合到基板開始。直接接合製程、金屬與介電質接合製程及其任何組合等可被使用。如果半導體層被附接到晶種層或為晶種晶圓的一部分,則轉移製程可以繼續移除晶種層或晶種晶圓的剩餘部分。移除製程藉由使用諸如研磨和化學機械拋光、智能切割(Smart Cut)製程、磊晶層轉移(ELTRAN)製程及/或化學蝕刻的適當技術來實施。作為薄化製程的結果,晶種晶圓的晶種層或剩餘部分被去除,且晶狀半導體層被轉移到基板,並被暴露以用於後續處理。
方法900繼續進行操作步驟906,自摻雜的晶狀半導體層形成奈米線。奈米線隨後用以作為無接面式場效電晶體的源極/汲極和通道區域。奈米線可以使用包括微影與蝕刻製程的適合製程自晶狀半導體層被製造。奈米線可以被圖案化成任何適合的形狀。
方法900繼續進行操作步驟908,在奈米線的一部分的周圍形成閘極介電質與閘極電極。閘極介電質可以包括高介電係數介電材料,氧化物-氮化物-氧化物(ONO)材料堆疊或其他適合的材料,並且可以通過原子層沉積、電漿增強化學氣相沉積及/或其他適合的沉積製程形成。閘極電極形成在閘極介電質的一部分上。閘極電極和閘極介電質共同包括了閘極區域,其被配置以控制通道區域的導電性。閘極電極可以包括任何適合的導電材料,並且可以使用微影蝕刻閘極優先製程或
鑲嵌製程形成。晶狀奈米線和閘極電極分別作為位元線和字元線,以形成具有交錯型結構的非揮發性記憶體陣列。如此,非揮發性記憶體的記憶胞位於字元線和位元線的交叉處,而允許記憶胞個別地被定址。
方法900繼續進行操作步驟910,形成用以為非揮發性記憶體陣列提供電性連接的互連。互連包括位元線互連和字元線互連,並且形成在層間介電層或基板中,以提供非揮發性記憶體陣列與其它電路和電源之間的電性連接。這種三維交錯型架構創建了具有更高的儲存密度和更小的裝置訊號足跡的結構。位元線和字元線互連可以是金屬互連,例如通孔或導線。
依據本揭露的實施例的一個優點是無需熱處理即可創建無接面式場效電晶體。上述的所有操作,包括接合晶種晶圓500,移除第一基板502,蝕刻、形成源極/汲極和通道區域,以及形成閘極介電質106和閘極電極108,是在低溫下執行,其不會對裝置晶圓510或形成的晶圓組件520造成損害。在一實施例中,所有處理步驟皆是在小於600℃的溫度下執行。這種低溫處理製程使得此一裝置的堆疊數層能以每層的附加製程是以包括不會對先前形成的裝置層造成損害的低溫處理製程的形式而可行。
依據本揭露的實施例的另一個優點是為了形成摻雜晶狀半導體層504'而所需或可能需要加熱的其他製程,例如結晶、離子植入或退火,可在接合與轉移製程之前執行。這防止在下層中形成的裝置(例如,在裝置晶圓510中形成的一個
或多個裝置或特徵)會被用於製造具有晶狀源極、汲極以及通道區域的無接面式場效電晶體中使用的處理溫度損壞。
在一個實施例中,一種形成非揮發性記憶胞陣列的方法提供了一基板,其具有一上介電層與位於所述上介電層下方的多個電晶體。一多層互連被形成在這些電晶體上。所述基板可以是大塊晶圓。一摻雜晶狀半導體層被設置在所述上介電層上,且被蝕刻以形成相對於所述基板表面的水平定向的多個奈米線。一電荷俘獲堆疊層被形成在所述多個奈米線上。多個閘極電極被形成在所述電荷俘獲堆疊層上。一第一互連被形成在所述多個奈米線的一第一奈米線和所述多個電晶體中的一第一電晶體之間。一第二互連被形成在所述多個閘極電極的一第一閘極電極和所述多個電晶體中的一第二電晶體之間。
在另一實施例中,一種形成無接面式場效電晶體基的非揮發性記憶體的方法提供了一基板,具有一第一介電層與位於所述第一介電層下方的多個電晶體。一多層互連被形成在這些電晶體上。一摻雜晶狀半導體層被設置在所述第一介電層上,且被蝕刻以在所述第一介電層上形成多個摻雜晶狀半導體結構。多個閘極結構被形成在所述多個摻雜晶狀半導體結構的每一個上。一第一電性連接互連被形成在所述多個摻雜晶狀半導體結構的一第一摻雜晶狀半導體結構和所述多個電晶體中的一第一電晶體之間。一第二電性連接互連被形成在所述多個閘極結構的一第一閘極結構和所述多個電晶體中的一第二電晶體之間。所述多個閘極結構的各閘極結構包括一閘極電極。
在又一實施例中,一種無接面式場效電晶體基的非揮發性記憶體結構,包括具有一第一介電層與位於所述第一介電層下方的多個電晶體以及位在所述第一介電層上的多個摻雜晶狀半導體結構的一基板。無接面式場效電晶體基的非揮發性記憶體結構更包括位在這些電晶體上的一多層互連以及位在所述多個摻雜晶狀半導體結構的每一個上的多個閘極結構。此無接面式場效電晶體基的非揮發性記憶體結構更包括電性耦接在所述多個摻雜晶狀半導體結構的一第一摻雜晶狀半導體結構和所述多個電晶體中的一第一電晶體之間的一第一互連以及電性耦接在所述多個閘極結構的一第一閘極結構和所述多個電晶體中的一第二電晶體之間的一第二互連。
應當理解的是,具體實施方式,並非本揭露的發明內容或摘要的部分,其旨在用於解釋申請專利範圍。本揭露的發明內容和摘要的部分可以闡述一個或多個,但並非所有的示例性實施例,因此並不用於限制所附的申請專利範圍。
上文概述了若干實施例的特徵,以便本領域熟習此項技藝者可更好地理解本揭露的態樣。本領域熟習此項技藝者應當瞭解到他們可容易地使用本揭露作為基礎來設計或者修改其他製程及結構,以實行相同目的及/或實現相同優勢的。本領域熟習此項技藝者亦應當瞭解到,此類等效構造不脫離本揭露的精神及範疇,以及在不脫離本揭露的精神及範疇的情況下,其可對本文進行各種改變、取代及變更。
900‧‧‧方法
902、904、906、908、910‧‧‧操作步驟
Claims (10)
- 一種形成非揮發性記憶胞陣列的方法,包括:提供一基板,具有一上介電層與位於該上介電層下方的多個電晶體;形成一多層互連,在該些電晶體上;形成一摻雜晶狀半導體層;設置該摻雜晶狀半導體層在該上介電層上;蝕刻該摻雜晶狀半導體層以形成相對於該基板表面的水平定向的多個奈米線;形成一電荷俘獲堆疊層,在該多個奈米線上;形成多個閘極電極,在該電荷俘獲堆疊層上;形成一第一互連,在該多個奈米線的一第一奈米線和該多個電晶體中的一第一電晶體之間;以及形成一第二互連,在該多個閘極電極的一第一閘極電極和該多個電晶體中的一第二電晶體之間;其中該基板是大塊晶圓。
- 如申請專利範圍第1項所述之方法,更包括在該上介電層上設置該摻雜晶狀半導體層之前,注入至少一種摻雜劑物質到一半導體層中,以形成摻雜晶狀半導體層。
- 如申請專利範圍第1項所述之方法,其中該多個閘極電極被佈置成相對於該基板表面的水平定向,且相對於該奈米線的垂直定向的多行中。
- 一種形成無接面式場效電晶體基的非揮發性記憶體的方法,包括:提供一基板,具有一第一介電層與位於該第一介電層下方的多個電晶體;形成一多層互連,在該些電晶體上;設置一摻雜晶狀半導體層在該第一介電層上;蝕刻該摻雜晶狀半導體層以在該第一介電層上形成多個摻雜晶狀半導體結構;形成多個閘極結構在該多個摻雜晶狀半導體結構的每一個上;形成一第一電性連接互連,在該多個摻雜晶狀半導體結構的一第一摻雜晶狀半導體結構和該多個電晶體中的一第一電晶體之間;以及形成一第二電性連接互連,在該多個閘極結構的一第一閘極結構和該多個電晶體中的一第二電晶體之間;其中該多個閘極結構的各閘極結構包括一閘極電極。
- 如申請專利範圍第4項所述之方法,其中形成該多個閘極結構包括沉積一氧化物-氮化物-氧化物的電荷俘獲堆疊層於該多個摻雜晶狀半導體結構上。
- 一種無接面式場效電晶體基的非揮發性記憶體結構,包括:一基板,具有一第一介電層與位於該第一介電層下方的多個電晶體; 一多層互連,位在該些電晶體上;多個摻雜晶狀半導體結構,位在該第一介電層上;多個閘極結構,位在該多個摻雜晶狀半導體結構的每一個上;一第一互連,電性耦接在該多個摻雜晶狀半導體結構的一第一摻雜晶狀半導體結構和該多個電晶體中的一第一電晶體之間;以及一第二互連,電性耦接在該多個閘極結構的一第一閘極結構和該多個電晶體中的一第二電晶體之間。
- 如申請專利範圍第6項所述之無接面式場效電晶體基的非揮發性記憶體結構,其中該多個摻雜晶狀半導體結構是被n摻雜至於每立方公分5×1018至5×1019個原子(atoms/cm3)的範圍內的摻雜濃度。
- 如申請專利範圍第6項所述之無接面式場效電晶體基的非揮發性記憶體結構,其中該多個摻雜晶狀半導體結構是被p摻雜至於每立方公分5×1018至5×1019個原子(atoms/cm3)的範圍內的摻雜濃度。
- 如申請專利範圍第6項所述之無接面式場效電晶體基的非揮發性記憶體結構,其中該多個閘極結構的該第一閘極結構包括一電荷俘獲閘極介電堆疊,且更包括一在電荷俘獲閘極介電堆疊上的電性導電閘極電極。
- 如申請專利範圍第9項所述之無接面式場效電晶體基的非揮發性記憶體結構,其中該多個摻雜晶狀半導體結構是被佈置在多個縱行上,且該多個閘極結構是被佈置在多個橫列上。
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