TWI595654B - Ldmos device for esd protection circuit - Google Patents

Description

Transverse double-diffused MOS device for electrostatic discharge protection circuit

The present invention relates to a semiconductor device, and more particularly to a lateral double diffused metal oxide semiconductor (LDMOS) device for an electrostatic protection discharge protection circuit.

Electrostatic discharge (ESD) is a phenomenon of electrostatic movement from a non-conductive surface, which causes damage to the semiconductor and other circuit components in the integrated circuit. For example, when a common body such as a human body walking on a carpet, a machine for packaging an integrated circuit, or an instrument for testing an integrated circuit contacts a wafer, it will discharge to the wafer, and the instantaneous power of the electrostatic discharge may cause The integrated circuit in the wafer is damaged or fails.

Therefore, in order to prevent the electrostatic discharge from damaging the semiconductor integrated circuit component, various methods for preventing electrostatic discharge are generated. One of the most common methods is to use hardware to prevent this electrostatic discharge, that is, an electrostatic discharge protection circuit is designed between the internal device and each pad to protect its internal components.

The lateral double diffused N-type metal oxide semiconductor (LDNMOS) component is an electronic component widely used in power management applications. When the internal component is a high voltage component such as a large-sized output driver, its output driver is coupled to its control circuit, and the LDNMOS component, which acts as an electrostatic discharge protection component, has its gate gate-grounded. However, in the case of instantaneous electrostatic discharge, The gate of the output driver will float, and the output driver's triggering voltage will be equal to or even less than the trigger voltage of the LDNMOS device that is the ESD protection component. As a result, the output driver may be activated faster than the LDNMOS device used for the ESD protection circuit, causing the LDNMOS device for the ESD protection circuit to lose its function of protecting the output driver.

Therefore, how to design an LDNMOS device for an ESD protection circuit that can be started faster than an internal component has become one of the most important topics in the industry.

The present invention provides an LDNMOS device for an ESD protection circuit that can be activated faster than a protected internal circuit.

The present invention provides a lateral double diffused metal oxide semiconductor (LDMOS) device for an electrostatic discharge protection circuit. The LDMOS device includes a substrate having a first conductivity type, a deep well region having a second conductivity type, a base region having a first conductivity type, a first doping region having a second conductivity type, and a second conductivity type having a second conductivity type Doped region and gate. The deep well area is located in the basement. The base area is located in the deep well area. The first doped region is located in the deep well region. The second doped region is located in the base region. The gate is located on the deep well region between the first doped region and the second doped region. It is particularly noted that the base region does not include a doped region having a first conductivity type but a different doping concentration than the substrate region.

In an embodiment of the invention, the LDMOS device for the electrostatic discharge protection circuit further includes an isolation structure and a floating region having a second conductivity type. The isolation structure is between the gate and the first doped region. Floating area surrounded by Around at least a portion of the isolation structure, the first doped region is located outside of the floating region and adjacent to the floating region.

In an embodiment of the invention, the isolation structure comprises a field oxide layer (FOX) structure or a shallow trench isolation (STI) structure.

In an embodiment of the invention, the LDMOS device for the ESD protection circuit further includes a contact window connecting the base region and the second doped region in the base region.

In an embodiment of the invention, the contact window is coupled to the source power source, and the first doped region is coupled to the drain power source.

In an embodiment of the invention, the junction of the contact window and the base region is a shottky contact.

In an embodiment of the invention, the first conductivity type is a P type, and the second conductivity type is an N type.

In an embodiment of the invention, the first conductivity type is an N type, and the second conductivity type is a P type.

In an embodiment of the invention, the LDMOS device for the electrostatic discharge protection circuit further includes a well region having a first conductivity type and a third dopant region having a first conductivity type. The well area is located on the periphery of the deep well area. The third doped region acts as a guard ring located in the well region and the third doped region is grounded.

The present invention further provides a lateral double diffused metal oxide semiconductor (LDMOS) device for an electrostatic discharge protection circuit. The LDMOS device includes a substrate having a first conductivity type, a deep well region having a second conductivity type, a base region having a first conductivity type, a first doping region having a second conductivity type, and a second conductivity type having a second conductivity type Doped regions, gates and contact windows. Deep well area is located at the base in. The base area is located in the deep well area. The first doped region is located in the deep well region. The second doped region is located in the base region. The gate is located on the deep well region between the first doped region and the second doped region. The contact window only connects the substrate region and the second doped region in the substrate region.

In an embodiment of the invention, the LDMOS device for the electrostatic discharge protection circuit further includes an isolation structure and a floating region having a second conductivity type. The isolation structure is between the gate and the first doped region. The floating zone surrounds at least a portion of the isolation structure, the first doped region being located outside of the floating zone and adjacent to the floating zone.

In an embodiment of the invention, the isolation structure comprises a field oxide layer structure or a shallow trench isolation structure.

In an embodiment of the invention, the contact window is coupled to the source power source, and the first doped region is coupled to the drain power source.

In an embodiment of the invention, the junction between the contact window and the substrate region is a Schuma contact.

In an embodiment of the invention, the first conductivity type is a P type, and the second conductivity type is an N type.

In an embodiment of the invention, the first conductivity type is an N type, and the second conductivity type is a P type.

In an embodiment of the invention, the LDMOS device for the electrostatic discharge protection circuit further includes a well region having a first conductivity type and a third dopant region having a first conductivity type. The well area is located on the periphery of the deep well area. The third doped region acts as a guard ring located in the well region and the third doped region is grounded.

An LDMOS device for an electrostatic discharge protection circuit of the present invention, The resistance value is higher than the conventional LDMOS device used for the ESD protection circuit, so the trigger voltage is low and can be started faster to protect the internal circuit.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a cross-sectional view of an LDMOS device for an ESD protection circuit in accordance with an embodiment of the invention.

Hereinafter, the first conductivity type is a P type, and the second conductivity type is an N type, but the invention is not limited thereto. Those skilled in the art will appreciate that the first conductivity type can be replaced by an N type and the second conductivity type can be replaced with a P type.

Referring to FIG. 1, the LDMOS devices 10, 20 for an ESD protection circuit include a substrate 100 having a first conductivity type and a deep well region 102 having a second conductivity type. Hereinafter, the LDMOS elements 10 and 20 for the electrostatic discharge protection circuit will be described in detail as an example, but are not intended to limit the present invention, and the present invention does not particularly limit the number of LDMOS elements. The substrate 100 is, for example, a P-type substrate. The deep well zone 102 is, for example, an N-type deep well zone located within the substrate 100.

The LDMOS device 10 for an electrostatic discharge protection circuit further includes a gate 110a, a first doped region 106 having a second conductivity type, a second doped region 108a having a second conductivity type, and a substrate having a first conductivity type Area 104a. The LDMOS device 20 for an electrostatic discharge protection circuit further includes a gate 110b, a first doped region 106 having a second conductivity type, and a second conductive A second doped region 108b of the type and a base region 104b having a first conductivity type.

The base regions 104a, 104b are, for example, P-type base regions located in the deep well region 102. The first doped region 106 is, for example, an N+ doped region, also located in the deep well region 102, as a common drain region for the LDMOS devices 10, 20 of the ESD protection circuit.

The second doped regions 108a, 108b are, for example, N+ doped regions, respectively serving as source regions for the LDMOS devices 10, 20 of the ESD protection circuit. The second doped regions 108a, 108b are located in the base regions 104a, 104b, respectively.

The gate 110a is located on the deep well region 102 between the first doped region 106 and the second doped region 108a. The gate 110b is located on the deep well region 102 between the first doped region 106 and the second doped region 108b. In an embodiment, the gates 110a, 110b are electrically connected to each other.

In particular, the doped regions having the first conductivity type but having different doping concentrations than the substrate regions 104ba, 104b are not included in the base regions 104ba, 104b. In an embodiment, when the base regions 104a, 104b are, for example, P-type base regions, there is no P+ doped region in the base regions 104a, 104b, but there may be an N-type doped region, such as the second doped region 108a, 108b.

In one embodiment, the LDMOS elements 10, 20 for the ESD protection circuit further include isolation structures 101a, 101b and floating regions 112a, 112b having a second conductivity type, respectively. The isolation structures 101a, 101b are, for example, field oxide layer (FOX) structures or shallow trench isolation (STI) structures. The isolation structure 101a is located between the gate 110a and the first doped region 106; the isolation structure 101b is located between the gate 110b and the first doped region 106. The floating areas 112a, 112b are, for example, N-type floating areas, respectively surrounding at least a portion of the isolation structure 101a, Around 101b, and adjacent to the first doped region 106.

In addition, the LDMOS elements 10, 20 for the electrostatic discharge protection circuit may also include contact windows 114a, 114b, respectively. The contact window 114a connects the base region 104a and the second doped region 108a in the base region 104a. The contact window 114b connects the base region 104b and the second doped region 108b in the base region 104b. The contact windows 114a, 114b are all coupled to the source power source, and the first doped region 106 is coupled to the drain power source.

Since the doped regions having the first conductivity type but different doping concentrations from the base regions 104ba, 104b, such as the P+ doped regions, are not included in the base regions 104ba, 104b, the contact windows 114a, 114b are not connected to the P+ doped regions. . Since the doping concentration of the base regions 104a, 104b is not high, the junction formed by the contact windows 114a, 114b and the base regions 104a, 104b is aShottky contact and has a large junction resistance. On the other hand, since the doping concentration of the second doping regions 108a, 108b is sufficiently high, the junction formed by the contact windows 114a, 114b and the second doping regions 108a, 108b is an ohmic contact. Small junction resistance.

The LDMOS device 10, 20 for an electrostatic discharge protection circuit of the present invention may also include well regions 116a and 116b having a first conductivity type, third doping regions 118a and 118b having a first conductivity type, and a third doping region. 118a and 118b are used as guard rings. Well zones 116a, 116b are located at the periphery of deep well zone 102, respectively. The third doped regions 118a, 118b are respectively located in the well regions 116a, 116b, and the third doped regions 118a, 118b are grounded.

In the LDMOS device 10 for an electrostatic discharge protection circuit of the present invention, the pnp formed by the base region 104a, the deep well region 102, and the substrate 100 A parasitic bipolar junction transistor (BJT) is coupled to the source power source through the base region 104a. Since the doping concentration of the base region 104a is low, the resistance is high, and the contact between the contact window 114a and the base region 104a also has a large junction resistance, so when the same pulse current passes, because the voltage = Current × resistance (V = I × R), therefore, the parasitic BJT will be triggered and activated quickly. As a result, the trigger voltage of the LDMOS device 10 for the ESD protection circuit is lowered, so that the LDMOS device for the ESD protection circuit is turned on first, and the internal component is protected. In addition, the LDMOS device 20 is similar to the LDMOS device 10 and will not be described herein.

Next, the LDMOS device for an electrostatic discharge protection circuit of the present invention and a conventional LDMOS device for an electrostatic discharge protection circuit will be compared to confirm the effects of the present invention. 2 is a diagram showing the current obtained by measuring an LDMOS device for an electrostatic discharge protection circuit of FIG. 1 and a conventional LDMOS device for an electrostatic discharge protection circuit using a Transmission Line Pulsing System (TLP System). Diagram of the relationship with voltage (IV) characteristics. The conventional LDMOS device (dashed line) and the LDMOS device (solid line) of the present invention are 40V LDNMOS devices of the same size for the ESD protection circuit.

Hereinafter, the mechanism of the electrostatic discharge protection circuit of the present invention will be described by taking the LDMOS device 10 as an example. In the LDMOS device 10, when the pulse current increases to the electrostatic discharge zapping, since the junction between the base region (base) 104a and the contact window 114a is a Schottky contact, the resistance value is large, so Parasitic BJT composed of doped region 108a, base region 104a, and deep well region 102 It will be turned on faster, so the LDMOS device used for the ESD protection circuit has a lower trigger voltage, such as the voltage at point A (60V) is lower than the voltage at the conventional A' point (75V). Then, the LDMOS element 10 for the electrostatic discharge protection circuit of the present invention is turned on, so that the IV curve of the LDMOS element 10 for the electrostatic discharge protection circuit of the present invention enters the snapback region (between BC), and Failed at point C.

The trigger voltage of the LDMOS device used in the ESD protection circuit is about 75V, and the trigger current is about 55mA. The trigger voltage of the LDMOS for the ESD protection circuit of the present invention is about 60V, and the trigger current is about 14mA. . It can be seen that the LDMOS device for the electrostatic discharge protection circuit of the present invention does not form a higher concentration of the same type doped region in the base region, and the LDMOS for the electrostatic discharge protection circuit can be started faster than the conventional one. Achieve the purpose of protecting internal components.

In addition, the LDMOS device for the electrostatic discharge protection circuit of the present invention has a lower holding voltage and a higher second breakdown current than the conventional LDMOS device for the electrostatic discharge protection circuit. Therefore, the ability to protect against electrostatic discharge can be improved.

In summary, the LDMOS device for the electrostatic discharge protection circuit of the present invention has a dense doped region of the same type in the base region, so that it is in contact with the contact window, and the contact resistance is better than the conventional one. The LDMOS component of the ESD protection circuit is high, so the trigger voltage can be greatly reduced, and it can be activated more quickly to achieve the purpose of protecting the internal components. In addition, the LDMOS device for the electrostatic discharge protection circuit of the present invention can be applied to all power management ICs. The process is simple, no need to add new processes or masks, which can save costs and enhance competitiveness.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20‧‧‧LDMOS components

100‧‧‧Base

101a, 101b‧‧‧ isolation structure

102‧‧‧Shenjing District

104a, 104b‧‧‧ base area

106, 108a, 108b, 118a, 118b‧‧‧ doped areas

110a, 110b‧‧‧ gate

112a, 112b‧‧‧ drift zone

114a, 114b‧‧‧Contact window

116a, 116b‧‧‧ well area

1 is a cross-sectional view of an LDMOS device for an ESD protection circuit in accordance with an embodiment of the invention.

2 is a graph showing the relationship between current and voltage (IV) characteristics of an LDMOS device for an electrostatic discharge protection circuit of the present invention and a conventional component for an electrostatic discharge protection circuit LDMOS measured by a transmission line wave generator. .

10, 20‧‧‧LDMOS components

100‧‧‧Base

101a, 101b‧‧‧ isolation structure

102‧‧‧Shenjing District

104a, 104b‧‧‧ base area

106, 108a, 108b, 118a, 118b‧‧‧ doped areas

110a, 110b‧‧‧ gate

112a, 112b‧‧‧ drift zone

114a, 114b‧‧‧Contact window

116a, 116b‧‧‧ well area

120‧‧‧Protection ring

Claims (15)

A lateral double-diffused metal oxide semiconductor (LDMOS) device for an electrostatic discharge protection circuit, comprising: a substrate having a first conductivity type; and a deep well region having a second conductivity type, located in the substrate; a substrate region of a conductivity type, located in the deep well region; having a first doped region of the second conductivity type, located in the deep well region; and having a second doping region of the second conductivity type a base region; and a gate on the deep well region between the first doped region and the second doped region; an isolation structure between the gate and the first doped region; Having a floating region of the second conductivity type, surrounding at least a portion of the isolation structure, and the first doping region is located outside the floating region and adjacent to the floating region; wherein the substrate region does not include the A doping region of a first conductivity type but having a different doping concentration than the matrix region. The LDMOS device for an electrostatic discharge protection circuit according to claim 1, wherein the isolation structure comprises a field oxide layer structure or a shallow trench isolation structure. As described in the scope of claim 1 for electrostatic discharge protection The LDMOS device of the circuit further includes a contact window connecting the substrate region and the second doped region located in the substrate region. The LDMOS device for an electrostatic discharge protection circuit according to claim 3, wherein the contact window is coupled to the source power source, and the first doping region is coupled to the drain power source. The LDMOS device for an electrostatic discharge protection circuit according to claim 3, wherein the contact surface of the contact window and the base region is a base contact. The LDMOS device for an electrostatic discharge protection circuit according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The LDMOS device for an electrostatic discharge protection circuit according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The LDMOS device for an electrostatic discharge protection circuit according to claim 1, further comprising: a well region having the first conductivity type, located at a periphery of the deep well region; and having one of the first conductivity types Third doped region, as a guard ring, bit In the well region, the third doped region is grounded. A lateral double-diffused metal oxide semiconductor (LDMOS) device for an electrostatic discharge protection circuit, comprising: a substrate having a first conductivity type; and a deep well region having a second conductivity type, located in the substrate; a substrate region of a conductivity type, located in the deep well region; having a first doped region of the second conductivity type, located in the deep well region; and having a second doping region of the second conductivity type a gate region located on the deep well region between the first doped region and the second doped region; a contact window connecting only the base region and the second doping in the base region a dummy region; an isolation structure between the gate and the first doped region; and a floating region having the second conductivity type, surrounding at least a portion of the isolation structure, and the first doping The miscellaneous zone is located outside of the floating zone and adjacent to the floating zone. The LDMOS device for an electrostatic discharge protection circuit according to claim 9, wherein the isolation structure comprises a field oxide layer structure or a shallow trench isolation structure. For electrostatic discharge protection as described in claim 9 An LDMOS device of the circuit, wherein the contact window is coupled to the source power source, and the first doped region is coupled to the drain power source. The LDMOS device for an electrostatic discharge protection circuit according to claim 9, wherein the contact surface of the contact window and the base region is a Schottky contact. The LDMOS device for an electrostatic discharge protection circuit according to claim 9, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The LDMOS device for an electrostatic discharge protection circuit according to claim 9, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The LDMOS device for an electrostatic discharge protection circuit according to claim 9, further comprising: a well region having the first conductivity type, located at a periphery of the deep well region; and having one of the first conductivity types The third doped region, as a guard ring, is located in the well region.