TWI686915B - Semiconductor structures - Google Patents

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate having a first doping type, a metal layer formed on the surface of the substrate, a gate formed on the substrate, a drain formed in the substrate and located at one side of the gate, the drain being adjacent to the metal layer, a source formed in the substrate and located at another side of the gate, and a first doping region having a second doping type formed in the substrate and surrounds the metal layer and the drain, wherein the second doping type is distinct from the first doping type.

Description

Semiconductor structure

The invention relates to a semiconductor structure, in particular to a semiconductor structure that can effectively improve the protection of electrostatic discharge.

Electrostatic discharge (ESD) is the main cause of most electronic components failure and damage. The generation of electrostatic discharge is difficult to avoid. For example, electronic components are extremely easy to accumulate static electricity during operation, especially for high-voltage components that are not easy to turn on (turn on), which makes electronic components vulnerable to electrostatic discharge. Destruction, such as electrostatic discharge current (ESD current), causes the transistor element to burn out. Therefore, general integrated circuits must be further equipped with appropriate ESD protection design to prevent the integrated circuits from being threatened and destroyed by electrostatic discharge.

Therefore, the development of a semiconductor structure that can effectively improve the electrostatic discharge protection is expected.

According to an embodiment of the invention, a semiconductor structure is provided. The semiconductor structure includes: a substrate having a first doping type; a metal layer formed on the surface of the substrate; a gate electrode formed on the substrate; a drain electrode formed in the substrate and located at One side of the gate is adjacent to the metal layer; a source is formed in the substrate on the other side of the gate; and a first doped region is formed in the substrate to surround the Metal layer and the drain, the first doping The region has a second doping type, and the second doping type is different from the first doping type.

According to some embodiments, the metal layer includes a metal silicide.

According to some embodiments, the source electrode and the drain electrode are N-doped, the first doped type of the substrate is P-doped, and the second doped type of the first doped region is N-doped.

According to some embodiments, the source electrode and the drain electrode are P-doped, the first doped type of the substrate is N-doped, and the second doped type of the first doped region is P-doped.

According to some embodiments, the semiconductor structure of the present invention further includes an isolation structure (isolation) formed in the first doped region on one side of the drain.

According to some embodiments, the doping concentration of the first doping region is the same as the doping concentration of the drain.

According to some embodiments, the doping concentration of the first doping region is different from the doping concentration of the drain.

According to an embodiment of the invention, a semiconductor structure is provided. The semiconductor structure includes: a substrate having a first doping type; a metal layer formed on the surface of the substrate; a first doped region formed in the substrate and adjacent to the metal layer; A second doped region is formed in the substrate relative to the first doped region; and a third doped region is formed in the substrate, surrounding the metal layer and the first doped region, the first The three doped regions have a second doped type, and the second doped type is different from the first doped type.

According to some embodiments, the first doped region and the second doped region are N-doped, the first doped type of the substrate is P-doped, and the second doped type of the third doped region N-doped.

According to some embodiments, the first doped region and the second doped region are P-doped, the first doped type of the substrate is N-doped, and the second doped type of the third doped region P-doped.

According to some embodiments, the semiconductor structure of the present invention further includes an isolation structure formed in the third doped region on one side of the first doped region.

According to some embodiments, the doping concentration of the third doping region is the same as the doping concentration of the first doping region.

According to some embodiments, the doping concentration of the third doping region is different from the doping concentration of the first doping region.

According to some embodiments, the first doped region is P doped, the second doped region is N doped, the first doped type of the substrate is P doped, and the second doped region of the third doped region The doping type is N doping.

According to some embodiments, the first doped region is N-doped, the second doped region is P-doped, the first doped type of the substrate is N-doped, and the second doped region of the third doped region The doping type is P doping.

The present invention proposes an integrated semiconductor structure combining a Schottky diode (Schottky diode) and a high-voltage MOS transistor (NMOS or PMOS). The high current characteristics of Schottky diodes are used to dissipate the electrostatic discharge current (ESD current) generated during the operation of the device, and the structure is surrounded by a doped region with a lower doping concentration and a larger doping range. Ukiji diode to reduce Schottky diode The possibility of body leakage. This integrated semiconductor structure not only retains the driving capability of high-voltage MOS transistors, but also effectively dissipates the electrostatic discharge current due to the structural and functional mutual benefits of Schottky diodes and MOS transistors. It can avoid the leakage of Schottky diode. The invention also proposes an application mode combining a Schottky diode and an NPN or PNP type double carrier junction transistor (BJT) and an application mode combining a Schottky diode and a silicon controlled rectifier (SCR).

In order to make the above objects, features and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the accompanying drawings, which are described in detail below.

10.100‧‧‧Semiconductor structure

12, 120‧‧‧ substrate

14.140‧‧‧Metal layer

16‧‧‧First gate

16’‧‧‧second gate

18‧‧‧ First Jiji

18’‧‧‧Second Jiji

20‧‧‧First source

20’‧‧‧Second source

22‧‧‧First doped area

24‧‧‧First N-type metal oxide semi-conductor (NMOS) field effect transistor

24’‧‧‧Second N-type metal oxide semi-oxide (NMOS) field effect transistor

26、260‧‧‧Schottky diode

28、280‧‧‧Isolated structure

30‧‧‧First P-type metal oxide semi-oxide (PMOS) field effect transistor

30’‧‧‧Second P-type metal oxide semi-oxide (PMOS) field effect transistor

180‧‧‧First doped area

200‧‧‧Second doped area

220‧‧‧The third doped region

240‧‧‧NPN double carrier junction transistor

250‧‧‧PNP type double carrier junction transistor

270‧‧‧Silicon controlled rectifier

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; Fig. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; Fig. 3 is an embodiment of the present invention, A schematic cross-sectional view of a semiconductor structure; Figure 4 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; Figure 5 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; Figure 6 is based on An embodiment of the present invention, a schematic cross-sectional view of a semiconductor structure; FIG. 7 is a sectional view of a semiconductor structure according to an embodiment of the present invention FIG. 8 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 9 is a cross-sectional schematic view of a semiconductor structure according to an embodiment of the present invention; FIG. 10 is an implementation according to the present invention For example, a schematic cross-sectional view of a semiconductor structure; FIG. 11 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 12 is a cross-sectional schematic view of a semiconductor structure according to an embodiment of the present invention.

Please refer to FIG. 1, according to one of the embodiments of the present invention, a semiconductor structure 10 is provided. FIG. 1 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 1, in this embodiment, the semiconductor structure 10 includes a substrate 12, a metal layer 14, a first gate 16, a first drain 18, a first source 20, a second gate 16', a first The second drain 18', the second source 20', and the first doped region 22. The doping type of the substrate 12 is P doping. The metal layer 14 is formed on the surface of the substrate 12. The first gate 16 and the second gate 16' are formed on the substrate 12. The first drain electrode 18 and the second drain electrode 18' are formed in the substrate 12, respectively located on one side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The first source electrode 20 and the second source electrode 20' are formed in the substrate 12, respectively located on the other side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The first drain 18, the second drain 18', the first source 20, And the doping type of the second source 20' is N doping. The first doped region 22 is formed in the substrate 12, surrounding the metal layer 14, the first drain 18, and the second drain 18', and the doping type of the first doped region 22 is N-doped.

In some embodiments, the substrate 12 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 14 may include metal silicide.

In some embodiments, the metal layer 14 is located on top of the first drain 18, the second drain 18', the first source 20, and the second source 20', namely the first drain 18, the second drain 18', the first source electrode 20, and the second source electrode 20' are connected to an external circuit (not shown) through the metal layer 14.

In some embodiments, the doping concentration of the first doped region 22 is the same as the doping concentration of the first drain 18 and the second drain 18'.

In some embodiments, the doping concentration of the first doping region 22 is different from the doping concentration of the first drain 18 and the second drain 18 ′. For example, the doping concentration of the first doping region 22 is low The doping concentration of the first drain 18 and the second drain 18'.

In this embodiment, the first gate electrode 16, the N-doped first drain electrode 18 and the first source electrode 20 constitute a first N-type metal oxide semiconductor (NMOS) field effect transistor 24. The second gate electrode 16', the N-doped second drain electrode 18' and the second source electrode 20' constitute a second N-type metal oxide semiconductor (NMOS) field effect transistor 24'. The metal layer 14 and the N-doped first doped region 22 constitute a Schottky diode 26. Therefore, the semiconductor structure 10 includes both NMOS field effect transistors (24, 24') and Schottky diodes 26.

Please refer to FIG. 2, according to one of the embodiments of the present invention, a semiconductor structure 10 is provided. FIG. 2 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 2, in this embodiment, the semiconductor structure 10 includes a substrate 12, a metal layer 14, a first gate 16, a first drain 18, a first source 20, a second gate 16', a first The second drain 18', the second source 20', the first doped region 22, and the isolation structure 28. The doping type of the substrate 12 is P doping. The metal layer 14 is formed on the surface of the substrate 12. The first gate 16 and the second gate 16' are formed on the substrate 12. The first drain electrode 18 and the second drain electrode 18' are formed in the substrate 12, respectively located on one side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The first source electrode 20 and the second source electrode 20' are formed in the substrate 12, respectively located on the other side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The doping types of the first drain 18, the second drain 18', the first source 20, and the second source 20' are N-doped. The first doped region 22 is formed in the substrate 12, surrounding the metal layer 14, the first drain 18, and the second drain 18', and the doping type of the first doped region 22 is N-doped. The isolation structure 28 is formed in the first doped region 22 on one side of the first drain 18 and the second drain 18'.

In some embodiments, the substrate 12 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 14 may include metal silicide.

In some embodiments, the metal layer 14 is located on top of the first drain 18, the second drain 18', the first source 20, and the second source 20', namely the first drain 18, the second drain 18', the first source 20, and the second source 20' by metal The layer 14 is connected to an external circuit (not shown).

In some embodiments, the doping concentration of the first doped region 22 is the same as the doping concentration of the first drain 18 and the second drain 18'.

In some embodiments, the doping concentration of the first doping region 22 is different from the doping concentration of the first drain 18 and the second drain 18 ′. For example, the doping concentration of the first doping region 22 is low The doping concentration of the first drain 18 and the second drain 18'.

In some embodiments, the isolation structure 28 may include any suitable insulating material.

In some embodiments, the isolation structure 28 extends downward beyond the first drain 18 and the second drain 18'.

In this embodiment, the first gate electrode 16, the N-doped first drain electrode 18 and the first source electrode 20 constitute a first N-type metal oxide semiconductor (NMOS) field effect transistor 24. The second gate electrode 16', the N-doped second drain electrode 18' and the second source electrode 20' constitute a second N-type metal oxide semiconductor (NMOS) field effect transistor 24'. The metal layer 14 and the N-doped first doped region 22 constitute a Schottky diode 26. Therefore, the semiconductor structure 10 includes both NMOS field effect transistors (24, 24') and Schottky diodes 26.

Referring to FIG. 3, according to one of the embodiments of the present invention, a semiconductor structure 10 is provided. FIG. 3 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 3, in this embodiment, the semiconductor structure 10 includes a substrate 12, a metal layer 14, a first gate 16, a first drain 18, a first source 20, a second gate 16', a first The second drain 18', the second source 20', and the first doped region 22. The doping type of the substrate 12 is N doping. The metal layer 14 is formed on the surface of the substrate 12. The first gate 16 and the second gate 16' are formed on the substrate 12. The first drain electrode 18 and the second drain electrode 18' are formed in the substrate 12, respectively located on one side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The first source electrode 20 and the second source electrode 20' are formed in the substrate 12, respectively located on the other side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The doping types of the first drain 18, the second drain 18', the first source 20, and the second source 20' are P-doped. The first doped region 22 is formed in the substrate 12, surrounding the metal layer 14, the first drain 18, and the second drain 18', and the doping type of the first doped region 22 is P-doped.

In some embodiments, the substrate 12 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 14 may include metal silicide.

In some embodiments, the metal layer 14 is located on top of the first drain 18, the second drain 18', the first source 20, and the second source 20', namely the first drain 18, the second drain 18', the first source electrode 20, and the second source electrode 20' are connected to an external circuit (not shown) through the metal layer 14.

In some embodiments, the doping concentration of the first doped region 22 is the same as the doping concentration of the first drain 18 and the second drain 18'.

In some embodiments, the doping concentration of the first doping region 22 is different from the doping concentration of the first drain 18 and the second drain 18 ′. For example, the doping concentration of the first doping region 22 is low The doping concentration of the first drain 18 and the second drain 18'.

In this embodiment, the first gate 16 and the P-doped first drain 18 And the first source electrode 20 constitutes a first P-type metal oxide semiconductor (PMOS) field effect transistor 30. The second gate electrode 16', the P-doped second drain electrode 18' and the second source electrode 20' constitute a second P-type metal oxide semiconductor (PMOS) field effect transistor 30'. The metal layer 14 and the P-doped first doped region 22 constitute a Schottky diode 26. Therefore, the semiconductor structure 10 includes both PMOS field effect transistors (30, 30') and Schottky diode 26.

Referring to FIG. 4, according to one of the embodiments of the present invention, a semiconductor structure 10 is provided. FIG. 4 is a schematic cross-sectional view of the semiconductor structure 10.

As shown in FIG. 4, in this embodiment, the semiconductor structure 10 includes a substrate 12, a metal layer 14, a first gate 16, a first drain 18, a first source 20, a second gate 16', a first The second drain 18', the second source 20', the first doped region 22, and the isolation structure 28. The doping type of the substrate 12 is N doping. The metal layer 14 is formed on the surface of the substrate 12. The first gate 16 and the second gate 16' are formed on the substrate 12. The first drain electrode 18 and the second drain electrode 18' are formed in the substrate 12, respectively located on one side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The first source electrode 20 and the second source electrode 20' are formed in the substrate 12, respectively located on the other side of the first gate electrode 16 and the second gate electrode 16', and adjacent to the metal layer 14. The doping types of the first drain 18, the second drain 18', the first source 20, and the second source 20' are P-doped. The first doped region 22 is formed in the substrate 12, surrounding the metal layer 14, the first drain 18, and the second drain 18', and the doping type of the first doped region 22 is P-doped. The isolation structure 28 is formed in the first doped region 22 on one side of the first drain 18 and the second drain 18'.

In some embodiments, the substrate 12 may include a silicon substrate or other suitable Substrate material.

In some embodiments, the metal layer 14 may include metal silicide.

In some embodiments, the metal layer 14 is located on top of the first drain 18, the second drain 18', the first source 20, and the second source 20', namely the first drain 18, the second drain 18', the first source electrode 20, and the second source electrode 20' are connected to an external circuit (not shown) through the metal layer 14.

In some embodiments, the doping concentration of the first doped region 22 is the same as the doping concentration of the first drain 18 and the second drain 18'.

In some embodiments, the doping concentration of the first doping region 22 is different from the doping concentration of the first drain 18 and the second drain 18 ′. For example, the doping concentration of the first doping region 22 is low The doping concentration of the first drain 18 and the second drain 18'.

In some embodiments, the isolation structure 28 may include any suitable insulating material.

In some embodiments, the isolation structure 28 extends downward beyond the first drain 18 and the second drain 18'.

In this embodiment, the first gate 16, the P-doped first drain 18 and the first source 20 constitute a first P-type metal oxide semiconductor (PMOS) field effect transistor 30. The second gate electrode 16', the P-doped second drain electrode 18' and the second source electrode 20' constitute a second P-type metal oxide semiconductor (PMOS) field effect transistor 30'. The metal layer 14 and the P-doped first doped region 22 constitute a Schottky diode 26. Therefore, the semiconductor structure 10 includes both PMOS field effect transistors (30, 30') and Schottky diode 26.

Please refer to FIG. 5, according to one of the embodiments of the present invention, a semiconductor structure 100 is provided. FIG. 5 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 5, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, and a third doped region 220. The doping type of the substrate 120 is P doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed in the substrate 120 and is adjacent to the metal layer 140. The second doped region 200 is formed in the substrate 120, opposite to the first doped region 180, and is adjacent to the metal layer 140. The doping types of the first doped region 180 and the second doped region 200 are N-doped. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is N-doped.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located on top of the first doped region 180 and the second doped region 200, that is, the first doped region 180 and the second doped region 200 pass through the metal layer 140 and the external circuit (not (Illustration) Connect.

In some embodiments, the doping concentration of the third doping region 220 is the same as the doping concentration of the first doping region 180.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In this embodiment, the N-doped first doped region 180, the N-doped third doped region 220, the P-doped substrate 120, and the N-doped second doped region 200 constitute an NPN double A carrier junction bipolar junction transistor (BJT) 240. The metal layer 140 and the N-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the NPN double carrier junction transistor 240 and the Schottky diode 260.

Referring to FIG. 6, according to one of the embodiments of the present invention, a semiconductor structure 100 is provided. FIG. 6 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 6, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, a third doped region 220, and Isolated structure 280. The doping type of the substrate 120 is P doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed in the substrate 120 and is adjacent to the metal layer 140. The second doped region 200 is formed in the substrate 120, opposite to the first doped region 180, and is adjacent to the metal layer 140. The doping types of the first doped region 180 and the second doped region 200 are N-doped. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is N-doped. The isolation structure 280 is formed in the third doped region 220 on one side of the first doped region 180.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located in the first doped region 180 The top of the second doped region 200, that is, the first doped region 180 and the second doped region 200 are connected to an external circuit (not shown) through the metal layer 140.

In some embodiments, the doping concentration of the third doping region 220 is the same as the doping concentration of the first doping region 180.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In some embodiments, the isolation structure 280 may include any suitable insulating material.

In some embodiments, the isolation structure 280 extends downward beyond the first doped region 180.

In this embodiment, the N-doped first doped region 180, the N-doped third doped region 220, the P-doped substrate 120, and the N-doped second doped region 200 constitute an NPN double A carrier junction bipolar junction transistor (BJT) 240. The metal layer 140 and the N-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the NPN double carrier junction transistor 240 and the Schottky diode 260.

Please refer to FIG. 7, according to one of the embodiments of the present invention, a semiconductor structure 100 is provided. FIG. 7 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 7, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, and a third doped region 220. The doping type of the substrate 120 is N doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed on the substrate 120 And adjacent to the metal layer 140. The second doped region 200 is formed in the substrate 120, opposite to the first doped region 180, and is adjacent to the metal layer 140. The doping type of the first doped region 180 and the second doped region 200 is P doping. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is P-doped.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located on top of the first doped region 180 and the second doped region 200, that is, the first doped region 180 and the second doped region 200 pass through the metal layer 140 and the external circuit (not (Illustration) Connect.

In some embodiments, the doping concentration of the third doping region 220 is the same as the doping concentration of the first doping region 180.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In this embodiment, the P-doped first doped region 180, the P-doped third doped region 220, the N-doped substrate 120, and the P-doped second doped region 200 constitute a PNP type dual Carrier junction bipolar junction transistor (BJT) 250. The metal layer 140 and the P-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the PNP type double carrier junction transistor 250 and the Schottky diode 260.

Please refer to FIG. 8, according to one of the embodiments of the present invention First, a semiconductor structure 100 is provided. FIG. 8 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 8, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, a third doped region 220, and Isolated structure 280. The doping type of the substrate 120 is N doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed in the substrate 120 and is adjacent to the metal layer 140. The second doped region 200 is formed in the substrate 120, opposite to the first doped region 180, and is adjacent to the metal layer 140. The doping type of the first doped region 180 and the second doped region 200 is P doping. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is P-doped. The isolation structure 280 is formed in the third doped region 220 on one side of the first doped region 180.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located on top of the first doped region 180 and the second doped region 200, that is, the first doped region 180 and the second doped region 200 pass through the metal layer 140 and the external circuit (not (Illustration) Connect.

In some embodiments, the doping concentration of the third doping region 220 is the same as the doping concentration of the first doping region 180.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In some embodiments, the isolation structure 280 may include any suitable insulating material.

In some embodiments, the isolation structure 280 extends downward beyond the first doped region 180.

In this embodiment, the P-doped first doped region 180, the P-doped third doped region 220, the N-doped substrate 120, and the P-doped second doped region 200 constitute a PNP type dual Carrier junction bipolar junction transistor (BJT) 250. The metal layer 140 and the P-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the PNP type double carrier junction transistor 250 and the Schottky diode 260.

Please refer to FIG. 9, according to one of the embodiments of the present invention, a semiconductor structure 100 is provided. FIG. 9 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 9, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, and a third doped region 220. The doping type of the substrate 120 is P doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed in the substrate 120 and is adjacent to the metal layer 140. The second doped region 200 is formed in the substrate 120, opposite to the first doped region 180, and is adjacent to the metal layer 140. The doping type of the first doping region 180 is P doping, and the doping type of the second doping region 200 is N doping. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is N-doped.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located on top of the first doped region 180 and the second doped region 200, that is, the first doped region 180 and the second doped region 200 pass through the metal layer 140 and the external circuit (not (Illustration) Connect.

In some embodiments, the doping concentration of the third doping region 220 is the same as the doping concentration of the first doping region 180.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In this embodiment, the P-doped first doped region 180, the N-doped third doped region 220, the P-doped substrate 120, and the N-doped second doped region 200 constitute a silicon controlled rectifier (silicon controlled rectifier, SCR) 270. The metal layer 140 and the N-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the silicon controlled rectifier 270 and the Schottky diode 260.

Referring to FIG. 10, according to one of the embodiments of the present invention, a semiconductor structure 100 is provided. FIG. 10 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 10, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, a third doped region 220, and Isolated structure 280. The doping type of the substrate 120 is P doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed in the substrate 120 and is adjacent to the metal layer 140. The second doped region 200 is formed In the substrate 120, relative to the first doped region 180, and adjacent to the metal layer 140. The doping type of the first doping region 180 is P doping, and the doping type of the second doping region 200 is N doping. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is N-doped. The isolation structure 280 is formed in the third doped region 220 on one side of the first doped region 180.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located on top of the first doped region 180 and the second doped region 200, that is, the first doped region 180 and the second doped region 200 pass through the metal layer 140 and the external circuit (not (Illustration) Connect.

In some embodiments, the doping concentration of the third doping region 220 is the same as the doping concentration of the first doping region 180.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In some embodiments, the isolation structure 280 may include any suitable insulating material.

In some embodiments, the isolation structure 280 extends downward beyond the first doped region 180.

In this embodiment, the P-doped first doped region 180, the N-doped third doped region 220, the P-doped substrate 120, and the N-doped second doped region 200 A silicon controlled rectifier (SCR) 270 is formed. The metal layer 140 and the N-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the silicon controlled rectifier 270 and the Schottky diode 260.

Please refer to FIG. 11, according to one of the embodiments of the present invention, a semiconductor structure 100 is provided. FIG. 11 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 11, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, and a third doped region 220. The doping type of the substrate 120 is N doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed in the substrate 120 and is adjacent to the metal layer 140. The second doped region 200 is formed in the substrate 120, opposite to the first doped region 180, and is adjacent to the metal layer 140. The doping type of the first doping region 180 is N doping, and the doping type of the second doping region 200 is P doping. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is P-doped.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located on top of the first doped region 180 and the second doped region 200, that is, the first doped region 180 and the second doped region 200 pass through the metal layer 140 and the external circuit (not (Illustration) Connect.

In some embodiments, the doping concentration of the third doped region 220 is The doping concentration of a doped region 180 is the same.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In this embodiment, the N-doped first doped region 180, the P-doped third doped region 220, the N-doped substrate 120, and the P-doped second doped region 200 constitute a silicon controlled rectifier (silicon controlled rectifier, SCR) 270. The metal layer 140 and the N-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the silicon controlled rectifier 270 and the Schottky diode 260.

Referring to FIG. 12, according to one of the embodiments of the present invention, a semiconductor structure 100 is provided. FIG. 12 is a schematic cross-sectional view of the semiconductor structure 100.

As shown in FIG. 12, in this embodiment, the semiconductor structure 100 includes a substrate 120, a metal layer 140, a plurality of first doped regions 180, a plurality of second doped regions 200, a third doped region 220, and Isolated structure 280. The doping type of the substrate 120 is N doping. The metal layer 140 is formed on the surface of the substrate 120. The first doped region 180 is formed in the substrate 120 and is adjacent to the metal layer 140. The second doped region 200 is formed in the substrate 120, opposite to the first doped region 180, and is adjacent to the metal layer 140. The doping type of the first doping region 180 is N doping, and the doping type of the second doping region 200 is P doping. The third doped region 220 is formed in the substrate 120 and surrounds the metal layer 140 and the first doped region 180, and the doping type of the third doped region 220 is P-doped. The isolation structure 280 is formed in the third doped region 220 on one side of the first doped region 180.

In some embodiments, the substrate 120 may include a silicon substrate or other suitable substrate materials.

In some embodiments, the metal layer 140 may include metal silicide.

In some embodiments, the metal layer 140 is located on top of the first doped region 180 and the second doped region 200, that is, the first doped region 180 and the second doped region 200 pass through the metal layer 140 and the external circuit (not (Illustration) Connect.

In some embodiments, the doping concentration of the third doping region 220 is the same as the doping concentration of the first doping region 180.

In some embodiments, the doping concentration of the third doping region 220 is different from that of the first doping region 180. For example, the doping concentration of the third doping region 220 is lower than that of the first doping region 180 doping concentration.

In some embodiments, the isolation structure 280 may include any suitable insulating material.

In some embodiments, the isolation structure 280 extends downward beyond the first doped region 180.

In this embodiment, the N-doped first doped region 180, the P-doped third doped region 220, the N-doped substrate 120, and the P-doped second doped region 200 constitute a silicon controlled rectifier (silicon controlled rectifier, SCR) 270. The metal layer 140 and the N-doped third doped region 220 constitute a Schottky diode 260. Therefore, the semiconductor structure 100 includes both the silicon controlled rectifier 270 and the Schottky diode 260.

The present invention proposes an integrated semiconductor structure combining a Schottky diode (Schottky diode) and a high-voltage MOS transistor (NMOS or PMOS). use The high current characteristics of Schottky diodes dissipate the electrostatic discharge current (ESD current) generated during the operation of the device, and the structure is surrounded by a doped region with a lower doping concentration and a larger doping range. Base diode to reduce the possibility of Schottky diode leakage. This integrated semiconductor structure not only retains the driving capability of high-voltage MOS transistors, but also effectively dissipates the electrostatic discharge current due to the structural and functional mutual benefits of Schottky diodes and MOS transistors. It can avoid the leakage of Schottky diode. The invention also proposes an application mode combining a Schottky diode and an NPN or PNP type double carrier junction transistor (BJT) and an application mode combining a Schottky diode and a silicon controlled rectifier (SCR).

Although the present invention has been disclosed in several preferred embodiments as above, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make any changes without departing from the spirit and scope of the present invention. And retouching, therefore, the scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10‧‧‧Semiconductor structure

12‧‧‧ substrate

14‧‧‧Metal layer

16‧‧‧First gate

16’‧‧‧second gate

18‧‧‧ First Jiji

18’‧‧‧Second Jiji

20‧‧‧First source

20’‧‧‧Second source

22‧‧‧First doped area

24‧‧‧First N-type metal oxide semi-conductor (NMOS) field effect transistor

24’‧‧‧Second N-type metal oxide semi-oxide (NMOS) field effect transistor

26‧‧‧Schottky diode

Claims (32)

A semiconductor structure includes: a substrate having a first doping type; a metal layer formed in the substrate and coplanar with the substrate; a plurality of gates formed on the substrate and located in the metal layer Two sides of the gate; a plurality of drains formed in the substrate, respectively located on one side of the gates, the drains are adjacent to each other and adjacent to the metal layer; a plurality of sources are formed on the substrate , Located on the other side of the gates; and a first doped region, formed in the substrate, surrounding the metal layer and the adjacent drains, the first doped region has a second doped Heterotype, and the second doping type is different from the first doping type, the doping concentration of the first doping region is lower than the doping concentration of the surrounding drains. The semiconductor structure as described in item 1 of the patent application scope, wherein the metal layer includes a metal silicide. The semiconductor structure as described in item 1 of the patent application scope, wherein the source electrode and the drain electrode are N-doped. The semiconductor structure as described in item 3 of the patent application range, wherein the first doping type is P doping. The semiconductor structure as described in item 4 of the patent application range, wherein the second doping type is N-doping. The semiconductor structure as described in item 5 of the patent application scope further includes an isolation structure formed in the first doped region on one side of the drain. The semiconductor structure as described in item 1 of the patent application scope, in which the source and the The drain is P-doped. The semiconductor structure as described in item 7 of the patent application range, wherein the first doping type is N-doping. The semiconductor structure as described in item 8 of the patent application range, wherein the second doping type is P doping. The semiconductor structure described in item 9 of the patent application scope further includes an isolation structure formed in the first doped region on one side of the drain. The semiconductor structure as described in item 1 of the patent application range, wherein the doping concentration of the first doped region is the same as the doping concentration of the drain. The semiconductor structure as described in item 1 of the patent application range, wherein the doping concentration of the first doped region is different from the doping concentration of the drain. A semiconductor structure includes: a substrate having a first doping type; a metal layer formed in the substrate and coplanar with the substrate; a plurality of first doped regions formed in the substrate, the The first doped regions are adjacent to each other and adjacent to the metal layer; a plurality of second doped regions are formed in the substrate opposite to the first doped regions; and a third doped region, Formed in the substrate, surrounding the metal layer and the adjacent first doped regions, the third doped region has a second doped type, and the second doped type and the first doped Different types, the doping concentration of the third doping region is lower than the doping concentration of the surrounding first doping regions. The semiconductor structure as described in item 13 of the patent application range, wherein the metal layer includes a metal silicide. The semiconductor structure as recited in item 13 of the patent application range, wherein the first doped region and the second doped region are N-doped. The semiconductor structure as described in item 15 of the patent application range, wherein the first doping type is P doping. The semiconductor structure as recited in item 16 of the patent application range, wherein the second doping type is N-doping. The semiconductor structure as described in item 17 of the patent application scope further includes an isolation structure formed in the third doped region on one side of the first doped region. The semiconductor structure as recited in item 13 of the patent application range, wherein the first doped region and the second doped region are P-doped. The semiconductor structure as described in item 19 of the patent application range, wherein the first doping type is N-doping. The semiconductor structure as described in item 20 of the patent application range, wherein the second doping type is P doping. The semiconductor structure as described in Item 21 of the patent application scope further includes an isolation structure formed in the third doped region on one side of the first doped region. The semiconductor structure as recited in item 13 of the patent application range, wherein the doping concentration of the third doping region is the same as the doping concentration of the first doping region. The semiconductor structure as recited in item 13 of the patent application range, wherein the doping concentration of the third doping region is different from the doping concentration of the first doping region. The semiconductor structure as recited in item 13 of the patent application range, wherein the first doped region is P-doped and the second doped region is N-doped. The semiconductor structure as described in item 25 of the patent application range, wherein the first doping type is P doping. The semiconductor structure as described in item 26 of the patent application range, wherein the second doping type is N-doping. The semiconductor structure as described in item 27 of the patent application scope further includes an isolation structure formed in the third doped region on one side of the first doped region. The semiconductor structure as recited in item 13 of the patent application range, wherein the first doped region is N-doped and the second doped region is P-doped. The semiconductor structure as described in item 29 of the patent application range, wherein the first doping type is N-doping. The semiconductor structure as recited in item 30 of the patent application range, wherein the second doping type is P doping. The semiconductor structure as described in item 31 of the patent application scope further includes an isolation structure formed in the third doped region on one side of the first doped region.

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