1360874 UMCD-2008-0051 27920twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件’且特別是有關於一 種用於靜電保護放電保護電路之橫向擴散金氧半導體 (lateral double diffused metal oxide semiconductor； LDMOS) 元件。 【先前技術】 靜電放電(Electrostatic Discharge ; ESD)是造成大多數 的電子元件或電子系統受到過度電性應力（Electrical Overstress ; EOS)破壞的主要因素。這種破壞會導致半導體 元件以及電腦系統永久性的毀壞，因而影響積體電路 (Integrated Circuits ; ICs)的電路功能，使得電子產品工作 不正常。 在深次微米半導體製程中，由於元件尺寸微縮，元件 的靜電放電(Electrostatic Discharge ; ESD)耐受度相對變 差’因此，靜電放電防護設計在1C設計時即必需加以考 量。通常商用1C的靜電放電耐受度必需通過人體放電模 式(Human Body Model ; HBM) 2 kV與機器放電模式 (Machine Model ; MM) 200 V 的測試。 為了能夠承受如此高電壓的靜電放電測試，IC上的 靜電放電防護元件常具有大元件尺寸的設計。為了盡可能 節省晶粒面積’在佈局(layout)上，這種大尺寸的元件通常 以指狀(multi-finger)的方式來實現。 然而’對於目前廣泛使用於電源管理的LDM〇s元件來 5 1360874 UMCD-2008-0051 27920twf.doc/n 說’指狀的LDMOS元件目前仍無法通過人體放電模式 (HBM)2kV與機器放電模式(MM) 200V的測試，因此， 亟需一種具有足夠之靜電放電耐受度的LDMOS元件來作 為靜電放電保護電路之元件。 【發明内容】 本發明提供一種用於靜電放電保護電路之LDMOS元 件’其具有較高的靜電放電耐受度。 鲁本發明提出一種靜電放電保護電路元件，其包括至少 一個橫向擴散金氧半導體（LDMOS)元件。LDMOS元件 包括具有第-導電型之基底、具有第二導電型之深井區。 • 基底，括第一區域與第二區域。深井區位於基底的第一區 • 域與第二區域之内。LDMOS元件還包括閘極、具有第一 導電型的植入區、具有第二導電型之階區、具有第二導電 型之第一摻雜區、具有第一導電型之基體區、具有第二導 電f之第二摻雜區以及具有第一導電型之摻雜區。閘極位 於ί一1f域區與第二區域之間的基底上。植入區位於基底 • 之第一區域内。階區位於第一區域的深井區中。第一摻雜 區位於卩0區中。基體區位於第二區域的深井區中。第二掺 雜區位於基體區中。摻雜區位於基體區中，且二捧雜 區相鄰。 ^布一少， 1雷nr月之一實施例所述’上述之用於靜電放電保 η述植入區位於第—摻雜區與階區之間。 護電路狀—實施例所述，上述之崎靜電放電保 4電路兀㈣，上述植入區位於第—換雜區下方。 6 1360874 UMCD-2008-0051 27920twf.doc/n 依知'本發明之一實施例所述，上述之用於靜電放電保 護電路元件中，上述植入區位於階區之中。 依照本發明之一實施例所述，上述之用於靜電放電保 濩電路元件中，上述植入區位於階區與深井區之間。 ^ 依照本發明之一實施例所述，上述之用於靜電放電保 護電路元件中’上述植入區位於深井區之中^ ” 依照本發明之一實施例所述，上述之用於靜電放電保 護電路元件中，上述第一導電型為p型，上述第二 刑 為型。 生 依照本發明之一實施例所述，上述之用於靜電放電保 護電路元件中，上述第一導電型為]^型，上述 刑 為P型。 电1 依照本發明之一實施例所述，上述之用於靜電放電保 護電路元件更包括一第二導電型淡摻雜區，位於閘極與第 二摻雜區之間的基體區中。 ^ 依照本發明之一實施例所述，上述之用於靜 護電路元件更包括··具有第-導電型之井區，位於深^ 的外圍；以及防護環’位於井區中。 依照本發明之一實施例所述，上述之用於靜電放電保 護電路元件更包括隔離綽構，位於防護環與第二摻雜區^ 間。 依照本發明之一實施例所述，上述之用於靜電放電保 Ϊ二件_，上述隔離結構包括場氧化層結構或淺溝渠 7 UMCD-2008-0051 27920twf.d〇〇/n 依照本發明之一實施例所述，上述之用於靜電玫 痩電路元件包括數個上述之LDMOS元件。 ^依照本發明之—實施例所述，上述之用於靜電放電保 護電路元件中，上述那些LDM〇s元件之數個閘極彼此連 接。 〇依照本發明之—實施例所述，上述之用於靜電放電保 兀件中，上述那些LDMOS元件之數個閘極連接呈 本發明之用於靜電放電保護電路iLDM〇s元件，1 做=為祕之摻_下方形成植人區確實可以達到提耐 受度之目的。 為讓本發明之上述特徵和優點能更明顯易懂，下 舉較佳實_，她合所關式，作詳細說明。 【實施方式】 本發明之用於靜電放電保護電路之LDM〇s元 以=NM0S元件或LDPM〇s元件。以下，是以⑽臓 Γ ΐ說:其中以P型來表示第—導電型，而以N型來 ΐί=Γ7以將第一導電型置換❹、型，= 導電型置換成Ρ型以形成LDPM〇s元件。 以下，將以兩個LDNM0S元件所構成之靜電放電保 遽電路it件為例綠詳細綱，但並_ 、 本發明並不對LDMOS元件的數量做特別的限=林 圖1為依照本發明之一實施例所綠示的用於靜電放電 1360874 UMCD-2008-0051 27920twf.doc/n 保護^路之LDNMOS元件的剖面示意圖。 請參考圖靜電放電保護電路元件包括LDNMOS元 件10、20包括p型基底ι〇〇與n型深井區1〇2。p型基 底分為第一區域140、第二區域150a與第二區域 150b。第一區域14〇在第二區域15〇a與第二區域15%之 間。N型深井區1〇2位於基底1〇()的第一區域14〇、第二1360874 UMCD-2008-0051 27920twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element and, in particular, to a lateral diffusion of gold oxide for an electrostatic protection discharge protection circuit A lateral double diffused metal oxide semiconductor (LDMOS) device. [Prior Art] Electrostatic discharge (ESD) is a major factor that causes most electronic components or electronic systems to be damaged by Electrical Overstress (EOS). This damage can lead to permanent destruction of semiconductor components and computer systems, thus affecting the circuit functions of integrated circuits (ICs), making electronic products work abnormally. In the deep sub-micron semiconductor process, the electrostatic discharge (ESD) tolerance of the component is relatively poor due to the small size of the component. Therefore, the electrostatic discharge protection design must be considered in the 1C design. Generally, the electrostatic discharge tolerance of commercial 1C must be tested by Human Body Model (HBM) 2 kV and Machine Discharge Mode (MM) 200 V. In order to withstand such high voltage ESD tests, ESD protection components on ICs often have large component sizes. In order to save as much as possible the grain area 'on the layout, such large-sized components are usually implemented in a multi-finger manner. However, for the LDM〇s components currently widely used in power management, 5 1360874 UMCD-2008-0051 27920twf.doc/n says that the finger-shaped LDMOS components are still unable to pass the human discharge mode (HBM) 2kV and the machine discharge mode ( MM) 200V test, therefore, there is a need for an LDMOS device with sufficient electrostatic discharge tolerance as an element of the ESD protection circuit. SUMMARY OF THE INVENTION The present invention provides an LDMOS device for an electrostatic discharge protection circuit which has a high electrostatic discharge tolerance. The Ruben invention proposes an electrostatic discharge protection circuit component comprising at least one laterally diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes a substrate having a first conductivity type and a deep well region having a second conductivity type. • Base, including the first area and the second area. The deep well zone is located in the first zone of the basement area and within the second zone. The LDMOS device further includes a gate, an implant region having a first conductivity type, a step region having a second conductivity type, a first doped region having a second conductivity type, a base region having a first conductivity type, and having a second a second doped region of conductive f and a doped region having a first conductivity type. The gate is located on the substrate between the ί1f domain and the second region. The implanted area is located in the first area of the substrate. The step zone is located in the deep well zone of the first zone. The first doped region is located in the 卩0 region. The base zone is located in the deep well zone of the second zone. The second doped region is located in the matrix region. The doped regions are located in the base region and the two holding regions are adjacent. ^布一少, 1 雷nr month one embodiment described above] for the electrostatic discharge protection described above, the implantation region is located between the first doped region and the step region. In the case of the circuit, as described in the embodiment, the above-mentioned SSD electrostatic discharge protection circuit 4 (4), the implantation region is located below the first impurity-changing region. 6 1360874 UMCD-2008-0051 27920 twf.doc/n According to one embodiment of the present invention, in the above-described electrostatic discharge protection circuit component, the implanted region is located in a step region. According to an embodiment of the invention, in the above electrostatic discharge protection circuit component, the implanted region is located between the stepped region and the deep well region. According to an embodiment of the present invention, the above-mentioned implanted region is located in the deep well region in the above-mentioned electrostatic discharge protection circuit component. According to an embodiment of the present invention, the above is used for electrostatic discharge protection. In the circuit component, the first conductivity type is a p-type, and the second penalty type is as described above. According to an embodiment of the invention, the first conductivity type is used in the electrostatic discharge protection circuit component. The above-mentioned penalty is P-type. Electric 1 According to an embodiment of the invention, the above-mentioned electrostatic discharge protection circuit component further comprises a second conductivity type lightly doped region, which is located at the gate and the second doping region. Between the base regions. ^ In accordance with an embodiment of the present invention, the above-described static circuit component further includes a well region having a first conductivity type, located at a periphery of the deep ^; and the guard ring 'located In the well region, in accordance with an embodiment of the invention, the electrostatic discharge protection circuit component further includes an isolation structure disposed between the guard ring and the second doped region. , the above In the case of electrostatic discharge protection, the above isolation structure comprises a field oxide layer structure or a shallow trench 7 UMCD-2008-0051 27920twf.d〇〇/n according to an embodiment of the invention, the above is used for electrostatic discharge The circuit component comprises a plurality of the above-mentioned LDMOS components. According to the embodiment of the invention, in the above-mentioned electrostatic discharge protection circuit component, the plurality of gates of the LDM 〇 s components are connected to each other. In the above embodiments, in the above-mentioned electrostatic discharge protection device, a plurality of gate connections of the above LDMOS devices are used in the present invention for the electrostatic discharge protection circuit iLDM〇s element, 1 The formation of the implanted area below can indeed achieve the purpose of tolerating. In order to make the above features and advantages of the present invention more obvious and easy to understand, the following is a better example, and she will be described in detail. MODE] The LDM 〇s element of the present invention for an electrostatic discharge protection circuit is an NMOS element or an LDPM 〇 s element. Hereinafter, it is (10) 臓Γ :: wherein the P-type indicates the first conductivity type, and Type to ΐί=Γ7 to be the first guide Type substitution ❹, type, = conductivity type is replaced by Ρ type to form LDPM 〇 s element. Hereinafter, an electrostatic discharge protection circuit element composed of two LDN MOS elements is taken as an example, but the present invention There is no particular limitation on the number of LDMOS components. FIG. 1 is a schematic cross-sectional view of an LDNMOS device for electrostatic discharge 1360874 UMCD-2008-0051 27920 twf.doc/n protection circuit according to an embodiment of the present invention. Please refer to the figure. The electrostatic discharge protection circuit component includes LDNMOS components 10, 20 including a p-type substrate ι and an n-type deep well region 1-2. The p-type substrate is divided into a first region 140, a second region 150a and a second region 150b. . The first region 14 is between the second region 15a and the second region 15%. N-type deep well area 1〇2 is located in the first area of the base 1〇() 14〇, second
區域150a與第二區域i5〇b之中。在一實施例中，形成N 型深井區1〇2的能量例如是1600〜2000 KeV ;劑量例如是 1011 〜3xl012/cm2。 用於靜電放電保護電路之LDNMOS元件1〇還包括閘 極 110a、N 型第一摻雜區 ι〇6、Ν 型階區(gmderegi〇n)13〇、 兩個N型第二摻雜區i〇8a、p型摻雜區134a及p型基體 區104a。LDNMOS元件20還包括閘極n〇b、N型第一摻 雜區106、N型階區130、兩個N型第二摻雜區1〇8b、p 型摻雜區134b及P型基體區1〇4b。 N型心區130，其位於第一區域“ο内的深井區1〇2 • 中。在一實施例中，形成N型階區130的能量例如是5〇〜15〇The area 150a is in the second area i5〇b. In one embodiment, the energy for forming the N-type deep well region 1 〇 2 is, for example, 1600 to 2000 KeV; and the dose is, for example, 1011 to 3xl012/cm2. The LDNMOS device 1 for the ESD protection circuit further includes a gate 110a, an N-type first doped region ι6, a Ν-type step region, and two N-type second doping regions i 〇8a, p-type doped region 134a and p-type base region 104a. The LDNMOS device 20 further includes a gate n〇b, an N-type first doped region 106, an N-type terrace 130, two N-type second doped regions 1〇8b, a p-type doped region 134b, and a P-type base region. 1〇4b. The N-type core region 130 is located in the deep well region 1〇2 of the first region “o. In an embodiment, the energy for forming the N-type terrace region 130 is, for example, 5〇~15〇
KeV ;劑量例如是 ίο11 〜5xi〇12/cm2。 N型第一摻雜區106例如為N+摻雜區，其位於同導電 型的階區130中，作為用於靜電放電保護電路之ldnm〇s 元件10、20的共同汲極區，藉由接觸窗與銲墊電性連接。 在一實施例令，形成N型第一摻雜區1〇6的能量例如是 60〜100 KeV ;劑量例如是 1〇14〜2xi〇i5/cm2。 P型基體區104a、104b分別位於第二區域15〇&、i5〇b 1360874 UMCD-2008-0051 27920twf.doc/n 内的N型深井區102中。在一實施例中，形成p型基體區 104a、104b的能量例如是160〜200KeV;劑量例如是1〇12〜4 xlO13/cm2。 N型第二摻雜區108a、l〇8b例如為N+摻雜區’分別 位於基體區104a、104b巾，作為用於靜電放電保護電路之 LDNMOS元件10、20的源極區。在一實施例中，形成N 型第一掺雜區l〇8a、i〇8b的能量例如是6〇〜1〇〇 KeV ;劑 量例如是1014〜2xl015/cm2。 P型摻雜區134a、134b例如為P+摻雜區，其分別位 於P型基體區104a、腿中，且夾於兩個N型第二換雜 區l〇8a以及兩個N型第二摻雜區1〇扑之間。在一實施例 中’形成P型摻雜區134a、134b的能量例如是35〜75就 劍里例如是1〇14〜3χ1〇15/^η2〇ρ型摻雜區134a、13仙分別 與N型第一摻雜區108a、1〇8b透過接觸窗與源 接。 ”閘極110a位於第一區域140與第二區域15〇a之間的 /米井區102上’並且延伸至第一區域ι4〇内的N型階區 上方且延伸至第二區域15〇&内的部分的p型基體區1⑽a 上方。閘極ii〇b位於第一區域140與第二區域15〇b之間 的深井區102上，並且延伸至第一區域14〇内的N型階區 130上方’且延伸至第—區域15此内的部分的p型基體區 104b上方。閘極u〇a、是由間極導電層以及閉介電 層所構成’ f雜導電層以及間介電層之側壁還可以形成間 隙壁。在一實施例中，閉極隐、ll〇b彼此電性連接，呈 1360874 UMCD-2008-0051 27920twf.doc/a 兩指狀。當然’靜電放電保護電路元件可以是由多個 LDNMOS元件構成，且各LDNM〇s元件的閘極可以彼此 連接，而呈多指狀，如圖1A所示。 在一實施例中’用於靜電放電保護電路之LDNMOS 元件10、20還分別包括N型淡摻雜區136a、n6b。N型 淡摻雜區136a位於閘極u〇a與N型第二摻雜區1〇8a之 間；N型淡摻雜區136b位於閘極11〇b與N型第二摻雜區 108b之間。 本發明之用於靜電放電保護電路之LDNMOS元件 10、20還可以包括p型井區U6a與n6b及防護環n8a與 118b。P型井區116a、116b分別位於N型深井區102的外 圍。防護環118a、118b分別位於n型井區116a、116b中。 在一貫施例中，防護環118a、iisb分別以隔離結構i〇la、 l〇lb與N型第二摻雜區108a、1〇gb隔絕。隔離結構1〇1& ' l〇lb可以是淺溝渠隔離(STI)結構或是場氧化層(F〇x)結 構。 值得注意的是，在本發明令，用於靜電放電保護電路 之LDMOS元件1〇、20還包括p型植入區132，其位於基 底100的第一區域140内。P型植入區132中的摻質例如 疋硼。P型植入區132的面積大於n型第一摻雜區1〇6之 面積，且小於N型階區130之面積。？型植入區132可與 現有的CDMOS製程整合’僅需藉由植入罩幕的形成以及離 子植入製程的施行即可形成之。p型植入區132的形成時 機並無特別的限制。p型植入區132的植入的深度與其植 11 1360874 UMCD-2008-0051 27920twf.doc/n 入的能量有關’其植入的能量約為10〜250 KeV。在一實施 例中，P型植入區132的劑量為N型階區130之劑量的0.5 〜1.5倍。在又一實施例中，p型植入區132的劑量為N 型階區130之劑量的0.7〜1.3倍。在另一實施例中，卩型 植入區132的劑量為N型階區130之劑量的〇.9〜U倍。 請參照圖1，在一實施例中，P型植入區132位於N 型第一摻雜區106與N型階區130之間。形成p型植入區 132的能量例如是1〇〜15 KeV ;劑量例如是2χ1〇13〜8χ1〇13 /cm2。 在另一實施例令，請參照圖2 ’ P型植入區132位於N 型階區130之中。形成p型植入區132的能量例如是15〜25 KeV ;劑量例如是 2χ1〇13〜8xl〇13/cm2。 在又一實施例中，請參照圖3’P型植入區132位於N 型階區130與N型深井區102之間。形成p型植入區132 的能量例如是25〜35 KeV;劑量例如是2χ1〇13〜8xl〇13 /cm2。 在又一實施例中’請參照圖4’P型植入區132位於N 型深井區102之中。形成p型植入區132的能量例如是 100〜200 KeV ;劑量例如是 2χ1〇13〜8xl〇13 /cm2。 以圖4所示之本發明之用於靜電放電保護電路之 LDNMOS元件1〇來說’當所施加的esd電壓值大於 LDNMOS元件10的N型深井區1〇2以及p型基體區i〇4a、 P型植入區132的接面的崩潰電壓時，透過累增崩潰機制 (avalanche breakdown mechanism)，將產生電子流與電洞 流。電洞流將流經P型基體區l〇4a而到達與源極線連接的 12 1360874 UMCD-2008-0051 27920twf.doc/n P型摻雜區134a，使得p型基體區i〇4a、P型植入區132 的電壓準位增加。詳而言之，當跨壓於P型基體區104a 電阻上的壓降大於側向npn BJT的切入電壓（cut_in voltage) ’由N型深井區1〇2、p型基體區i〇4a以及N型 第二摻雜區l〇8a所構成的侧向npnBJT將被觸發。當側向 npnBJT的被開啟之後，電洞流將注入經由p型植入區132 而被主入於P型摻雜區134a ’以增加P型植入區132的電 壓準位。然後，當所注入的電洞流大於一臨界值時，由N 型第一摻雜區106、P型植入區132以及N型深井區1〇2 所構成的垂直npn BJT將被開啟。一旦侧向npn BJT的以 及垂直ηρηΒΓΓ同時被開啟，在N型第一摻雜區1〇6、p 型植入區132、N型深井區1〇2以及p型摻雜區134a形成 低阻抗路徑’以有效釋放ESD電流。 同樣地，對於圖1〜3之用於靜電放電保護電路之 LDNMOS元件1〇來說，在N型第一摻雜區1〇6與N型 階區130之間所形成的p型植入區132,或是在N型階區 130之中所形成的P型植入區132,抑或是在]^型階區13〇 與N型深井區1〇2之間所形成的p型植入區132，均可以 與N型第一摻雜區1〇6、n型深井區1〇2構成垂直npn BJT，而與N型深井區ι〇2、Ρ型基體區1〇4a、N型第二摻 雜區108a組成之側向npnBJT形成低阻抗路徑，以有效釋 放ESD電流。 在以上的貫施例中，均是以單一且位於N型第一摻雜 區106正下方的p型植入區132來說明之。然而，本發明 13 1360874 UMCD-2008-0051 27920twf.doc/n 並不以此為限，P型植入區132可以是由多個分離的小區 域所構成。例如是，P型植入區132是由多個與基底表面 平行的小區域所構成。抑或是，由縱向排列的多個小區域 所構成，例如，P型植入區132可以選擇性地同時位在圖 1至圖4所示的任意兩個、三個區域或同時位在這四個區 域之中。 P型植入區132也不限於在N型第一摻雜區1〇6的正 下方’其可以略微偏離N型第一摻雜區1〇6的正下方而較 靠近閘極110a或110b。此外，p型植入區132的濃度並 不限於均勻分佈’也可以是成梯度分佈。 實驗例是以本發明之18伏特的LDNMOS元件來作為 用於ESD靜電放電保護電路元件。實驗例所形成的 LDNMOS元件在進行封裝之前’經測量之後的電性關係圖 如圖5所示。實驗例所形成的LDNM〇s元件及傳統的 LDNMOS元件在進行封裝之後，經人體放電模式(HBM) 與機盗放電模式(MM)測量之後的結果分別如表1與表2 所示。 表1 HBM HBM 測試（KV) 測試 逆向 正向 (KV) 晶粒1 晶粒2 晶粒3 晶粒4 晶粒5 晶粒6 傳統元件 1 1 1.2 1.8 1.8 1.8 >-8 實驗例 >8 >8 >8 >8 >8 >8 >-8 1360874 UMCD-2008-0051 27920twf.doc/n 表2 MM MM測試（ν') 測試 逆向 正向 (V) 晶粒1 晶粒2 晶粒3 晶粒4 晶粒5 晶粒6 傳统元件 125 200 150 125 -275 -825 -750 實驗例 >800 >800 >800 >800 -750 -750 -800 由圖5的結果顯示：實驗例之⑶丽⑽元件可以耐 響受8安培以上的電流且其觸發可維持在23伏特左右。 由表1、2的結果顯示：實驗例之人體放電模式(HBM) 測試的結果大於8 · 0 kV;機器放電模式(MM) _式的結果大 於 800 V。 綜合以上所述，本發明之用於靜電放電保護電路之 LDMOS元件可以在作為汲極的摻雜區下方增加不同導電 型的植入區確實可以達到提升用於高壓元件之ESD保護 兀件之效能，使其可以通過商用Ic的靜電放電耐受度必 籲 需通過人體放電模式(HBM) 2 kV與機器放電模式(MM) 200 V的測試。 另外，本發明之用於靜電放電保護電路之LDM〇s元件 可以應用在所有電源管理之半導體元件wer瓜如哗⑽抓1C) 上’製程簡單且可與現有的CDM〇s製程整合，且成本低，極 具競爭力。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，因此 15 1360874 27920twf.doc/n UMCD-2008-0051 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 圖1為依照本發明之一實施例所繪示的用於靜電放電 保護電路之LDNMOS元件之剖面示意圖。 圖1A為依照本發明之一實施例所繪示的用於靜電放 電保護電路之LDNMOS元件之上視圖。 圖2為依照本發明之另一實施例所繪示的用於靜電放 電保濩電路之LDNMOS元件之剖面示意圖。 圖3為依照本發明之又—實施例所繪示的用於靜電放 书保護電路之LDNMOS元件之剖面示意圖。 圖4為依照本發明之再—實施例所繪示的用於靜電放 電保護電路之LDNMOS元件之剖面示意圖。 圖5分別為依照本發明實驗例所形成的LDNM〇s在 進行封裝之前所測量的電性關係圖。 【主要元件符號說明】 10、20 : LDNMOS 元件 100 : P型基底 101a、101b :隔離結構 102 : N型深井區 104a、104b : P型基體區 106、108a、108b : N 型摻雜區 110a、110b :閘極 116a、116b : P 型井區 1360874 UMCD-2008-005 1 27920twf.doc/n 134a、134b : P型摻雜區 118a、118b :防護環 130 : N型階區 132 : P型植入區 136a、136b : N型淡摻雜區 140 :第一區域 150a、150b ··第二區域KeV; the dose is, for example, ίο11 〜5xi〇12/cm2. The N-type first doped region 106 is, for example, an N+ doped region located in the same conductivity type step region 130 as a common drain region for the ldnm〇s elements 10, 20 of the electrostatic discharge protection circuit by contact The window is electrically connected to the pad. In an embodiment, the energy for forming the N-type first doping region 1 〇 6 is, for example, 60 to 100 KeV; and the dose is, for example, 1 〇 14 〜 2 xi 〇 i 5 / cm 2 . The P-type base regions 104a, 104b are respectively located in the N-type deep well region 102 in the second region 15〇&, i5〇b 1360874 UMCD-2008-0051 27920twf.doc/n. In one embodiment, the energy for forming the p-type base regions 104a, 104b is, for example, 160 to 200 KeV; and the dose is, for example, 1 〇 12 to 4 x 10 13 /cm 2 . The N-type second doped regions 108a, 108b are, for example, N+ doped regions' located in the base regions 104a, 104b, respectively, as the source regions of the LDNMOS devices 10, 20 for the ESD protection circuit. In one embodiment, the energy for forming the N-type first doping regions 10a, 8b, 8b is, for example, 6 〇 to 1 〇〇 KeV; and the dose is, for example, 1014 to 2xl015/cm2. The P-type doped regions 134a, 134b are, for example, P+ doped regions, which are respectively located in the P-type base region 104a, the legs, and sandwiched between two N-type second mismatch regions l〇8a and two N-type second dopings. Miscellaneous area 1 〇 between. In an embodiment, the energy for forming the P-type doped regions 134a, 134b is, for example, 35 to 75, for example, 1 〇 14 〜 3 χ 1 〇 15 / 2 η 〇 型 type doped regions 134a, 13 s, respectively, and N The first doped regions 108a, 1b 8b are connected to the source through the contact window. The gate 110a is located on the /well region 102 between the first region 140 and the second region 15A and extends above the N-shaped region within the first region ι4〇 and extends to the second region 15〇& The inner portion is above the p-type base region 1 (10)a. The gate electrode ii〇b is located on the deep well region 102 between the first region 140 and the second region 15〇b, and extends to the N-type step region in the first region 14〇 130 is above and extending over the p-type base region 104b of the portion of the first region 15. The gate electrode u〇a is composed of a ferroelectric conductive layer and a closed dielectric layer The sidewalls of the layer may also form a spacer. In an embodiment, the closed-end hidden, ll〇b are electrically connected to each other, and are in the shape of 1360874 UMCD-2008-0051 27920twf.doc/a. Of course, the electrostatic discharge protection circuit component It may be composed of a plurality of LDNMOS elements, and the gates of the respective LDNM〇s elements may be connected to each other in a multi-finger shape as shown in FIG. 1A. In one embodiment, the LDNMOS element 10 for the electrostatic discharge protection circuit 20 further includes N-type lightly doped regions 136a, n6b, respectively. N-type lightly doped region 136a is located at the gate u a between the N-type second doped region 1〇8a; the N-type lightly doped region 136b is located between the gate 11〇b and the N-type second doped region 108b. The present invention is used for an electrostatic discharge protection circuit The LDNMOS elements 10, 20 may also include p-type well regions U6a and n6b and guard rings n8a and 118b. P-type well regions 116a, 116b are respectively located at the periphery of the N-type deep well region 102. The guard rings 118a, 118b are respectively located in the n-type well region. 116a, 116b. In a consistent embodiment, the guard rings 118a, iisb are isolated from the N-type second doped regions 108a, 1〇gb by isolation structures i〇la, l〇lb, respectively. Isolation structure 1〇1 & 'l The 〇 lb may be a shallow trench isolation (STI) structure or a field oxide layer (F 〇 x) structure. It is noted that, in the present invention, the LDMOS elements 1 and 20 for the electrostatic discharge protection circuit further include a p-type An implanted region 132 is located within the first region 140 of the substrate 100. The dopant in the P-type implant region 132 is, for example, boron. The area of the P-type implant region 132 is greater than the n-type first doped region 1〇6. The area is smaller than the area of the N-type terrace 130. The implanted area 132 can be integrated with the existing CDMOS process 'only by the formation of the implant mask and ion implantation The process of the process can be formed. The timing of formation of the p-type implanted region 132 is not particularly limited. The depth of implantation of the p-type implanted region 132 is the same as that of the implantation of the p-type implanted region 132 1 UMCD-2008-0051 27920 twf.doc/n The energy-related energy is about 10 to 250 KeV. In one embodiment, the dose of the P-type implant region 132 is 0.5 to 1.5 times the dose of the N-type region 130. In yet another embodiment, the dose of p-type implanted region 132 is 0.7 to 1.3 times the dose of N-type terrace 130. In another embodiment, the dose of the sputum implanted region 132 is 〇.9 to U times the dose of the N-type terrace 130. Referring to FIG. 1, in an embodiment, a P-type implant region 132 is between the N-type first doped region 106 and the N-type terrace region 130. The energy for forming the p-type implanted region 132 is, for example, 1 〇 15 15 KeV; the dose is, for example, 2 χ 1 〇 13 〜 8 χ 1 〇 13 / cm 2 . In another embodiment, please refer to FIG. 2' The P-type implant region 132 is located in the N-type terrace 130. The energy for forming the p-type implanted region 132 is, for example, 15 to 25 KeV; the dose is, for example, 2χ1〇13~8xl〇13/cm2. In yet another embodiment, please refer to FIG. 3'P-type implant region 132 between N-type terrace 130 and N-type deep well region 102. The energy for forming the p-type implanted region 132 is, for example, 25 to 35 KeV; the dose is, for example, 2χ1〇13~8xl〇13/cm2. In yet another embodiment, please refer to Figure 4, where the P-type implant region 132 is located in the N-type deep well region 102. The energy for forming the p-type implanted region 132 is, for example, 100 to 200 KeV; the dose is, for example, 2χ1〇13~8xl〇13/cm2. In the LDNMOS device 1 for the electrostatic discharge protection circuit of the present invention shown in FIG. 4, 'when the applied esd voltage value is larger than the N-type deep well region 1〇2 of the LDNMOS device 10 and the p-type base region i〇4a When the breakdown voltage of the junction of the P-type implant region 132 is generated, an electron flow and a hole flow are generated by an avalanche breakdown mechanism. The hole current will flow through the P-type base region l〇4a to reach the 12 1360874 UMCD-2008-0051 27920twf.doc/n P-type doped region 134a connected to the source line, so that the p-type base region i〇4a, P The voltage level of the implanted region 132 is increased. In detail, when the voltage drop across the resistance of the P-type base region 104a is greater than the cut-in voltage of the lateral npn BJT 'from the N-type deep well region 1, 2, the p-type base region i〇4a and N The lateral npnBJT formed by the type second doping region 10a will be triggered. After the lateral npnBJT is turned on, the hole current is implanted into the P-doped region 134a' via the p-type implant region 132 to increase the voltage level of the P-type implant region 132. Then, when the injected hole flow is greater than a critical value, the vertical npn BJT composed of the N-type first doping region 106, the P-type implant region 132, and the N-type deep well region 1〇2 will be turned on. Once the lateral npn BJT and vertical ηρηΒΓΓ are simultaneously turned on, a low impedance path is formed in the N-type first doped region 1〇6, the p-type implant region 132, the N-type deep well region 1〇2, and the p-type doped region 134a. 'To effectively release the ESD current. Similarly, for the LDNMOS device 1 for the electrostatic discharge protection circuit of FIGS. 1 to 3, a p-type implant region formed between the N-type first doping region 1〇6 and the N-type step region 130 is formed. 132, or a P-type implant region 132 formed in the N-type terrace 130, or a p-type implant region formed between the ^-type step region 13〇 and the N-type deep well region 1〇2 132, both can form a vertical npn BJT with the N-type first doped region 1〇6, the n-type deep well region 1〇2, and the N-type deep well region ι〇2, the Ρ-type base region 1〇4a, N-type second The lateral npnBJT, which is composed of doped regions 108a, forms a low impedance path to effectively release the ESD current. In the above embodiments, each is illustrated as a single p-type implant region 132 directly under the N-type first doped region 106. However, the present invention 13 1360874 UMCD-2008-0051 27920 twf.doc/n is not limited thereto, and the P-type implanted region 132 may be composed of a plurality of separate cell domains. For example, the P-type implant region 132 is composed of a plurality of small regions parallel to the surface of the substrate. Or, it is composed of a plurality of small regions arranged in a longitudinal direction. For example, the P-type implant region 132 can be selectively simultaneously positioned in any two, three regions shown in FIG. 1 to FIG. 4 or simultaneously. Among the areas. The P-type implant region 132 is also not limited to being directly below the N-type first doped region 1〇6. It may be slightly offset from directly below the N-type first doped region 1〇6 and closer to the gate 110a or 110b. Further, the concentration of the p-type implanted region 132 is not limited to a uniform distribution' and may be a gradient distribution. The experimental example was based on the 18 volt LDNMOS device of the present invention as an ESD electrostatic discharge protection circuit element. The electrical relationship diagram of the LDNMOS device formed in the experimental example before being packaged is shown in Fig. 5. The results of the LDNM〇s component and the conventional LDNMOS device formed in the experimental example after being packaged by the human body discharge mode (HBM) and the pirate discharge mode (MM) are shown in Tables 1 and 2, respectively. Table 1 HBM HBM Test (KV) Test Reverse Forward (KV) Grain 1 Grain 2 Grain 3 Grain 4 Grain 5 Grain 6 Conventional Components 1 1 1.2 1.8 1.8 1.8 >-8 Experimental Example >8 >8 >8 >8 >8 >8 >-8 1360874 UMCD-2008-0051 27920twf.doc/n Table 2 MM MM Test (ν') Test Reverse Forward (V) Grain 1 Crystal Grain 2 Grain 3 Grain 4 Grain 5 Grain 6 Conventional element 125 200 150 125 -275 -825 -750 Experimental Example >800 >800 >800 >800 -750 -750 -800 From Figure 5 The results show that the (3) Li (10) component of the experimental example can withstand a current of 8 amps or more and its trigger can be maintained at about 23 volts. The results of Tables 1 and 2 show that the results of the human body discharge mode (HBM) test of the experimental example are greater than 8 · 0 kV; the result of the machine discharge mode (MM) _ formula is greater than 800 V. In summary, the LDMOS device for the ESD protection circuit of the present invention can increase the efficiency of the ESD protection component for the high voltage component by adding different conductivity type implant regions under the doping region as the drain electrode. To make it possible to pass the commercial Ic's ESD tolerance must be tested by Human Body Discharge Mode (HBM) 2 kV and Machine Discharge Mode (MM) 200 V. In addition, the LDM 〇 s component of the present invention for electrostatic discharge protection circuit can be applied to all power management semiconductor components, such as 制 哗 哗 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Low and very competitive. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the scope of the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. 1360874 27920 twf.doc/n UMCD-2008-0051 The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an LDNMOS device for an ESD protection circuit according to an embodiment of the invention. 1A is a top view of an LDNMOS device for an electrostatic discharge protection circuit in accordance with an embodiment of the invention. 2 is a cross-sectional view of an LDNMOS device for an electrostatic discharge protection circuit in accordance with another embodiment of the present invention. 3 is a cross-sectional view of an LDNMOS device for an electrostatic discharge protection circuit in accordance with yet another embodiment of the present invention. 4 is a cross-sectional view of an LDNMOS device for an electrostatic discharge protection circuit in accordance with yet another embodiment of the present invention. Fig. 5 is a graph showing the electrical relationship of LDNM〇s formed in accordance with an experimental example of the present invention before being packaged. [Main component symbol description] 10, 20: LDNMOS device 100: P-type substrate 101a, 101b: isolation structure 102: N-type deep well region 104a, 104b: P-type substrate region 106, 108a, 108b: N-type doping region 110a, 110b: gate 116a, 116b: P-type well region 1360874 UMCD-2008-005 1 27920twf.doc/n 134a, 134b: P-type doped region 118a, 118b: guard ring 130: N-type terrace 132: P-type implant Incoming region 136a, 136b: N-type lightly doped region 140: first region 150a, 150b · · second region
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