TWI455275B - Electrostatic discharge (esd) protection device - Google Patents

Description

Electrostatic discharge protection device

The invention relates to an electrostatic discharge protection device, in particular to an electrostatic discharge protection device with adjustable latch voltage and trigger voltage.

In the conventional high voltage (HV) component process, the holding voltage of the Electrostatic Discharge (ESD) protection component cannot be greater than the operating voltage (VDD) of the circuit, so the integrated circuit component will work normally because The surge interference causes the integrated circuit components to latch-up and burn out. However, the conventional technique increases the trigger voltage of the ESD protection component at the same time, so that the ESD protection component cannot effectively protect the internal circuit.

There is a need in the art for a semiconductor device having an ESD protection component that can adjust the latch voltage and trigger voltage to improve the above disadvantages.

In view of the above, an embodiment of the present invention provides an electrostatic discharge protection device including a semiconductor substrate having a first conductivity type, an epitaxial layer on the semiconductor substrate, wherein the epitaxial layer has the first conductive layer a pattern of an isolation region disposed on the epitaxial layer to define a first active region and a second active region; a first well region disposed in the epitaxial layer and surrounding the first active region and The second active region, wherein the first well region has a second conductivity type opposite to the first conductivity type; a gate structure is disposed on the isolation region pattern, and is located in the first active region and the first Between the two active regions; a first doped region disposed in the first active region and located on the first well region, wherein the first doped region has the second conductivity type; a second doping a region, disposed in the second active region, and located on the first well region, wherein the second doped region has the first conductivity type; a drain doped region is disposed in the first doped region a source doped region and a first doped region doped adjacent to each other are disposed in the second doped region, wherein the source doped region has the second conductivity type, and the first wire bonding is performed The impurity region has the first conductivity type; a source contact plug connecting the source doping region, the source contact plug has an extension portion, wherein the extension portion covers the top view of the first wire doped region The ratio of the area to the upper view area of the first wire doping region is between 0 and 1.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

FIG. 1 is a cross-sectional view showing an electrostatic discharge (ESD) protection device 500a according to an embodiment of the present invention. In the present embodiment, the ESD protection device 500a can be regarded as a gate insulated double junction transistor electrostatic discharge protection component (IGBT-ESD) 500a. The main components of the ESD protection device 500a may include a semiconductor substrate 200, an epitaxial layer 202, a first well region 206, a first doped region 208, a second doped region 210, a drain doped region 212, and adjacent to each other. a source doped region 214 and a first wire doped region 216, a gate structure 224, and a source contact plug 218, wherein the source contact plug 218 has an adjustable variable size extension 230 to change Covers the area of the source active area. In one embodiment of the present invention, the drain doping region 212 can be coupled to a device operating voltage VDD, and the source doping region 214, or the source doping region 214 and the first bonding doping region 216 can be coupled. Connected to a circuit common ground terminal voltage VSS.

In an embodiment of the invention, the semiconductor substrate 200 may be a germanium substrate. In other embodiments of the present invention, germanium telluride (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, or other commonly used semiconductor substrates may be utilized. In an embodiment of the invention, the semiconductor substrate 200 can be implanted with p-type or n-type impurities to change its conductivity type for design needs. In the present embodiment, the semiconductor substrate 200 has a first conductivity type such as a p-type. An epitaxial layer 202 is disposed on the semiconductor substrate 200. In the present embodiment, the epitaxial layer 202 has a first conductivity type such as a p-type, for example, a p-type. In an embodiment of the invention, a buried layer 204 having a second conductivity type, such as an n-type, is disposed on an interface 240 of the semiconductor substrate 200 and the epitaxial layer 202. In other embodiments of the present invention, the semiconductor substrate 200, the buried layer 204, and the epitaxial layer 202 may be a substrate of a silicon on insulator (SOI) substrate, a buried oxide layer, and an epitaxial layer, respectively.

As shown in FIG. 1, the isolation region pattern 201 is disposed on the epitaxial layer 202, and defines a first active region AR1 and a second active region AR2. In an embodiment of the invention, the isolation region pattern 201 may be a shallow trench isolation (STI). In this embodiment, the first active area AR1 can be regarded as a drain active area of the electrostatic discharge protection device 500a, and the second active area AR2 can be regarded as the source active area of the electrostatic discharge protection device 500a.

As shown in FIG. 1, the first well region 206 is disposed in the epitaxial layer 202 and surrounds the first active region AR1 and the second active region AR2. In an embodiment of the invention, the first well region 206 has a second conductivity type, such as an n-type, such as a high pressure n-type well region (HVNW). As shown in FIG. 1, a bottom surface of the first well region 206 is connected to the buried layer 204.

As shown in FIG. 1, the gate structure 224 of the electrostatic discharge protection device 500a of the embodiment of the present invention is disposed on the isolation region pattern 201 and located between the first active region AR1 and the second active region AR2. In addition, the gate structure 224 is located within the boundary of the isolation region pattern 201 and does not extend to the first active region AR1 or the second active region AR2. In the embodiment of the present invention, the gate structure 224 may be composed of a gate insulating layer of a lower layer and a gate layer of an upper layer, wherein the gate insulating layer may include, for example, an oxide, a nitride, and a nitrogen. Common dielectric materials such as oxynitride, oxycarbide or combinations thereof. The gate insulating layer may also include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), hafnium silicate (HfSiO ₄ ), Zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO ₄ ), yttrium oxide (Y ₂ O ₃ ), lanthanum oxide (La) High dielectric constant (high-k, ₂ O ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ) or a combination thereof A dielectric material having an electrical constant greater than 8). The gate layer may include germanium or polysilicon. The gate layer is preferably doped with a dopant to reduce its sheet resistance. In other embodiments, the gate layer comprises amorphous silicon. As shown in FIG. 1 , the first doping region 208 and the second doping region 210 in the embodiment of the present invention are respectively disposed in the first active region AR1 and the second active region AR2, and are located in the first well region 206. on. The first doped region 208 and the second doped region 210 are respectively adjacent to two sides of the gate structure 224 on opposite sides of each other. In an embodiment of the invention, the first doped region 208 has a second conductivity type, such as an n-type, for example, an n-type drift drain region 208, which is A portion of the drain of the ESD protection device 500a. As shown in FIG. 1, the first doped region 208 extends toward the gate structure 224 and partially overlaps the isolation region pattern 201 under the gate structure 224. The vertical boundary of the first doped region 208 is substantially aligned with the gate structure. One side of 224. In the embodiment of the present invention, the second doping region 210 has a first conductivity type such as a p-type, for example, can be regarded as a p-type body region 210 as an electrostatic discharge protection device. The channel region of the 500a and a part of the source. As shown in FIG. 1, the second doped region 210 extends toward the gate structure 224, partially overlapping the isolation region pattern 201 under the gate structure 224, and the vertical boundary of the second doped region 210 is substantially at the gate structure. Just below 224. Additionally, the ESD protection device 500a further includes a semiconductor ring 222 disposed on the isolation pattern 201 above the boundary of the first well region 206. The semiconductor ring 222 is separated from the gate structure 224 by the first active region AR1 and the second active region AR2, which can increase the breakdown voltage (VBD) of the device. In an embodiment of the invention, the semiconductor ring 222 and the gate structure 224 may be the same material and may be formed in the same process step. In the present embodiment, the semiconductor ring 222 may be a poly ring.

As shown in FIG. 1, the drain doping region 212 of the ESD protection device 500a of the embodiment of the present invention is disposed in the first doping region 208, and the boundary of the drain doping region 212 is the first doping region. Surrounded by 208. In an embodiment of the invention, the drain doped region 212 has a first conductivity type, such as a p-type, for example, a p-type drain heavily doped region (p+ drain region). A boundary of the drain doping region 212 is substantially in contact with the isolation region pattern 201 defining the first active region AR1, and thus the upper viewing area of the gate doping region 212 is substantially equal to the upper viewing area of the first active region AR1. .

As shown in FIG. 1, the ESD protection device 500a of the embodiment of the present invention further includes a source doping region 214 and a first wire doping region 216 adjacent to each other, and is disposed in the second doping region 210. The boundary of the source doping region 214 and the first bonding doping region 216 is surrounded by the second doping region 210. In an embodiment of the invention, the source doping region 214 has a second conductivity type, such as an n-type, such as an n-source region. Additionally, the first wire doped region 216 has a first conductivity type, such as a p-type, such as a first wire doped region 216 that can be considered a p-type body region 210. In the embodiment of the present invention, the upper view area of the first wire doped region 216 is designed to be larger than the upper view area of the source doped region 214, and the top view of the first wire doped region 216 and the source doped region 214 The total area is substantially equal to the upper view area of the second active area AR2. As shown in FIG. 1, a boundary of the first wire doped region 216 is substantially in contact with the isolation region pattern 201 under the gate structure 224.

As shown in FIG. 1, the source contact plug 218 of the ESD protection device 500a of the embodiment of the present invention is connected to the source doping region 214 for coupling the source doping region 214 to the common ground terminal voltage of the circuit. VSS. In the embodiment of the present invention, the source contact plug 218 is designed to have an extension portion 230 extending over the first wire doped region 216. In the embodiment of the present invention, the extension portion 230 has a variable size, that is, the extension portion 230 has a variable length in the cross-sectional view as shown in FIG. 1 so that the extension portion 230 covers the first wire blending. The upper viewing area of the miscellaneous region 216 and the upper viewing area A ratio of the first bonding doping region 216 are between 0 and 1, meaning that the extension portion 230 can be adjusted to cover the area of the first bonding doping region 216. In the process, the area of the silicide block located in the second active area AR2 can be adjusted and combined with the subsequent deuteration process to form the extension portions 230 of different sizes. In addition, as shown in FIG. 1, the drain contact plug 220 of the ESD protection device 500a of the embodiment of the present invention is connected to the drain doping region 212 for coupling the gate doping region 212 to the component operating voltage. VDD.

Next, the operation mechanism of the electrostatic discharge protection device 500a of the embodiment of the present invention will be described. Please refer to FIGS. 1 and 2 at the same time. FIG. 2 is an equivalent circuit diagram of the electrostatic discharge protection device 500a shown in FIG. 1. As shown in FIGS. 1 and 2, for example, a drain-doped region 212 of a p-type drain heavily doped region (p+drain region) and, for example, an n-type drift drain region The first doped region 208 constitutes a pn junction diode, and the gate doped region 212 is coupled to the component operating voltage VDD. Also, for example, a first doped region 208 of an n-type drift drain region, a first well region 206 such as a high voltage n-type well region (HVNW), such as a p-type body The second doped region 210 of the p-type body region, for example, the source doped region 214 of the n-type source region, together form a parasitic n-type-p a n-type bipolar junction transistor (NPN BJT), wherein the first doped region 208 is, for example, an n-type drift drain region For example, the first well region 206 of the high voltage n-type well region (HVNW) can be regarded as the collector of the parasitic NPN BJT, for example, the second doping of the p-type body region. The region 210 can be regarded as the base of the parasitic NPN BJT, and the source doped region 214 of, for example, an n-type source heavily doped region (n+ source region) can be regarded as the emitter of the parasitic NPN BJT ( Emitters, and the collector of the parasitic NPN BJT is coupled to the component operating voltage VDD, and the emitter of the parasitic NPN BJT is coupled to the circuit common ground terminal voltage VSS. In addition, the first wire doping region 216 not covered by the extension portion 230 of the source contact plug 218 can be regarded as a variable parasitic resistance, and both ends of the adjustable parasitic resistance are electrically connected to the NPN BJT. Both the pole and the base mean the cathode end of the ESD component. When subjected to ESD or zapping from the component operating voltage VDD, the parasitic NPN BJT is triggered to form a path from the component operating voltage VDD to the circuit common ground terminal voltage VSS. Therefore, a large number of holes will pass from the p-type drain doping region 212 via the first doping region 208, such as an n-type drift drain region, and for example, a high voltage n-well region. The first well region 206 of (HVNW) is implanted into the second doped region 210 of the p-type body region, and then via the first wire doped region 216, for example, a p-type doped region. The variable parasitic resistance and the source doping region 214, for example, an n-type source region, direct the hole to the circuit common ground terminal voltage VSS. It can be seen that the parasitic NPN BJT can conduct a large amount of ESD transient current without damaging the protected internal circuit.

The area of the first wire doping region 216 is covered by adjusting the extension portion 230 of the source contact plug 218 to change the parasitic resistance value connected to the cathode end of the entire electrostatic discharge protection device 500a, thereby adjusting the electrostatic discharge protection device. The difference between the device trigger voltage of 500a and the holding voltage. Please refer to FIGS. 1 to 3 at the same time. FIG. 3 is an extension portion 230 of the ESD protection device 500a shown in FIG. 1 covering the area of the first wire doping region 216 and its corresponding device trigger voltage and latch voltage. When the extension portions 230 are respectively located at the positions B0 and B1 (that is, the extension portion 230 covers part and all of the source doping regions 214 and has not covered the first wire doping region 216), the device of the electrostatic discharge protection device 500a The trigger voltages are 40V and 43V, respectively, and the latch voltages are 33V and 34V, respectively. In addition, when the extension portion 230 is changed from the position B6 to B1 (that is, the case where the extension portion 230 covers the area where the first wire doping region 216 is decremented), the parasitic resistance of the electrostatic discharge protection device 500a is increased, as shown in FIG. As shown, when the area of the first wire doping region 216 is reduced, the amplitude of the trigger voltage of the ESD protection device 500a of the embodiment of the present invention may be greater than the amplitude of the latch voltage. For example, when the extension portion 230 covers the first wire doping region 216 (the extension portion 230 is at the position B6), the trigger voltage and the latch voltage of the ESD protection device 500a are 79V and 49V, respectively; when the first wire is doped When the region 216 is completely exposed from the extension portion 230 (the extension portion 230 is at the position B1), the trigger voltage and the latch voltage of the electrostatic discharge protection device 500a are 43V and 34V, respectively. The electrostatic discharge protection device 500a of the embodiment of the present invention covers the area of the first wire doping region 216 by adjusting the extension portion 230 of the source contact plug 218 to reduce the difference between the trigger voltage and the latch voltage of the ESD protection device. . Compared with the conventional electrostatic discharge protection device, the electrostatic discharge protection device 500a of the embodiment of the invention can increase the device latch voltage and mitigate the increase of the trigger voltage without stacking. Avoid triggering the ESD protection device under the normal operating voltage of the component, and latch-up occurs to damage the internal circuit. Therefore, the performance of the ESD protection device can be improved.

Fig. 4 is a cross-sectional view showing an electrostatic discharge protection device 500b according to another embodiment of the present invention. Fig. 5 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device 500b shown in Fig. 4. In the present embodiment, the ESD protection device 500b can be regarded as a gate grounded n-type metal-oxide-semiconductor electrostatic grounding protection device (gate grounded NMOS, GGNMOS) 500b. The electrostatic discharge protection device 500b differs from the electrostatic discharge protection device 500a in that the drain doping region 226 of the electrostatic discharge protection device 500b has a second conductivity type, for example, an n-type, such as an n-type drain heavily doped region ( n+ drain region). As shown in FIGS. 4 and 5, for example, an n-type drain doped region 226, such as a first doped region 208 of an n-type drift drain region, such as a high voltage n a first well region 206 of a well region (HVNW), such as a second doped region 210 of a p-type body region, such as an n-type source heavily doped region (n+ source region) The source doped regions 214 together form a parasitic n-type p-type n-type junction bipolar junction transistor (NPN BJT), wherein, for example, n-type germanium doping Region 226, a first doped region 208, such as an n-type drift drain region, and a first well region 206, such as a high voltage n-well region (HVNW), may be considered as parasitic The collector of the NPN BJT, for example, the second doped region 210 of the p-type body region may be regarded as the base of the parasitic NPN BJT, and is, for example, n-type. The source doped region 214 of the source heavily doped region (n+ source region) may be regarded as the emitter of the parasitic NPN BJT, and the collector of the parasitic NPN BJT is coupled to the component operating voltage VDD. The emitter of the parasitic NPN BJT lines coupled to the circuit common ground voltage VSS. In addition, the first wire doping region 216 not covered by the extension portion 230 of the source contact plug 218 can be regarded as a variable parasitic resistance, and both ends of the adjustable parasitic resistance are electrically connected to the NPN BJT. Both the pole and the base mean the cathode end of the ESD device 500b.

Figure 6 is a cross-sectional view showing an electrostatic discharge protection device 500c according to still another embodiment of the present invention. Fig. 7 is an equivalent circuit diagram of the electrostatic discharge protection device 500c shown in Fig. 6. In the present embodiment, the ESD protection device 500c can be regarded as an n-type silicon controlled rectifier (SCR) (NSCR) 500c. The drain doped region 232 of the ESD protection device 500c has a first conductivity type, such as a p-type, such as a p-drain region. The difference between the ESD protection device 500c and the ESD protection device 500a is that the ESD protection device 500a further includes a second wire doping region 234 disposed in the first doping region 208 and surrounding the gate doping region 232. The second wire doped region 234 has a second conductivity type, such as an n-type, such as an n-type wire doped region 234. In another embodiment of the present invention, the positions of the drain doping region 232 and the second bonding doping region 234 may be interchanged. For example, the drain doping region 232 surrounds the second bonding doping region 234. As shown in FIGS. 6 and 7, a gate doped region 232, such as a p-type drain heavily doped region (p+ drain region), and a second wire doped region 234, such as an n-type doped region, constitute a The pn junction diode is coupled to the component operating voltage VDD. Also, for example, a first doped region 208 of an n-type drift drain region, a first well region 206 such as a high voltage n-type well region (HVNW), such as a p-type body The second doped region 210 of the p-type body region, for example, the source doped region 214 of the n-type source region, together form a parasitic n-type-p An n-type bipolar junction transistor (NPN BJT), wherein the second wire doped region 234 is, for example, an n-type doped region, for example, an n-type drift drain doping A first doped region 208 of an n-type drift drain region and a first well region 206 such as a high voltage n-type well region (HVNW) may be considered as a collector of the parasitic NPN BJT, such as p The second doped region 210 of the p-type body region may be regarded as the base of the parasitic NPN BJT, and is, for example, an n-type source heavily doped region (n+ source region) The source doping region 214 can be regarded as the emitter of the parasitic NPN BJT, and the collector of the parasitic NPN BJT is coupled to the component operating voltage VDD, and the parasitic NPN BJT Emitter lines coupled to a common circuit ground voltage VSS. In addition, the first wire doping region 216 not covered by the extension portion 230 of the source contact plug 218 can be regarded as a variable parasitic resistance, and both ends of the adjustable parasitic resistance are electrically connected to the NPN BJT. Both the pole and the base mean the cathode end of the ESD device 500b.

Similarly, the ESD protection devices 500b and 500c of other embodiments of the present invention cover the area of the first wire doping region 216 by adjusting the extension portion 230 of the source contact plug 218 to reduce the trigger voltage of the ESD protection device and The difference in latch voltage. Compared with the conventional electrostatic discharge protection device, the electrostatic discharge protection devices 500b and 500c of the embodiments of the present invention can increase the device latch voltage and ease the increase of the trigger voltage without stacking. Avoid triggering the ESD protection device under the normal operating voltage of the component, and latch-up occurs to damage the internal circuit. Therefore, the performance of the ESD protection device can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.

200. . . Semiconductor substrate

201. . . Shallow trench spacer

202. . . Epitaxial layer

204. . . Buried layer

206. . . First well area

208. . . First doped region

210. . . Second doped region

212, 226, 232. . . Bipolar doping zone

214. . . Source doping region

216. . . First wire doping zone

218. . . Source contact plug

220. . . Bungee contact plug

222. . . Semiconductor ring

224. . . Gate structure

230. . . Extension

234. . . Second wire doping zone

240. . . interface

500a, 500b, 500c. . . Electrostatic discharge protection device

VDD. . . Component operating voltage

VSS. . . Circuit common ground voltage

A. . . area

B0, B1, B2, B3, B4, B5, B6. . . position

Fig. 1 is a schematic cross-sectional view showing an electrostatic discharge protection device according to an embodiment of the present invention.

Fig. 2 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device shown in Fig. 1.

Figure 3 is a diagram showing the area of the wire-doped region covered by the extended portion of the ESD protection device shown in Figure 1 and its corresponding device trigger voltage and latch voltage.

Figure 4 is a cross-sectional view showing an electrostatic discharge protection device according to another embodiment of the present invention.

Fig. 5 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device shown in Fig. 4.

Figure 6 is a cross-sectional view showing an electrostatic discharge protection device according to still another embodiment of the present invention.

Fig. 7 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device shown in Fig. 6.

200. . . Semiconductor substrate

201. . . Shallow trench spacer

202. . . Epitaxial layer

204. . . Buried layer

206. . . First well area

208. . . First doped region

210. . . Second doped region

212. . . Bipolar doping zone

214. . . Source doping region

216. . . First wire doping zone

218. . . Source contact plug

220. . . Bungee contact plug

222. . . Semiconductor ring

224. . . Gate structure

230. . . Extension

240. . . interface

500a. . . Electrostatic discharge protection device

VDD. . . Component operating voltage

VSS. . . Circuit common ground voltage

A. . . area

B0, B1, B2, B3, B4, B5, B6. . . position

Claims (10)

An electrostatic discharge protection device comprising: a semiconductor substrate having a first conductivity type; an epitaxial layer on the semiconductor substrate, wherein the epitaxial layer has the first conductivity type; and an isolation region pattern disposed on the a first active region and a second active region are defined on the epitaxial layer; a first well region is disposed in the epitaxial layer and surrounds the first active region and the second active region, wherein the first The well region has a second conductivity type opposite to the first conductivity type; a gate structure is disposed on the isolation region pattern and located between the first active region and the second active region; a doped region disposed in the first active region and located on the first well region, wherein the first doped region has the second conductivity type; and a second doped region disposed in the second active region And located on the first well region, wherein the second doped region has the first conductivity type; a drain doped region is disposed in the first doped region; a source doping adjacent to each other a region and a first doped region, disposed in the second doped region, The source doping region has the second conductivity type, and the first wire doping region has the first conductivity type; and a source contact plug connecting the source doping region, the source contact plug Having an extension portion, wherein the extension portion covers an upper view area of the first wire doped region and a top view area ratio of the first wire doped region is between 0 and 1, wherein the gate structure is located in the isolation Within the boundaries of the zone pattern. For example, the electrostatic discharge protection device described in claim 1 is Wherein the first conductivity type is p-type and the second conductivity type is n-type. The electrostatic discharge protection device of claim 2, wherein the drain doping region has the first conductivity type. The electrostatic discharge protection device of claim 2, wherein the drain doped region has the second conductivity type. The electrostatic discharge protection device of claim 2, further comprising a second wire doping region disposed in the first doping region and surrounding the gate doping region, wherein the drain doping region The region has the first conductivity type, and the second wire doped region has the second conductivity type. The electrostatic discharge protection device of claim 1, wherein a top view area of the first wire doped region is larger than an upper view area of the source doped region. The electrostatic discharge protection device of claim 1, wherein the first doped region and the second doped region extend below the isolation region pattern, respectively. The electrostatic discharge protection device of claim 1, further comprising a buried layer on an interface between the semiconductor substrate and the epitaxial layer and connected to a bottom surface of the first well region, wherein the buried The layer has this second conductivity type. The electrostatic discharge protection device of claim 2, wherein the first doping region, the first well region, the second doping region, and the source doping region form an n-type-p type a n-type junction bipolar transistor, wherein the first doped region and the first well region are collectors of the n-type-p-n-type junction bipolar transistor, the second doping The region is the base of the n-type-p-n-type junction bipolar transistor, and the source doped region is the n-type-p-n junction The emitter of the carrier transistor. The electrostatic discharge protection device of claim 9, wherein the first wire doping region not covered by the extension portion is a variable resistance resistor, and both ends of the adjustable resistor are electrically connected to Both the emitter and the base of the n-type-p-n-type junction bipolar transistor.