TW201340286A - Electrostatic discharge (ESD) protection device - Google Patents
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本發明係有關於一種靜電放電防護裝置,特別係有關於一種可調變栓鎖電壓和觸發電壓之靜電放電防護裝置。The invention relates to an electrostatic discharge protection device, in particular to an electrostatic discharge protection device with adjustable latch voltage and trigger voltage.
傳統高電壓(HV)元件製程中,靜電放電(Electrostatic Discharge,簡稱ESD)防護元件的栓鎖電壓(holding voltage)無法大於電路的操作電壓(VDD),因此在積體電路元件正常工作時會因為突波干擾而導致積體電路元件發生閂鎖效應(latch-up)而燒毀。然而,習知技術在提升ESD防護元件的栓鎖電壓時,會同時提高觸發電壓(trigger voltage),以致於ESD防護元件無法有效保護內部電路。In the conventional high voltage (HV) component process, the holding voltage of the Electrostatic Discharge (ESD) protection component cannot be greater than the operating voltage (VDD) of the circuit, so the integrated circuit component will work normally because The surge interference causes the integrated circuit components to latch-up and burn out. However, the conventional technique increases the trigger voltage of the ESD protection component at the same time, so that the ESD protection component cannot effectively protect the internal circuit.
在此技術領域中,有需要一種具有可調整栓鎖電壓和觸發電壓之ESD防護元件之半導體裝置,以改善上述缺點。There is a need in the art for a semiconductor device having an ESD protection component that can adjust the latch voltage and trigger voltage to improve the above disadvantages.
有鑑於此,本發明之實施例係提供一種靜電放電防護裝置,包括一半導體基板,具有一第一導電類型;一磊晶層,位於上述半導體基板上,其中上述磊晶層具有上述第一導電類型;一隔離區圖案,設置於上述磊晶層上,定義一第一主動區及一第二主動區;一第一井區,設置於上述磊晶層中,且包圍上述第一主動區及上述第二主動區,其中上述第一井區具有相反於上述第一導電類型的一第二導電類型;一閘極結構,設置於上述隔離區圖案上,且位於上述第一主動區及上述第二主動區之間;一第一摻雜區,設置於上述第一主動區中,且位於上述第一井區上,其中上述第一摻雜區具有上述第二導電類型;一第二摻雜區,設置於上述第二主動區中,且位於上述第一井區上,其中上述第二摻雜區具有上述第一導電類型;一汲極摻雜區,設置於上述第一摻雜區中;彼此相鄰的一源極摻雜區和一第一打線摻雜區,設置於上述第二摻雜區中,其中上述源極摻雜區具有上述第二導電類型,且上述第一打線摻雜區具有上述第一導電類型;一源極接觸插塞,連接上述源極摻雜區,上述源極接觸插塞具有一延伸部分,其中上述延伸部分覆蓋上述第一打線摻雜區的上視面積與上述第一打線摻雜區的上視面積比值介於0至1之間。In view of the above, an embodiment of the present invention provides an electrostatic discharge protection device including a semiconductor substrate having a first conductivity type, an epitaxial layer on the semiconductor substrate, wherein the epitaxial layer has the first conductive layer a pattern of an isolation region disposed on the epitaxial layer to define a first active region and a second active region; a first well region disposed in the epitaxial layer and surrounding the first active region and The second active region, wherein the first well region has a second conductivity type opposite to the first conductivity type; a gate structure is disposed on the isolation region pattern, and is located in the first active region and the first Between the two active regions; a first doped region disposed in the first active region and located on the first well region, wherein the first doped region has the second conductivity type; a second doping a region, disposed in the second active region, and located on the first well region, wherein the second doped region has the first conductivity type; a drain doped region is disposed in the first doped region a source doped region and a first doped region doped adjacent to each other are disposed in the second doped region, wherein the source doped region has the second conductivity type, and the first wire bonding is performed The impurity region has the first conductivity type; a source contact plug connecting the source doping region, the source contact plug has an extension portion, wherein the extension portion covers the top view of the first wire doped region The ratio of the area to the upper view area of the first wire doping region is between 0 and 1.
以下以各實施例詳細說明並伴隨著圖式說明之範例,做為本發明之參考依據。在圖式或說明書描述中,相似或相同之部分皆使用相同之圖號。且在圖式中,實施例之形狀或是厚度可擴大,並以簡化或是方便標示。再者,圖式中各元件之部分將以分別描述說明之,值得注意的是,圖中未繪示或描述之元件,為所屬技術領域中具有通常知識者所知的形式,另外,特定之實施例僅為揭示本發明使用之特定方式,其並非用以限定本發明。The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.
第1圖為本發明一實施例之靜電放電(Electrostatic Discharge,簡稱ESD)防護裝置500a的剖面示意圖。在本實施例中,靜電放電防護裝置500a可視為一閘極絕緣雙接面電晶體靜電放電防護元件(IGBT-ESD)500a。靜電放電防護裝置500a的主要元件可包括半導體基板200、磊晶層202、第一井區206、第一摻雜區208、第二摻雜區210、汲極摻雜區212、彼此相鄰的一源極摻雜區214和一第一打線摻雜區216、閘極結構224、以及的源極接觸插塞218,其中源極接觸插塞218具有可調變尺寸之延伸部分230,以改變覆蓋源極主動區的面積。在本發明之一實施例中,汲極摻雜區212可耦接至一元件操作電壓VDD,而源極摻雜區214、或源極摻雜區214及第一打線摻雜區216可耦接至一電路公共接地端電壓VSS。FIG. 1 is a cross-sectional view showing an electrostatic discharge (ESD) protection device 500a according to an embodiment of the present invention. In the present embodiment, the ESD protection device 500a can be regarded as a gate insulated double junction transistor electrostatic discharge protection component (IGBT-ESD) 500a. The main components of the ESD protection device 500a may include a semiconductor substrate 200, an epitaxial layer 202, a first well region 206, a first doped region 208, a second doped region 210, a drain doped region 212, and adjacent to each other. a source doped region 214 and a first wire doped region 216, a gate structure 224, and a source contact plug 218, wherein the source contact plug 218 has an adjustable variable size extension 230 to change Covers the area of the source active area. In one embodiment of the present invention, the drain doping region 212 can be coupled to a device operating voltage VDD, and the source doping region 214, or the source doping region 214 and the first bonding doping region 216 can be coupled. Connected to a circuit common ground terminal voltage VSS.
在本發明一實施例中,半導體基板200可為矽基板。在本發明其他實施例中,可利用鍺化矽(SiGe)、塊狀半導體(bulk semiconductor)、應變半導體(strained semiconductor)、化合物半導體(compound semiconductor),或其他常用之半導體基板。在本發明實施例中,半導體基板200可植入p型或n型不純物,以針對設計需要改變其導電類型。在本實施例中,半導體基板200具有例如為p型的一第一導電類型。一磊晶層202,位於半導體基板200上。在本實施例中,磊晶層202具有例如為p型的例如為p型的第一導電類型。在本發明實施例中,在半導體基板200和磊晶層202的一界面240上設置有一埋藏層204,其具有例如為n型的第二導電類型。在本發明其他實施例中,半導體基板200、埋藏層204和磊晶層202可分別為一絶緣層上覆矽(silicon on insulator,SOI)基板的基底、埋藏氧化層和磊晶層。In an embodiment of the invention, the semiconductor substrate 200 may be a germanium substrate. In other embodiments of the present invention, germanium telluride (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, or other commonly used semiconductor substrates may be utilized. In an embodiment of the invention, the semiconductor substrate 200 can be implanted with p-type or n-type impurities to change its conductivity type for design needs. In the present embodiment, the semiconductor substrate 200 has a first conductivity type such as a p-type. An epitaxial layer 202 is disposed on the semiconductor substrate 200. In the present embodiment, the epitaxial layer 202 has a first conductivity type such as a p-type, for example, a p-type. In an embodiment of the invention, a buried layer 204 having a second conductivity type, such as an n-type, is disposed on an interface 240 of the semiconductor substrate 200 and the epitaxial layer 202. In other embodiments of the present invention, the semiconductor substrate 200, the buried layer 204, and the epitaxial layer 202 may be a substrate of a silicon on insulator (SOI) substrate, a buried oxide layer, and an epitaxial layer, respectively.
如第1圖所示,隔離區圖案201設置於磊晶層202上,定義出一第一主動區AR1及一第二主動區AR2。在本發明一實施例中,隔離區圖案201可為淺溝槽隔離物(STI)。在本實施例中,第一主動區AR1可視為靜電放電防護裝置500a的一汲極主動區,而第二主動區AR2可視為靜電放電防護裝置500a的源極主動區。As shown in FIG. 1, the isolation region pattern 201 is disposed on the epitaxial layer 202, and defines a first active region AR1 and a second active region AR2. In an embodiment of the invention, the isolation region pattern 201 may be a shallow trench isolation (STI). In this embodiment, the first active area AR1 can be regarded as a drain active area of the electrostatic discharge protection device 500a, and the second active area AR2 can be regarded as the source active area of the electrostatic discharge protection device 500a.
如第1圖所示,第一井區206係設置於磊晶層202中,且包圍第一主動區AR1及第二主動區AR2。在本發明一實施例中,第一井區206具有例如為n型的第二導電類型,例如可視為一高壓n型井區(HVNW)。如第1圖所示,第一井區206的一底面係連接埋藏層204。As shown in FIG. 1, the first well region 206 is disposed in the epitaxial layer 202 and surrounds the first active region AR1 and the second active region AR2. In an embodiment of the invention, the first well region 206 has a second conductivity type, such as an n-type, such as a high pressure n-type well region (HVNW). As shown in FIG. 1, a bottom surface of the first well region 206 is connected to the buried layer 204.
如第1圖所示,本發明實施例之靜電放電防護裝置500a的閘極結構224係設置於隔離區圖案201上,且位於第一主動區AR1及第二主動區AR2之間。另外,閘極結構224係位於隔離區圖案201的邊界內且並未延伸至第一主動區AR1或第二主動區AR2上。在本發明實施例中,閘極結構224可由一下層之閘極絕緣層和一上層之閘極層所構成,其中閘極絕緣層可包括例如氧化物(oxide)、氮化物(nitride)、氮氧化物(oxynitride)、碳氧化物(oxycarbide)或其組合等常用的介電材料。閘極絕緣層也可包括氧化鋁(aluminum oxide;Al2O3)、氧化鉿(hafnium oxide,HfO2)、氮氧化鉿(hafnium oxynitride,HfON)、矽酸鉿(hafnium silicate,HfSiO4)、氧化鋯(zirconium oxide,ZrO2)、氮氧化鋯(zirconium oxynitride,ZrON)、矽酸鋯(zirconium silicate,ZrSiO4)、氧化釔(yttrium oxide,Y2O3)、氧化鑭(lanthalum oxide,La2O3)、氧化鈰(cerium oxide,CeO2)、氧化鈦(titanium oxide,TiO2)、氧化鉭(tantalum oxide,Ta2O5)或其組合等高介電常數(high-k,介電常數大於8)之介電材料。而閘極層可包括矽或多晶矽(polysilicon)。閘極層較佳為摻雜摻質以降低其片電阻(sheet resistance)。在其他實施例中,閘極層係包括非晶矽(amorphous silicon)。如第1圖所示,本發明實施例之第一摻雜區208和第二摻雜區210,分別設置於第一主動區AR1和第二主動區AR2中,且皆位於第一井區206上。第一摻雜區208和第二摻雜區210分別鄰近於閘極結構224的互為相反側的兩個側邊。在本發明實施例中,第一摻雜區208具有例如為n型的第二導電類型,例如可視為一n型漂移汲極摻雜區(n-type drift drain region)208,其係做為靜電放電防護裝置500a的汲極的一部分。如第1圖所示,第一摻雜區208朝閘極結構224延伸,與位於閘極結構224下之隔離區圖案201部分重疊,第一摻雜區208的垂直邊界大體上對齊閘極結構224的一側邊。在本發明實施例中,第二摻雜區210具有例如為p型的第一導電類型,例如可視為一p型主體摻雜區(p-type body region) 210,以做為靜電放電防護裝置500a的通道區(channel region)以及源極的一部分。如第1圖所示,第二摻雜區210朝閘極結構224延伸,與位於閘極結構224下之隔離區圖案201部分重疊,第二摻雜區210的垂直邊界大體上位於閘極結構224的正下方。另外,靜電放電防護裝置500a還包括設置位於第一井區206邊界上方的隔離區圖案201上的半導體環狀物222。半導體環狀物222藉由第一主動區AR1和第二主動區AR2與閘極結構224隔開,其可以增加元件的崩潰電壓(VBD)。在本發明一實施例中,半導體環狀物222與閘極結構224可為相同的材料,且可於同一製程步驟形成。在本實施例中,半導體環狀物222可為多晶矽環狀物(poly ring)。As shown in FIG. 1, the gate structure 224 of the electrostatic discharge protection device 500a of the embodiment of the present invention is disposed on the isolation region pattern 201 and located between the first active region AR1 and the second active region AR2. In addition, the gate structure 224 is located within the boundary of the isolation region pattern 201 and does not extend to the first active region AR1 or the second active region AR2. In the embodiment of the present invention, the gate structure 224 may be composed of a gate insulating layer of a lower layer and a gate layer of an upper layer, wherein the gate insulating layer may include, for example, an oxide, a nitride, and a nitrogen. Common dielectric materials such as oxynitride, oxycarbide or combinations thereof. The gate insulating layer may also include aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO 4 ), Zirconium oxide (ZrO 2 ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO 4 ), yttrium oxide (Y 2 O 3 ), lanthanum oxide (La) High dielectric constant (high-k, 2 O 3 ), cerium oxide (CeO 2 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ) or a combination thereof A dielectric material having an electrical constant greater than 8). The gate layer may include germanium or polysilicon. The gate layer is preferably doped with a dopant to reduce its sheet resistance. In other embodiments, the gate layer comprises amorphous silicon. As shown in FIG. 1 , the first doping region 208 and the second doping region 210 in the embodiment of the present invention are respectively disposed in the first active region AR1 and the second active region AR2, and are located in the first well region 206. on. The first doped region 208 and the second doped region 210 are respectively adjacent to two sides of the gate structure 224 on opposite sides of each other. In an embodiment of the invention, the first doped region 208 has a second conductivity type, such as an n-type, for example, an n-type drift drain region 208, which is A portion of the drain of the ESD protection device 500a. As shown in FIG. 1, the first doped region 208 extends toward the gate structure 224 and partially overlaps the isolation region pattern 201 under the gate structure 224. The vertical boundary of the first doped region 208 is substantially aligned with the gate structure. One side of 224. In the embodiment of the present invention, the second doping region 210 has a first conductivity type such as a p-type, for example, can be regarded as a p-type body region 210 as an electrostatic discharge protection device. The channel region of the 500a and a part of the source. As shown in FIG. 1, the second doped region 210 extends toward the gate structure 224, partially overlapping the isolation region pattern 201 under the gate structure 224, and the vertical boundary of the second doped region 210 is substantially at the gate structure. Just below 224. Additionally, the ESD protection device 500a further includes a semiconductor ring 222 disposed on the isolation pattern 201 above the boundary of the first well region 206. The semiconductor ring 222 is separated from the gate structure 224 by the first active region AR1 and the second active region AR2, which can increase the breakdown voltage (VBD) of the device. In an embodiment of the invention, the semiconductor ring 222 and the gate structure 224 may be the same material and may be formed in the same process step. In the present embodiment, the semiconductor ring 222 may be a poly ring.
如第1圖所示,本發明實施例之靜電放電防護裝置500a的汲極摻雜區212係設置於第一摻雜區208中,且汲極摻雜區212的邊界被第一摻雜區208包圍。在本發明實施例中,汲極摻雜區212具有例如為p型的第一導電類型,例如可視為p型汲極重摻雜區(p+ drain region)。汲極摻雜區212的一邊界大體上與定義出第一主動區AR1的隔離區圖案201接觸,因此汲極摻雜區212的上視面積大體上與第一主動區AR1的上視面積相等。As shown in FIG. 1, the drain doping region 212 of the ESD protection device 500a of the embodiment of the present invention is disposed in the first doping region 208, and the boundary of the drain doping region 212 is the first doping region. Surrounded by 208. In an embodiment of the invention, the drain doped region 212 has a first conductivity type, such as a p-type, for example, a p-type drain heavily doped region (p+ drain region). A boundary of the drain doping region 212 is substantially in contact with the isolation region pattern 201 defining the first active region AR1, and thus the upper viewing area of the gate doping region 212 is substantially equal to the upper viewing area of the first active region AR1. .
如第1圖所示,本發明實施例之靜電放電防護裝置500a更包括彼此相鄰的一源極摻雜區214和一第一打線摻雜區216,設置於第二摻雜區210中,且源極摻雜區214和第一打線摻雜區216的邊界被第二摻雜區210包圍。在本發明實施例中,源極摻雜區214具有例如為n型的第二導電類型,例如可視為n型源極重摻雜區(n+ source region)。另外,第一打線摻雜區216具有例如為p型的第一導電類型,例如可視為p型主體摻雜區(p-type body region) 210的第一打線摻雜區216。在本發明實施例中,第一打線摻雜區216的上視面積係設計大於源極摻雜區214的上視面積,且第一打線摻雜區216和源極摻雜區214的上視總面積大體上與第二主動區AR2的上視面積相等。如第1圖所示,第一打線摻雜區216的一邊界大體上與位於閘極結構224下之隔離區圖案201接觸。As shown in FIG. 1, the ESD protection device 500a of the embodiment of the present invention further includes a source doping region 214 and a first wire doping region 216 adjacent to each other, and is disposed in the second doping region 210. The boundary of the source doping region 214 and the first bonding doping region 216 is surrounded by the second doping region 210. In an embodiment of the invention, the source doping region 214 has a second conductivity type, such as an n-type, such as an n-source region. Additionally, the first wire doped region 216 has a first conductivity type, such as a p-type, such as a first wire doped region 216 that can be considered a p-type body region 210. In the embodiment of the present invention, the upper view area of the first wire doped region 216 is designed to be larger than the upper view area of the source doped region 214, and the top view of the first wire doped region 216 and the source doped region 214 The total area is substantially equal to the upper view area of the second active area AR2. As shown in FIG. 1, a boundary of the first wire doped region 216 is substantially in contact with the isolation region pattern 201 under the gate structure 224.
如第1圖所示,本發明實施例之靜電放電防護裝置500a的源極接觸插塞218係連接源極摻雜區214,用以將源極摻雜區214耦接至電路公共接地端電壓VSS。在本發明實施例中,源極接觸插塞218係設計具有一延伸部分230,延伸覆蓋第一打線摻雜區216。在本發明實施例中,延伸部分230具有可調變的尺寸,意即延伸部分230在如第1圖所示的剖面圖中具有可調變的長度,以使延伸部分230覆蓋第一打線摻雜區216的上視面積和第一打線摻雜區216的上視面積A比值介於0至1之間,意即延伸部分230可調變覆蓋第一打線摻雜區216的面積。在製程上可藉由調整位於第二主動區AR2之矽化物遮蔽物(silicide block)的面積,並搭配後續矽化製程,以形成不同尺寸的延伸部分230。另外,如第1圖所示,本發明實施例之靜電放電防護裝置500a的汲極接觸插塞220係連接汲極摻雜區212,用以將汲極摻雜區212耦接至元件操作電壓VDD。As shown in FIG. 1, the source contact plug 218 of the ESD protection device 500a of the embodiment of the present invention is connected to the source doping region 214 for coupling the source doping region 214 to the common ground terminal voltage of the circuit. VSS. In the embodiment of the present invention, the source contact plug 218 is designed to have an extension portion 230 extending over the first wire doped region 216. In the embodiment of the present invention, the extension portion 230 has a variable size, that is, the extension portion 230 has a variable length in the cross-sectional view as shown in FIG. 1 so that the extension portion 230 covers the first wire blending. The upper viewing area of the miscellaneous region 216 and the upper viewing area A ratio of the first bonding doping region 216 are between 0 and 1, meaning that the extension portion 230 can be adjusted to cover the area of the first bonding doping region 216. In the process, the area of the silicide block located in the second active area AR2 can be adjusted and combined with the subsequent deuteration process to form the extension portions 230 of different sizes. In addition, as shown in FIG. 1, the drain contact plug 220 of the ESD protection device 500a of the embodiment of the present invention is connected to the drain doping region 212 for coupling the gate doping region 212 to the component operating voltage. VDD.
接下來說明本發明實施例之靜電放電防護裝置500a的操作機制。請同時參考第1和2圖,第2圖為第1圖所示之靜電放電防護裝置500a的等效電路示意圖。如第1和2圖所示,例如為p型汲極重摻雜區(p+ drain region)之汲極摻雜區212和例如為n型漂移汲極摻雜區(n-type drift drain region))之第一摻雜區208構成一p-n接面二極體,且汲極摻雜區212係耦接至元件操作電壓VDD。並且,例如為n型漂移汲極摻雜區(n-type drift drain region)之第一摻雜區208、例如為高壓n型井區(HVNW)之第一井區206、例如為p型主體摻雜區(p-type body region)之第二摻雜區210、例如為n型源極重摻雜區(n+ source region)之源極摻雜區214係共同構成一寄生之n型-p型-n型接面雙載子電晶體(NPN bipolar junction transistor,以下簡稱NPN BJT),其中例如為n型漂移汲極摻雜區(n-type drift drain region)之第一摻雜區208和例如為高壓n型井區(HVNW)之第一井區206可視為上述寄生之NPN BJT的集極(collector),例如為p型主體摻雜區(p-type body region)之第二摻雜區210可視為上述寄生之NPN BJT的基極(base),且例如為n型源極重摻雜區(n+ source region)之源極摻雜區214可視為上述寄生之NPN BJT的射極(emitter),且上述寄生之NPN BJT的集極係耦接至元件操作電壓VDD,而上述寄生之NPN BJT的射極係耦接至電路公共接地端電壓VSS。另外,未被源極接觸插塞218之延伸部分230覆蓋的第一打線摻雜區216可視為一可調變寄生電阻,且上述可調變寄生電阻的兩端電性連接至NPN BJT的射極和基極兩者,意即ESD元件的陰極(cathode)端。當遭受ESD或來自元件操作電壓VDD的轟擊(zapping)時,上述寄生之NPN BJT會被觸發,會形成從元件操作電壓VDD至電路公共接地端電壓VSS的通路。因此,大量的電洞會由p型汲極摻雜區212經由例如為n型漂移汲極摻雜區(n-type drift drain region)之第一摻雜區208和例如為高壓n型井區(HVNW)之第一井區206注入於p型主體摻雜區(p-type body region)之第二摻雜區210中,再經由例如為p型摻雜區之第一打線摻雜區216之可調變寄生電阻和例如為n型源極重摻雜區(n+ source region)之源極摻雜區214將電洞導至電路公共接地端電壓VSS。由此可知,上述寄生之NPN BJT可以傳導大量的ESD暫態電流,而不會破壞受保護的內部電路。Next, the operation mechanism of the electrostatic discharge protection device 500a of the embodiment of the present invention will be described. Please refer to FIGS. 1 and 2 at the same time. FIG. 2 is an equivalent circuit diagram of the electrostatic discharge protection device 500a shown in FIG. 1. As shown in FIGS. 1 and 2, for example, a drain-doped region 212 of a p-type drain heavily doped region (p+drain region) and, for example, an n-type drift drain region The first doped region 208 constitutes a pn junction diode, and the gate doped region 212 is coupled to the component operating voltage VDD. Also, for example, a first doped region 208 of an n-type drift drain region, a first well region 206 such as a high voltage n-type well region (HVNW), such as a p-type body The second doped region 210 of the p-type body region, for example, the source doped region 214 of the n-type source region, together form a parasitic n-type-p a n-type bipolar junction transistor (NPN BJT), wherein the first doped region 208 is, for example, an n-type drift drain region For example, the first well region 206 of the high voltage n-type well region (HVNW) can be regarded as the collector of the parasitic NPN BJT, for example, the second doping of the p-type body region. The region 210 can be regarded as the base of the parasitic NPN BJT, and the source doped region 214 of, for example, an n-type source heavily doped region (n+ source region) can be regarded as the emitter of the parasitic NPN BJT ( Emitters, and the collector of the parasitic NPN BJT is coupled to the component operating voltage VDD, and the emitter of the parasitic NPN BJT is coupled to the circuit common ground terminal voltage VSS. In addition, the first wire doping region 216 not covered by the extension portion 230 of the source contact plug 218 can be regarded as a variable parasitic resistance, and both ends of the adjustable parasitic resistance are electrically connected to the NPN BJT. Both the pole and the base mean the cathode end of the ESD component. When subjected to ESD or zapping from the component operating voltage VDD, the parasitic NPN BJT is triggered to form a path from the component operating voltage VDD to the circuit common ground terminal voltage VSS. Therefore, a large number of holes will pass from the p-type drain doping region 212 via the first doping region 208, such as an n-type drift drain region, and for example, a high voltage n-well region. The first well region 206 of (HVNW) is implanted into the second doped region 210 of the p-type body region, and then via the first wire doped region 216, for example, a p-type doped region. The variable parasitic resistance and the source doping region 214, for example, an n-type source region, direct the hole to the circuit common ground terminal voltage VSS. It can be seen that the parasitic NPN BJT can conduct a large amount of ESD transient current without damaging the protected internal circuit.
藉由調整源極接觸插塞218之延伸部分230覆蓋第一打線摻雜區216的面積,以改變連接至整靜電放電防護裝置500a陰極(cathode)端的寄生電阻值,因而可以調整靜電放電防護裝置500a的裝置觸發電壓(trigger voltage)和栓鎖電壓(holding voltage)的差值。請同時參考第1至3圖,第3圖為第1圖所示之靜電放電防護裝置500a的延伸部分230覆蓋第一打線摻雜區216的面積與其對應的裝置觸發電壓和栓鎖電壓。當延伸部分230分別位於位置B0和B1時(意即延伸部分230覆蓋部分和全部的源極摻雜區214,且尚未覆蓋第一打線摻雜區216的情形),靜電放電防護裝置500a的裝置觸發電壓分別為40V和43V,栓鎖電壓分別為33V和34V。另外,當延伸部分230從位置B6調變至B1時(意即延伸部分230覆蓋第一打線摻雜區216的面積遞減的情形),會增加靜電放電防護裝置500a的寄生電阻,如第3圖所示,當降低延伸部分230覆蓋第一打線摻雜區216的面積時,本發明實施例之靜電放電防護裝置500a之觸發電壓的調降幅度會大於栓鎖電壓的調降幅度。舉例來說,當延伸部分230覆蓋第一打線摻雜區216時(延伸部分230在位置B6),靜電放電防護裝置500a之觸發電壓和栓鎖電壓分別為79V和49V;當第一打線摻雜區216完全從延伸部分230暴露出來時(延伸部分230在位置B1),靜電放電防護裝置500a之觸發電壓和栓鎖電壓分別為43V和34V。本發明實施例之靜電放電防護裝置500a係藉由調整源極接觸插塞218之延伸部分230覆蓋第一打線摻雜區216的面積,以縮小靜電放電防護裝置觸發電壓和栓鎖電壓的差值。相較於習知靜電放電防護裝置,本發明實施例之靜電放電防護裝置500a可不需堆疊方式即可提高裝置栓鎖電壓且緩和觸發電壓增加幅度。避免在元件正常操作電壓下觸發靜電放電防護裝置,發生拴鎖現象(latch-up)而損壞內部電路。因此可提升靜電放電防護裝置的性能。The area of the first wire doping region 216 is covered by adjusting the extension portion 230 of the source contact plug 218 to change the parasitic resistance value connected to the cathode end of the entire electrostatic discharge protection device 500a, thereby adjusting the electrostatic discharge protection device. The difference between the device trigger voltage of 500a and the holding voltage. Please refer to FIGS. 1 to 3 at the same time. FIG. 3 is an extension portion 230 of the ESD protection device 500a shown in FIG. 1 covering the area of the first wire doping region 216 and its corresponding device trigger voltage and latch voltage. When the extension portions 230 are respectively located at the positions B0 and B1 (that is, the extension portion 230 covers part and all of the source doping regions 214 and has not covered the first wire doping region 216), the device of the electrostatic discharge protection device 500a The trigger voltages are 40V and 43V, respectively, and the latch voltages are 33V and 34V, respectively. In addition, when the extension portion 230 is changed from the position B6 to B1 (that is, the case where the extension portion 230 covers the area where the first wire doping region 216 is decremented), the parasitic resistance of the electrostatic discharge protection device 500a is increased, as shown in FIG. As shown, when the area of the first wire doping region 216 is reduced, the amplitude of the trigger voltage of the ESD protection device 500a of the embodiment of the present invention may be greater than the amplitude of the latch voltage. For example, when the extension portion 230 covers the first wire doping region 216 (the extension portion 230 is at the position B6), the trigger voltage and the latch voltage of the ESD protection device 500a are 79V and 49V, respectively; when the first wire is doped When the region 216 is completely exposed from the extension portion 230 (the extension portion 230 is at the position B1), the trigger voltage and the latch voltage of the electrostatic discharge protection device 500a are 43V and 34V, respectively. The electrostatic discharge protection device 500a of the embodiment of the present invention covers the area of the first wire doping region 216 by adjusting the extension portion 230 of the source contact plug 218 to reduce the difference between the trigger voltage and the latch voltage of the ESD protection device. . Compared with the conventional electrostatic discharge protection device, the electrostatic discharge protection device 500a of the embodiment of the invention can increase the device latch voltage and mitigate the increase of the trigger voltage without stacking. Avoid triggering the ESD protection device under the normal operating voltage of the component, and latch-up occurs to damage the internal circuit. Therefore, the performance of the ESD protection device can be improved.
第4圖為本發明另一實施例之靜電放電防護裝置500b的剖面示意圖。第5圖為第4圖所示之靜電放電防護裝置500b的等效電路示意圖。在本實施例中,靜電放電防護裝置500b可視為一閘極接地n型金氧半電晶體靜電放電防護元件(gate grounded NMOS,GGNMOS) 500b。靜電放電防護裝置500b與靜電放電防護裝置500a的不同處為靜電放電防護裝置500b的汲極摻雜區226具有例如為n型的第二導電類型,例如可視為n型汲極重摻雜區(n+ drain region)。如第4和5圖所示,例如為n型汲極摻雜區226、例如為n型漂移汲極摻雜區(n-type drift drain region)之第一摻雜區208、例如為高壓n型井區(HVNW)之第一井區206、例如為p型主體摻雜區(p-type body region)之第二摻雜區210、例如為n型源極重摻雜區(n+ source region)之源極摻雜區214係共同構成一寄生之n型-p型-n型接面雙載子電晶體(NPN bipolar junction transistor,以下簡稱NPN BJT),其中例如為n型汲極摻雜區226、例如為n型漂移汲極摻雜區(n-type drift drain region)之第一摻雜區208和例如為高壓n型井區(HVNW)之第一井區206可視為上述寄生之NPN BJT的集極(collector),例如為p型主體摻雜區(p-type body region)之第二摻雜區210可視為上述寄生之NPN BJT的基極(base),且例如為n型源極重摻雜區(n+ source region)之源極摻雜區214可視為上述寄生之NPN BJT的射極(emitter),且上述寄生之NPN BJT的集極係耦接至元件操作電壓VDD,而上述寄生之NPN BJT的射極係耦接至電路公共接地端電壓VSS。另外,未被源極接觸插塞218之延伸部分230覆蓋的第一打線摻雜區216可視為一可調變寄生電阻,且上述可調變寄生電阻的兩端電性連接至NPN BJT的射極和基極兩者,意即ESD裝置500b的陰極(cathode)端。Fig. 4 is a cross-sectional view showing an electrostatic discharge protection device 500b according to another embodiment of the present invention. Fig. 5 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device 500b shown in Fig. 4. In the present embodiment, the ESD protection device 500b can be regarded as a gate grounded n-type metal-oxide-semiconductor electrostatic grounding protection device (gate grounded NMOS, GGNMOS) 500b. The electrostatic discharge protection device 500b differs from the electrostatic discharge protection device 500a in that the drain doping region 226 of the electrostatic discharge protection device 500b has a second conductivity type, for example, an n-type, such as an n-type drain heavily doped region ( n+ drain region). As shown in FIGS. 4 and 5, for example, an n-type drain doped region 226, such as a first doped region 208 of an n-type drift drain region, such as a high voltage n a first well region 206 of a well region (HVNW), such as a second doped region 210 of a p-type body region, such as an n-type source heavily doped region (n+ source region) The source doped regions 214 together form a parasitic n-type p-type n-type junction bipolar junction transistor (NPN BJT), wherein, for example, n-type germanium doping Region 226, a first doped region 208, such as an n-type drift drain region, and a first well region 206, such as a high voltage n-well region (HVNW), may be considered as parasitic The collector of the NPN BJT, for example, the second doped region 210 of the p-type body region may be regarded as the base of the parasitic NPN BJT, and is, for example, n-type. The source doped region 214 of the source heavily doped region (n+ source region) may be regarded as the emitter of the parasitic NPN BJT, and the collector of the parasitic NPN BJT is coupled to the component operating voltage VDD. The emitter of the parasitic NPN BJT lines coupled to the circuit common ground voltage VSS. In addition, the first wire doping region 216 not covered by the extension portion 230 of the source contact plug 218 can be regarded as a variable parasitic resistance, and both ends of the adjustable parasitic resistance are electrically connected to the NPN BJT. Both the pole and the base mean the cathode end of the ESD device 500b.
第6圖為本發明又另一實施例之靜電放電防護裝置500c的剖面示意圖。第7圖為第6圖所示之靜電放電防護裝置500c的等效電路示意圖。在本實施例中,靜電放電防護裝置500c可視為一n型矽控整流器(silicon controlled rectifier,SCR)(NSCR) 500c。靜電放電防護裝置500c的汲極摻雜區232具有例如為p型的第一導電類型,例如可視為p型汲極重摻雜區(p+ drain region)。靜電放電防護裝置500c與靜電放電防護裝置500a的不同處為,靜電放電防護裝置500a更包括一第二打線摻雜區234,設置於第一摻雜區208中,且包圍汲極摻雜區232,第二打線摻雜區234具有例如為n型的第二導電類型,例如可視為n型打線摻雜區234。在本發明另一實施例中,汲極摻雜區232和第二打線摻雜區234的位置可以互換,舉例來說,汲極摻雜區232包圍第二打線摻雜區234。如第6和7圖所示,例如為p型汲極重摻雜區(p+ drain region)之汲極摻雜區232和例如為n型打線摻雜區之第二打線摻雜區234構成一p-n接面二極體,且汲極摻雜區232係耦接至元件操作電壓VDD。並且,例如為n型漂移汲極摻雜區(n-type drift drain region)之第一摻雜區208、例如為高壓n型井區(HVNW)之第一井區206、例如為p型主體摻雜區(p-type body region)之第二摻雜區210、例如為n型源極重摻雜區(n+ source region)之源極摻雜區214係共同構成一寄生之n型-p型-n型接面雙載子電晶體(NPN bipolar junction transistor,以下簡稱NPN BJT),其中例如為n型打線摻雜區之第二打線摻雜區234、例如為n型漂移汲極摻雜區(n-type drift drain region)之第一摻雜區208和例如為高壓n型井區(HVNW)之第一井區206可視為上述寄生之NPN BJT的集極(collector),例如為p型主體摻雜區(p-type body region)之第二摻雜區210可視為上述寄生之NPN BJT的基極(base),且例如為n型源極重摻雜區(n+ source region)之源極摻雜區214可視為上述寄生之NPN BJT的射極(emitter),且上述寄生之NPN BJT的集極係耦接至元件操作電壓VDD,而上述寄生之NPN BJT的射極係耦接至電路公共接地端電壓VSS。另外,未被源極接觸插塞218之延伸部分230覆蓋的第一打線摻雜區216可視為一可調變寄生電阻,且上述可調變寄生電阻的兩端電性連接至NPN BJT的射極和基極兩者,意即ESD裝置500b的陰極(cathode)端。Figure 6 is a cross-sectional view showing an electrostatic discharge protection device 500c according to still another embodiment of the present invention. Fig. 7 is an equivalent circuit diagram of the electrostatic discharge protection device 500c shown in Fig. 6. In the present embodiment, the ESD protection device 500c can be regarded as an n-type silicon controlled rectifier (SCR) (NSCR) 500c. The drain doped region 232 of the ESD protection device 500c has a first conductivity type, such as a p-type, such as a p-drain region. The difference between the ESD protection device 500c and the ESD protection device 500a is that the ESD protection device 500a further includes a second wire doping region 234 disposed in the first doping region 208 and surrounding the gate doping region 232. The second wire doped region 234 has a second conductivity type, such as an n-type, such as an n-type wire doped region 234. In another embodiment of the present invention, the positions of the drain doping region 232 and the second bonding doping region 234 may be interchanged. For example, the drain doping region 232 surrounds the second bonding doping region 234. As shown in FIGS. 6 and 7, a gate doped region 232, such as a p-type drain heavily doped region (p+ drain region), and a second wire doped region 234, such as an n-type doped region, constitute a The pn junction diode is coupled to the component operating voltage VDD. Also, for example, a first doped region 208 of an n-type drift drain region, a first well region 206 such as a high voltage n-type well region (HVNW), such as a p-type body The second doped region 210 of the p-type body region, for example, the source doped region 214 of the n-type source region, together form a parasitic n-type-p An n-type bipolar junction transistor (NPN BJT), wherein the second wire doped region 234 is, for example, an n-type doped region, for example, an n-type drift drain doping A first doped region 208 of an n-type drift drain region and a first well region 206 such as a high voltage n-type well region (HVNW) may be considered as a collector of the parasitic NPN BJT, such as p The second doped region 210 of the p-type body region may be regarded as the base of the parasitic NPN BJT, and is, for example, an n-type source heavily doped region (n+ source region) The source doping region 214 can be regarded as the emitter of the parasitic NPN BJT, and the collector of the parasitic NPN BJT is coupled to the component operating voltage VDD, and the parasitic NPN BJT Emitter lines coupled to a common circuit ground voltage VSS. In addition, the first wire doping region 216 not covered by the extension portion 230 of the source contact plug 218 can be regarded as a variable parasitic resistance, and both ends of the adjustable parasitic resistance are electrically connected to the NPN BJT. Both the pole and the base mean the cathode end of the ESD device 500b.
類似地,本發明其他實施例之靜電放電防護裝置500b和500c係藉由調整源極接觸插塞218之延伸部分230覆蓋第一打線摻雜區216的面積,以縮小靜電放電防護裝置觸發電壓和栓鎖電壓的差值。相較於習知靜電放電防護裝置,本發明實施例之靜電放電防護裝置500b和500c可不需堆疊方式即可提高裝置栓鎖電壓且緩和觸發電壓增加幅度。避免在元件正常操作電壓下觸發靜電放電防護裝置,發生拴鎖現象(latch-up)而損壞內部電路。因此可提升靜電放電防護裝置的性能。Similarly, the ESD protection devices 500b and 500c of other embodiments of the present invention cover the area of the first wire doping region 216 by adjusting the extension portion 230 of the source contact plug 218 to reduce the trigger voltage of the ESD protection device and The difference in latch voltage. Compared with the conventional electrostatic discharge protection device, the electrostatic discharge protection devices 500b and 500c of the embodiments of the present invention can increase the device latch voltage and ease the increase of the trigger voltage without stacking. Avoid triggering the ESD protection device under the normal operating voltage of the component, and latch-up occurs to damage the internal circuit. Therefore, the performance of the ESD protection device can be improved.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.
200...半導體基板200. . . Semiconductor substrate
201...淺溝槽隔離物201. . . Shallow trench spacer
202...磊晶層202. . . Epitaxial layer
204...埋藏層204. . . Buried layer
206...第一井區206. . . First well area
208...第一摻雜區208. . . First doped region
210...第二摻雜區210. . . Second doped region
212、226、232...汲極摻雜區212, 226, 232. . . Bipolar doping zone
214...源極摻雜區214. . . Source doping region
216...第一打線摻雜區216. . . First wire doping zone
218...源極接觸插塞218. . . Source contact plug
220...汲極接觸插塞220. . . Bungee contact plug
222...半導體環狀物222. . . Semiconductor ring
224...閘極結構224. . . Gate structure
230...延伸部分230. . . Extension
234...第二打線摻雜區234. . . Second wire doping zone
240...界面240. . . interface
500a、500b、500c...靜電放電防護裝置500a, 500b, 500c. . . Electrostatic discharge protection device
VDD...元件操作電壓VDD. . . Component operating voltage
VSS...電路公共接地端電壓VSS. . . Circuit common ground voltage
A...面積A. . . area
B0、B1、B2、B3、B4、B5、B6...位置B0, B1, B2, B3, B4, B5, B6. . . position
第1圖為本發明一實施例之靜電放電防護裝置的剖面示意圖。Fig. 1 is a schematic cross-sectional view showing an electrostatic discharge protection device according to an embodiment of the present invention.
第2圖為第1圖所示之靜電放電防護裝置的等效電路示意圖。Fig. 2 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device shown in Fig. 1.
第3圖為第1圖所示之靜電放電防護裝置的延伸部分覆蓋打線摻雜區的面積與其對應的裝置觸發電壓和栓鎖電壓。Figure 3 is a diagram showing the area of the wire-doped region covered by the extended portion of the ESD protection device shown in Figure 1 and its corresponding device trigger voltage and latch voltage.
第4圖為本發明另一實施例之靜電放電防護裝置的剖面示意圖。Figure 4 is a cross-sectional view showing an electrostatic discharge protection device according to another embodiment of the present invention.
第5圖為第4圖所示之靜電放電防護裝置的等效電路示意圖。Fig. 5 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device shown in Fig. 4.
第6圖為本發明又另一實施例之靜電放電防護裝置的剖面示意圖。Figure 6 is a cross-sectional view showing an electrostatic discharge protection device according to still another embodiment of the present invention.
第7圖為第6圖所示之靜電放電防護裝置的等效電路示意圖。Fig. 7 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device shown in Fig. 6.
200...半導體基板200. . . Semiconductor substrate
201...淺溝槽隔離物201. . . Shallow trench spacer
202...磊晶層202. . . Epitaxial layer
204...埋藏層204. . . Buried layer
206...第一井區206. . . First well area
208...第一摻雜區208. . . First doped region
210...第二摻雜區210. . . Second doped region
212...汲極摻雜區212. . . Bipolar doping zone
214...源極摻雜區214. . . Source doping region
216...第一打線摻雜區216. . . First wire doping zone
218...源極接觸插塞218. . . Source contact plug
220...汲極接觸插塞220. . . Bungee contact plug
222...半導體環狀物222. . . Semiconductor ring
224...閘極結構224. . . Gate structure
230...延伸部分230. . . Extension
240...界面240. . . interface
500a...靜電放電防護裝置500a. . . Electrostatic discharge protection device
VDD...元件操作電壓VDD. . . Component operating voltage
VSS...電路公共接地端電壓VSS. . . Circuit common ground voltage
A...面積A. . . area
B0、B1、B2、B3、B4、B5、B6...位置B0, B1, B2, B3, B4, B5, B6. . . position
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TWI360874B (en) * | 2008-07-29 | 2012-03-21 | United Microelectronics Corp | Device for esd protection circuit |
TWI387106B (en) * | 2008-10-16 | 2013-02-21 | Vanguard Int Semiconduct Corp | Insulated gate bipolar transistor (igbt) electrostatic discharge (esd) protection devices |
TWI397180B (en) * | 2008-12-17 | 2013-05-21 | Vanguard Int Semiconduct Corp | Lateral diffused metal oxide semiconductor (ldmos) devices with electrostatic discharge (esd) protection capability in integrated circuit |
-
2012
- 2012-03-16 TW TW101109026A patent/TWI455275B/en active
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TWI566419B (en) * | 2015-02-04 | 2017-01-11 | 世界先進積體電路股份有限公司 | Semiconductor device |
US9646964B2 (en) | 2015-07-23 | 2017-05-09 | Vanguard International Semiconductor Corporation | Semiconductor device |
TWI575707B (en) * | 2016-02-26 | 2017-03-21 | 世界先進積體電路股份有限公司 | Semiconductor device and method of manufacturing the same |
US9831305B1 (en) | 2016-05-06 | 2017-11-28 | Vanguard International Semiconductor Corporation | Semiconductor device and method for manufacturing the same |
US11978733B2 (en) | 2021-08-05 | 2024-05-07 | Globalfoundries Singapore Pte. Ltd. | High-voltage electrostatic discharge devices |
US11942472B2 (en) | 2021-09-15 | 2024-03-26 | Globalfoundries Singapore Pte. Ltd. | High-voltage electrostatic discharge devices |
US11990466B2 (en) | 2021-10-14 | 2024-05-21 | Globalfoundries Singapore Pte. Ltd. | High voltage electrostatic devices |
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