TW202425283A - Electrostatic discharge protection device - Google Patents

Abstract

An electrostatic discharge protection device is provided and includes a semiconductor substrate, an epitaxy layer, first to third well regions, and first to sixth doped regions. The first to third well regions are disposed in the epitaxy layer. The third region well is disposed between the first well region and the second region well. The first and second doped regions are disposed above the first well region. The third and fourth doped regions are disposed above the second well region. The fifth doped region is disposed above the third well region, and the sixth doped region is disposed in the fifth doped region. The third doped region, the fifth doped region, and the sixth doped region have the same conductive type. The first and second doped regions are coupled to a pad, and the third and fourth doped regions are coupled to a ground terminal. When an electrostatic discharge even occurs on the pad, a discharge path is formed between the pad and the ground terminal.

Description

Electrostatic discharge protection device

The present invention relates to an electrostatic discharge (ESD) protection device, and in particular to a bidirectional ESD protection device.

With the development of semiconductor manufacturing process for integrated circuits, the size of semiconductor components has been reduced to the sub-micron stage to improve the performance and computing speed of integrated circuits. However, the reduction in component size has caused some reliability issues, especially the protection capability of integrated circuits against electrostatic discharge (ESD). Therefore, in this technical field, a device that can effectively provide an ESD path is needed.

The present invention provides an electrostatic discharge protection device. The electrostatic discharge protection device includes a semiconductor substrate, an epitaxial layer, a first well region, a second well region, a third well region, a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, and a sixth doped region. The semiconductor substrate has a first conductivity type. The epitaxial layer is located on the semiconductor substrate and has a first conductivity type. The first well region is arranged in the epitaxial layer and has a first conductivity type. The second well region is arranged in the epitaxial layer and has a first conductivity type. The third well region is arranged in the epitaxial layer and is located between the first well region and the second well region. The third well region has a second conductivity type opposite to the first conductivity type. The first doped region is disposed on the first well region and has the first conductivity type. The second doped region is disposed on the first well region, and the second doped region has the second conductivity type. The third doped region is disposed on the second well region and has the first conductivity type. The fourth doped region is disposed on the second well region and has the second conductivity type. The fifth doped region is disposed on the third well region and has the second conductivity type. The sixth doped region is disposed in the fifth doped region and has the second conductivity type. The first doped region and the second doped region are coupled to a bonding pad, and the third doped region and the fourth doped region are coupled to a ground terminal. When an electrostatic discharge event occurs on the bonding pad, a discharge path is formed between the bonding pad and the ground terminal.

In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, a preferred embodiment is specifically described below in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional schematic diagram of an electrostatic discharge (ESD) protection device according to an embodiment of the present invention. Referring to FIG. 1, the electrostatic discharge protection device 1 is a bidirectional electrostatic discharge protection device. When an electrostatic discharge event occurs on the bonding pad 10, the electrostatic discharge protection device 1 provides a discharge path in the direction from the bonding pad 10 to the ground terminal TGND or provides a discharge path in the direction from the ground terminal TGND to the bonding pad 10. The electrostatic discharge protection device 1 includes a semiconductor substrate 100, an epitaxial layer 101, a buried layer 102, well regions 103-106, doped regions 107-112, isolators 113-116, and gate structures 117 and 118. The doped regions 107 and 108 and the gate structure 117 are coupled to the bonding pad 10, and the doped regions 109 and 110 and the gate structure 118 are coupled to the ground terminal TGND.

In this embodiment, the semiconductor substrate 100 may be a silicon substrate. In other embodiments of the present invention, silicon germanium (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, or other commonly used semiconductor substrates may be used. In the embodiment, the semiconductor substrate 100 may be implanted with P-type or N-type dopants to change its conductivity type according to design requirements. In the embodiment of FIG. 1 , the semiconductor substrate 100 has a first conductivity type, such as a P-type.

Referring to FIG. 1 , an epitaxial layer 101 is formed on a semiconductor substrate 100. In this embodiment, the conductivity type of the epitaxial layer 101 is P type (first conductivity type). A buried layer 102 is disposed on an interface 119 between the epitaxial layer 101 and the semiconductor substrate 100. In this embodiment, the buried layer 102 has a second conductivity type, such as N type.

As shown in FIG. 1 , well regions 103 to 106 are disposed in the epitaxial layer 101. In this embodiment, the conductivity type of the well regions 103 and 104 is P-type (first conductivity type), and the conductivity type of the well regions 105 and 106 is N-type (second conductivity type). In order to clearly explain the configuration and conductivity type of the well regions 103 to 106, hereinafter, the well regions 103 and 104 are referred to as P-type well regions, and the well regions 105 and 106 are referred to as N-type well regions. Referring to FIG. 1 , the P-type well region 103 is disposed between the N-type well regions 105 and 106, and the N-type well region 106 is disposed between the P-type well regions 103 and 104. The bottom surfaces of the P-type well region 103 , the N-type well region 105 , and the N-type well region 106 are all connected to the buried layer 102 .

Referring to FIG. 1 , both doping regions 107 and 108 are disposed on the P-type well region 103. Referring to FIG. 1 , the doping region 107 is adjacent to the N-type well region 105, and the doping region 108 is adjacent to the N-type well region 106. The doping regions 107 and 108 are coupled to the bonding pad 10. In this embodiment, the conductivity type of the doping region 107 is P-type and can be used as a P-type heavily doped (P+) region, and the conductivity type of the doping region 108 is N-type and can be used as an N-type heavily doped (N+) region. In order to clearly explain the configuration and conductivity type of the doped regions 107 and 108, hereinafter, the doped region 107 is referred to as a P-type doped region, and the doped region 108 is referred to as an N-type doped region.

As shown in FIG. 1 , both doped regions 109 and 110 are disposed on the P-type well region 104. Referring to FIG. 1 , the doped region 110 is adjacent to the N-type well region 106, while the doped region 109 is away from the N-type well region 106. The doped regions 109 and 110 are coupled to the ground terminal TGND. In this embodiment, the conductivity type of the doped region 109 is P-type and can be used as a P-type heavily doped (P+) region. In addition, the conductivity type of the doped region 110 is N-type and can be used as an N-type heavily doped (N+) region. In order to clearly explain the configuration and conductivity type of the doped regions 109 and 110, hereinafter, the doped region 109 is referred to as a P-type doped region, and the doped region 110 is referred to as an N-type doped region.

Referring to FIG. 1 , the doping region 111 is disposed on the N-type well region 106. The doping region 112 is disposed in the doping region 111, and the boundary of the doping region 112 is surrounded by the doping region 111. In this embodiment, the conductivity type of the doping region 111 is N-type and can be used as an N-type doping drift (NDD) region. In addition, the conductivity type of the doping region 112 is N-type and can be used as an N-type heavily doped (N+) region. In order to clearly explain the configuration and conductivity type of the doped regions 111 and 112, hereinafter, the doped region 111 is referred to as the NDD region, and the doped region 112 is referred to as the N-type doped region. The NDD region 111 has two sidewalls W111A and W111B opposite to each other. In the embodiment of FIG. 1 , the NDD region 111 extends from the N-type well region 106 toward the P-type well region 103, so that the sidewall W111A of the NDD region 111 contacts the P-type well region 103, and at the same time, the NDD region 111 extends from the N-type well region 106 toward the P-type well region 104, so that the sidewall W111B of the NDD region 111 contacts the P-type well region 104. Therefore, it can be known that the NDD region 111 is disposed on the P-type well regions 103 and 104 and the N-type well region 106. Specifically, the NDD region 111 completely overlaps with the N-type well region 106, partially overlaps with the P-type well region 103, and partially overlaps with the P-type well region 104.

As shown in FIG. 1 , isolators 113 to 116 are disposed on the epitaxial layer 101. In this embodiment, isolators 113 to 116 may be shallow trench isolators (STI). Referring to FIG. 1 , isolator 113 completely covers the N-type well region 105 and partially covers the P-type well region 103, isolator 114 is disposed between the P-type doped region 107 and the N-type doped region 108, isolator 115 is disposed between the P-type doped region 109 and the N-type doped region 110, and isolator 116 partially covers the P-type well region 104.

Referring to FIG. 1 , gate structures 117 and 118 are disposed on P-type well regions 103 and 104, respectively. Gate structure 117 is located between N-type doped region 108 and NDD region 111, and is coupled to bonding pad 10. Gate structure 118 is located between N-type doped region 110 and NDD region 111, and is coupled to ground terminal TGND. In the embodiment of the present invention, gate structures 117 and 118 can each be composed of a lower gate insulating layer and an upper gate layer. In one embodiment, the gate insulating layer may include commonly used dielectric materials such as oxide, nitride, oxynitride, oxycarbide or a combination thereof. In other embodiments, the gate insulating layer may also include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), hafnium silicate (HfSiO ₄ ), zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO ₄ ), yttrium oxide (Y ₂ O ₃ ), lanthalum oxide (La ₂ O ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ In _one embodiment, the gate layer may include silicon or polysilicon. In other embodiments, the gate layer includes amorphous silicon.

FIG2 is a schematic diagram showing an equivalent circuit of the electrostatic discharge protection device 1. As shown in FIG2, the equivalent circuit of the electrostatic discharge protection device 1 includes equivalent elements 20-24. Referring to FIG. 1 and FIG. 2 simultaneously, the P-type doped region 107, the P-type well region 103, the N-type buried layer 102, the N-type well region 106, the P-type well region 104, and the P-type doped region 109 together constitute a P-type-N-type-P-type junction bipolar transistor (PNP bipolar junction transistor, PNP BJT) 20, wherein the P-type doped region 107 and the P-type well region 103 serve as the first collector/emitter of the PNP BJT 20, the N-type buried layer 102 and the N-type well region 106 serve as the base of the PNP BJT 20, and the P-type well region 104 and the P-type doped region 109 serve as the second collector/emitter of the PNP BJT 20. The first collector/emitter of the PNP BJT 20 is coupled to the bonding pad 10, and the second collector/emitter of the PNP BJT 20 is coupled to the ground terminal TGND. Whether the first collector/emitter and the second collector/emitter of the PNP BJT 20 are respectively the collector or the emitter depends on the polarity of the voltage caused by the electrostatic discharge event on the bonding pad 10 (positive electrostatic discharge event or negative electrostatic discharge event). Therefore, in FIG. 2, the emitter of the PNP BJT 20 under different polarities of the above voltage is represented by a solid arrow and a hollow arrow, respectively, and the details will be described later.

The N-type doped region 108, the P-type well region 103, the NDD region 111, and the N-type doped region 112 together constitute an NPN bipolar junction transistor (NPN BJT) 21, wherein the N-type doped region 108 serves as an emitter of the NPN BJT 21, the P-type well region 103 serves as a base of the NPN BJT 21, and the NDD region 111 and the N-type doped region 112 serve as a collector of the NPN BJT 21. The N-type doped region 110, the P-type well region 104, the NDD region 111, and the N-type doped region 112 together constitute the NPN BJT 22, wherein the N-type doped region 110 serves as the emitter of the NPN BJT 22, the P-type well region 103 serves as the base of the NPN BJT 22, and the NDD region 111 and the N-type doped region 112 serve as the collector of the NPN BJT 22. Referring to FIG. 2, according to the structure of FIG. 1, the emitter and base of NPN BJT 21 are coupled to bonding pad 10, the collector of NPN BJT 21, the base of PNP BJT 20, and the collector of NPN BJT 22 are commonly coupled to node N20, and the emitter and base of NPN BJT 22 are coupled to ground terminal TGND. Node N20 corresponds to the N-type buried layer 102, N-type well region 106, NDD region 111, and N-type doped region 112 whose conductivity type is N-type and connected to each other in FIG. 1.

Referring to FIG. 1 and FIG. 2 , the N-type doped region 108 , the gate structure 117 , and the N-type doped region 112 together constitute an N-type metal oxide semiconductor (NMOS) transistor 23 , wherein the N-type doped region 108 serves as a source of the NMOS transistor 23 , the gate structure 117 serves as a gate of the NMOS transistor 23 , and the N-type doped region 112 serves as a drain of the NMOS transistor 23 . The N-type doped region 110, the gate structure 118, and the N-type doped region 112 together constitute an NMOS transistor 24, wherein the N-type doped region 110 serves as the source of the NMOS transistor 24, the gate structure 118 serves as the gate of the NMOS transistor 24, and the N-type doped region 112 serves as the drain of the NMOS transistor 24. Referring to FIG. 2, according to the structure of FIG. 1, the gate and source of the NMOS transistor 23 are coupled to the bonding pad 10, the drain of the NMOS transistor 23 and the drain of the NMOS transistor 24 are coupled to the node N20, and the gate and source of the NMOS transistor 24 are coupled to the ground terminal TGND.

Referring to FIG. 1 , when an electrostatic discharge event occurs on the bonding pad 10 to induce a positive voltage (or, when a positive electrostatic discharge event occurs on the bonding pad 10 ), the bonding pad 10, the P-type doped region 107, the P-type well region 103, the NDD region 111, the N-type doped region 112, the P-type well region 104, the N-type doped region 110, and the ground terminal TGND form a discharge path, so that the electrostatic charge on the bonding pad 10 is conducted to the ground terminal TGND through the discharge path. That is, the discharge path is from the bonding pad 10 through a P-N-P-N junction and finally to the ground terminal TGND. From the perspective of the equivalent circuit of the electrostatic discharge protection device 1, referring to FIG. 2, when an electrostatic discharge event occurs on the bonding pad 10 to cause a positive voltage, the PNP BJT 20 and the NPN BJT 22 are turned on. At this time, the first collector/emitter of the PNP BJT 20 acts as an emitter (indicated by a solid arrow). The PNP BJT 20 and the NPN BJT 22 form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure in FIG. 1, the electrostatic charge on the bonding pad 10 is conducted to the ground terminal TGND via the emitter and base of the PNP BJT 20, and the collector, base, and emitter of the NPN BJT 22. In addition, the NMOS transistor 24 is turned on, so part of the electrostatic charge can also be conducted to the ground terminal TGND through the NMOS transistor 24.

Referring to FIG. 1 , when an electrostatic discharge event occurs on the bonding pad 10 to cause a negative voltage (or, when a negative electrostatic discharge event occurs on the bonding pad 10), the ground terminal TGND, the P-type doped region 109, the P-type well region 104, the NDD region 111, the N-type doped region 112, the P-type well region 103, the N-type doped region 108, and the bonding pad 10 form a discharge path, so that the charge on the ground terminal TGND is conducted to the bonding pad 10 through the discharge path. That is, the discharge path is from the ground terminal TGND through a P-N-P-N junction and finally to the bonding pad 10. From the perspective of the equivalent circuit of the electrostatic discharge protection device 1, referring to FIG. 2, when an electrostatic discharge event occurs on the bonding pad 10 to cause a negative voltage, the PNP BJT 20 and the NPN BJT 21 are turned on. At this time, the second collector/emitter of the PNP BJT 20 acts as an emitter (indicated by a hollow arrow). The PNP BJT 20 and the NPN BJT 21 form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure in FIG. 1, the charge on the ground terminal TGND is sequentially conducted to the bonding pad 10 via the emitter and base of the PNP BJT 20, the collector, base, and emitter of the NPN BJT 21. In addition, the NMOS transistor 23 is turned on, so part of the electrostatic charge can also be conducted to the ground terminal TGND through the NMOS transistor 23.

Referring to FIG. 1 , the P-type well region 103 and the NDD region 111 form a first parasitic diode, and the P-type well region 104 and the NDD region 111 form a second parasitic diode. When a positive electrostatic discharge event occurs on the bonding pad 10, the second parasitic diode is reverse biased; when a negative electrostatic discharge event occurs on the bonding pad 10, the first parasitic diode is reverse biased. Therefore, the breakdown voltage of the first parasitic diode and the second parasitic diode respectively affects the performance of the electrostatic discharge of the present invention. According to the embodiment of the present invention, the breakdown voltage of the first parasitic diode and the second parasitic diode can be changed by changing the position of the NDD region 111 relative to the N-type well region 106.

Referring to FIG. 3 , the position of the NDD region 111 relative to the N-type well region 106 is different from the embodiment shown in FIG. 1 . As shown in FIG. 3 , the NDD region 111 extends from the N-type well region 106 toward the P-type well region 104, so that the sidewall W111B of the NDD region 111 contacts the P-type well region 104, that is, the NDD region 111 extends to the top of the P-type well region 104 and partially overlaps with the P-type well region 104. The NDD region 111 does not extend to the top of the P-type well region 103. The sidewall W111A of the NDD region 111 contacts the N-type well region 106, that is, the sidewall W111A is in the N-type well region 106. Compared with FIG. 1 , the breakdown voltage of the first parasitic diode formed in the P-type well region 103 and the NDD region 111 in FIG. 3 is larger. In addition, in the embodiment of FIG. 3 , the breakdown voltage of the first parasitic diode is greater than the breakdown voltage of the second parasitic diode formed in the P-type well region 104 and the NDD region 111 , which is beneficial for triggering the formation of a discharge path when a positive electrostatic discharge event occurs on the bonding pad 10 .

In another embodiment, as shown in FIG. 4 , the NDD region 111 extends from the N-type well region 106 toward the P-type well region 103, so that the sidewall W111A of the NDD region 111 contacts the P-type well region 103, that is, the NDD region 111 extends above the P-type well region 103 and partially overlaps with the P-type well region 103. The NDD region 111 does not extend above the P-type well region 104. The sidewall W111B of the NDD region 111 contacts the N-type well region 106, that is, the sidewall W111B is in the N-type well region 106. Compared with FIG. 1 , the breakdown voltage of the second parasitic diode formed in the P-type well region 104 and the NDD region 111 in FIG. 4 is larger. In addition, in the embodiment of FIG. 4 , the breakdown voltage of the second parasitic diode is greater than the breakdown voltage of the first parasitic diode formed in the P-type well region 103 and the NDD region 111 , which is beneficial for triggering the formation of a discharge path when a negative electrostatic discharge event occurs on the bonding pad 10 .

FIG. 5 is a cross-sectional schematic diagram of an electrostatic discharge protection device according to another embodiment of the present invention. Referring to FIG. 1 and FIG. 5, the electrostatic discharge protection device 5 of FIG. 5 is different from the electrostatic discharge protection device 1 of FIG. 1 in that the electrostatic discharge protection device 5 further includes doping regions 500-502 and isolators 503-505, and the electrostatic discharge protection device 5 does not have the gate structures 117 and 118 of the electrostatic discharge protection device 1. In this embodiment, the conductivity type of each of the doping regions 500 and 501 is P-type and can be used as a P-type doping drift (PDD) region, and the conductivity type of the doping region 502 is N-type and can be used as an N-type heavily doped (N+) region. In order to clearly explain the configuration and conductivity type of the doping regions 500-502, hereinafter, the doping regions 500 and 501 are both referred to as PDD regions, and the doping region 502 is referred to as an N-type doping region.

As shown in FIG. 5 , the PDD region 500 is disposed on the P-type well region 103 and its boundary is surrounded by the P-type well region 103, and the PDD region 501 is disposed on the P-type well region 104 and its boundary is surrounded by the P-type well region 104. In this configuration, the P-type doped region 107 and the N-type doped regions 108 and 502 are disposed in the PDD region 500, and the P-type doped region 109 and the N-type doped region 110 are disposed in the PDD region 501. The N-type doped region 502 is adjacent to the N-type well region 105 and is coupled to the bonding pad 10. The P-type doped region 107 is disposed between the N-type doped regions 108 and 502.

Different from the embodiments of FIGS. 1, 3 and 4, the boundary of the NDD region 111 in FIG. 5 is surrounded by the N-type well region 106, that is, the NDD region 111 does not overlap with the P-type well regions 103 and 104. In addition, the isolators 503-505 are disposed on the epitaxial layer 101. In this embodiment, the isolators 503-505 can be shallow trench isolators (STI). The isolator 503 is disposed between the P-type doped region 107 and the N-type doped region 502 , the isolator 504 is disposed between the PDD region 500 and the NDD region 111 and partially covers the P-type well region 103 and the N-type well region 106 , and the isolator 504 is disposed between the PDD region 501 and the NDD region 111 and partially covers the P-type well region 104 and the N-type well region 106 .

FIG. 6 is a schematic diagram showing an equivalent circuit of the ESD protection device 5. According to the above, the PDD region 500 and the P-type well region 103 have the same conductivity type, and the PDD region 501 and the P-type well region 104 have the same conductivity type. Therefore, like the ESD protection circuit 1, the equivalent components of the ESD protection device 5 include the PNP BJT 20, the NPN BJT 21, and the NPN BJT 22. In the embodiment of FIG. 5, since the ESD protection device 5 does not have the gate structures 117 and 118 of the ESD protection device 1, the equivalent components of the ESD protection device 5 do not include the NMOS transistors 23 and 24.

In the embodiments of FIGS. 5 and 6 , when a positive electrostatic discharge event or a negative electrostatic discharge event occurs on the bonding pad 10, a current path is formed through a P-N-P-N junction of a silicon-controlled rectifier, similar to the embodiments of FIGS. 1 and 2 , and the description thereof is omitted here.

Similarly, the breakdown voltages of the first parasitic diode formed between the P-type well region 103 and the NDD region 111 and the second parasitic diode formed between the P-type well region 104 and the NDD region 111 can be adjusted by changing the position of the NDD region 111 relative to the N-type well region 106.

Referring to FIG. 7 , the NDD region 111 extends from the N-type well region 106 toward the P-type well region 103, so that the sidewall W111A of the NDD region 111 contacts the P-type well region 103, that is, the NDD region 111 extends above the P-type well region 103 and partially overlaps with the P-type well region 103. The NDD region 111 does not extend above the P-type well region 104. The sidewall W111B of the NDD region 111 contacts the N-type well region 106, that is, the sidewall W111B is in the N-type well region 106. Compared to FIG. 5 , in FIG. 7 , the NDD region 111 extends from the N-type well region 106 toward the P-type well region 103 , resulting in a smaller breakdown voltage of the first parasitic diode formed between the P-type well region 103 and the NDD region 111 , which is beneficial for triggering the formation of a discharge path when a negative electrostatic discharge event occurs on the bonding pad 10 .

Referring to FIG. 8 , the NDD region 111 extends from the N-type well region 106 toward the P-type well region 104, so that the sidewall W111B of the NDD region 111 contacts the P-type well region 104, that is, the NDD region 111 extends above the P-type well region 104 and partially overlaps with the P-type well region 104. The NDD region 111 does not extend above the P-type well region 103. The sidewall W111A of the NDD region 111 contacts the N-type well region 106, that is, the sidewall W111A is in the N-type well region 106. Compared to FIG. 5 , in FIG. 8 , the NDD region 111 extends from the N-type well region 106 toward the P-type well region 104 , resulting in a smaller breakdown voltage of the second parasitic diode formed between the P-type well region 104 and the NDD region 111 , which is beneficial for triggering the formation of a discharge path when a positive electrostatic discharge event occurs on the bonding pad 10 .

FIG. 9 is a cross-sectional schematic diagram of an electrostatic discharge (ESD) protection device according to another embodiment of the present invention. Referring to FIG. 9, the electrostatic discharge protection device 9 is a bidirectional electrostatic discharge protection device. When an electrostatic discharge event occurs on the bonding pad 90, the electrostatic discharge protection device 9 provides a discharge path in the direction from the bonding pad 90 to the ground terminal TGND or in the direction from the ground terminal TGND to the bonding pad 90. The electrostatic discharge protection device 9 includes a semiconductor substrate 900, an epitaxial layer 901, a buried layer 902, well regions 903-906, doped regions 907-916, and isolators 917-923. The doped regions 910-912 are coupled to the bonding pad 90, and the doped regions 913-915 are coupled to the ground terminal TGND. In this embodiment, the electrostatic discharge protection device 9 is formed by a high voltage device process.

In this embodiment, the semiconductor substrate 900 may be a silicon substrate. In other embodiments of the present invention, silicon germanium (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, or other commonly used semiconductor substrates may be used. In the embodiment, the semiconductor substrate 900 may be implanted with P-type or N-type dopants to change its conductivity type according to design requirements. In the embodiment of FIG. 9 , the semiconductor substrate 900 has a first conductivity type, such as a P-type.

Referring to FIG. 9 , an epitaxial layer 901 is formed on a semiconductor substrate 900. In this embodiment, the conductivity type of the epitaxial layer 901 is P type (first conductivity type). A buried layer 902 is disposed on an interface 924 between the epitaxial layer 901 and the semiconductor substrate 900. In this embodiment, the buried layer 902 has a second conductivity type, such as N type.

As shown in FIG. 9 , well regions 903 to 906 are disposed in the epitaxial layer 901. In this embodiment, the conductivity type of well regions 903 and 904 is P-type (first conductivity type) and serves as a high voltage P-type well region (HVPW), and the conductivity type of well regions 905 and 906 is N-type (second conductivity type) and serves as an N-type deep well region (DHVNW). In order to clearly explain the configuration and conductivity type of well regions 903 to 906, well regions 903 and 904 are referred to as high voltage P-type well regions, and well regions 905 and 906 are referred to as N-type deep well regions hereinafter. Referring to FIG. 9 , the high voltage P-type well region 903 is disposed between the N-type deep well regions 905 and 906, and the N-type deep well region 906 is disposed between the high voltage P-type well regions 903 and 904. The bottom surface of the high voltage P-type well region 903 , the bottom surface of the high voltage P-type well region 904 , the bottom surface of the N-type deep well region 905 , and the bottom surface of the N-type deep well region 906 are all connected to the buried layer 902 .

As shown in FIG. 9 , doped region 907 is disposed on high voltage P-type well region 903, doped region 908 is disposed on high voltage P-type well region 903 and N-type deep well region 906, and doped region 909 is disposed on high voltage P-type well region 904 and N-type deep well region 906. Doped regions 907 and 909 are each of P-type conductivity type and serve as P-type well regions, and doped region 908 is of N-type conductivity type and serves as N-type well region. In order to clearly explain the configuration and conductivity type of well regions 907 to 909, doped regions 907 and 909 are referred to as P-type well regions, and doped region 908 is referred to as N-type well region hereinafter. Referring to FIG. 9 , the P-type well region 907 is disposed on the high-voltage P-type well region 903 and its boundary is surrounded by the high-voltage P-type well region 903 .

The N-type well region 908 has two side walls W908A and W908B facing each other. The N-type well region 908 extends from the N-type deep well region 906 toward the high-voltage P-type well region 903, so that the side wall W111A of the N-type well region 908 contacts the high-voltage P-type well region 903, that is, the side wall W908A is in the high-voltage P-type well region 903. The side wall W908B of the N-type well region 908 contacts the N-type deep well region 906, that is, the side wall W908B is in the N-type deep well region 906. Therefore, it can be seen that the N-type well region 908 partially overlaps with the high-voltage P-type well region 903 and partially overlaps with the N-type deep well region 906.

The P-type well region 909 partially overlaps with the N-type deep well region 906, and partially overlaps with the high-voltage P-type well region 904. The P-type well region 909 has two side walls W909A and W909B facing each other. As shown in FIG. 9 , the side wall W909A of the P-type well region 909 contacts the N-type deep well region 906, that is, the side wall W909A is in the N-type deep well region 906; the side wall W909B of the P-type well region 909 contacts the high-voltage P-type well region 904, that is, the side wall W909B is in the high-voltage P-type well region 904.

As shown in FIG. 9 , doping regions 910-912 are all disposed on the P-type well region 907. Doping region 910 is adjacent to the N-type deep well region 905, doping region 912 is adjacent to the N-type well region 908, and doping region 911 is disposed between doping regions 910 and 912. Doping regions 910-912 are coupled to the bonding pad 90. In this embodiment, the conductivity type of doping region 911 is P-type and can be used as a P-type heavily doped (P+) region. In addition, the conductivity types of doping regions 910 and 912 are N-type and can be used as N-type heavily doped (N+) regions. In order to clearly explain the configuration and conductivity type of the doped regions 910-912, hereinafter, the doped region 911 is referred to as a P-type doped region, and the doped regions 910 and 912 are referred to as N-type doped regions.

Referring to FIG. 9 , the doping region 916 is disposed on the N-type well region 908. In this embodiment, the conductivity type of the doping region 916 is N-type and can be used as an N-type heavily doped (N+) region. In order to clearly explain the configuration and conductivity type of the doping region 916, the doping region 916 is referred to as an N-type doping region hereinafter.

As shown in FIG. 9 , both doped regions 913 and 914 are disposed on the P-type well region 909. The doped region 913 is adjacent to the N-type deep well region 906, and the doped region 914 is adjacent to the high voltage P-type well region 904. The doped regions 913 and 914 are coupled to the ground terminal TGND. In this embodiment, the conductivity type of the doped region 913 is P-type and can be used as a P-type heavily doped (P+) region, and the conductivity type of the doped region 914 is N-type and can be used as an N-type heavily doped (N+) region. In order to clearly explain the configuration and conductivity type of the doping regions 913 and 914, hereinafter, the doping region 913 is referred to as a P-type doping region, and the doping region 914 is referred to as an N-type doping region.

The doped region 915 is disposed on the high voltage P-type well region 904 and coupled to the ground terminal TGND. In this embodiment, the conductivity type of the doped region 914 is P-type and can be used as a P-type heavily doped (P+) region.

Referring to FIG. 9 , isolators 917 to 923 are disposed on the epitaxial layer 901. In this embodiment, isolators 917 to 923 may be shallow trench isolators (STI). Referring to FIG. 9 , isolator 917 completely covers the N-type deep well region 905 and partially covers the high voltage P-type well region 903, isolator 918 is disposed between the N-type doped region 910 and the P-type doped region 911, isolator 919 is disposed between the P-type doped region 911 and the N-type doped region 912, and isolator 920 is disposed between the N-type doped region 912 and the N-type doped region 916. In addition, the isolator 921 is disposed between the N-type doped region 916 and the P-type doped region 913 , the isolator 922 is disposed between the N-type doped region 914 and the P-type doped region 915 , and the isolator 923 partially covers the high voltage P-type well region 904 .

In the embodiment of FIG. 9 , the equivalent circuit of the electrostatic discharge protection device 9 includes the equivalent elements 20 to 24 shown in FIG. 6 . Referring to FIG. 9 and FIG. 6 simultaneously, the P-type doped region 911, the P-type well region 907, the high voltage P-type well region 903, the N-type buried layer 902, the N-type deep well region 906, the P-type well region 909, and the P-type doped region 913 together constitute the PNP BJT 20, wherein the P-type doped region 911, the P-type well region 907, and the high voltage P-type well region 903 serve as the first collector/emitter of the PNP BJT 20, the N-type buried layer 902 and the N-type deep well region 906 serve as the base of the PNP BJT 20, and the P-type well region 909 and the P-type doped region 913 serve as the second collector/emitter of the PNP BJT 20. A first collector/emitter of the PNP BJT 20 is coupled to the bonding pad 90 , and a second collector/emitter of the PNP BJT 20 is coupled to the ground terminal TGND.

The N-type doped region 912, the P-type well region 907, the high voltage P-type well region 903, the N-type well region 908, and the N-type doped region 916 together constitute the NPN BJT 21, wherein the N-type doped region 912 serves as the emitter of the NPN BJT 21, the P-type well region 907 and the high voltage P-type well region 903 serve as the base of the NPN BJT 21, and the N-type well region 908 and the N-type doped region 916 serve as the collector of the NPN BJT 21. The N-type doped region 914, the P-type well region 909, the N-type deep well region 906, the N-type well region 908, and the N-type doped region 916 together constitute the NPN BJT 22, wherein the N-type doped region 914 serves as the emitter of the NPN BJT 22, the P-type well region 909 serves as the base of the NPN BJT 22, and the N-type deep well region 906, the N-type well region 908, and the N-type doped region 916 serve as the collector of the NPN BJT 22. Referring to FIG. 6 , according to the structure of FIG. 9 , the emitter and base of NPN BJT 21 are coupled to bonding pad 90, the collector of NPN BJT 21, the base of PNP BJT 20, and the collector of NPN BJT 22 are commonly coupled to node N20, and the emitter and base of NPN BJT 22 are coupled to ground terminal TGND. Node N20 corresponds to N-type buried layer 902, N-type deep well region 906, N-type well region 908, and N-type doped region 916, which are N-type conductive types and connected to each other in FIG. 9 .

Referring to FIG. 9 , when an electrostatic discharge event occurs on the bonding pad 90 to induce a positive voltage (or, when a positive electrostatic discharge event occurs on the bonding pad 10 ), the bonding pad 90, the P-type doped region 911, the P-type well region 907, the high voltage P-type well region 903, the N-type well region 908, the N-type deep well region 906, the P-type well region 909, the N-type doped region 914, and the ground terminal TGND form a discharge path, so that the electrostatic charge on the bonding pad 90 is conducted to the ground terminal TGND through the discharge path. That is, the discharge path is from the bonding pad 90 through a P-N-P-N junction and finally to the ground terminal TGND. From the perspective of the equivalent circuit of the electrostatic discharge protection device 9, referring to FIG. 9, when an electrostatic discharge event occurs on the bonding pad 90 to cause a positive voltage, the PNP BJT 20 and the NPN BJT 22 are turned on. At this time, the first collector/emitter of the PNP BJT 20 acts as an emitter (indicated by a solid arrow). The PNP BJT 20 and the NPN BJT 22 form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure in FIG. 9, the electrostatic charge on the bonding pad 90 is conducted to the ground terminal TGND via the emitter and base of the PNP BJT 20, and the collector, base, and emitter of the NPN BJT 22.

Referring to FIG. 9 , when an electrostatic discharge event occurs on the bonding pad 90 to cause a negative voltage (or, when a negative electrostatic discharge event occurs on the bonding pad 90 ), the ground terminal TGND, the P-type doped region 913, the P-type well region 909, the N-type deep well region 906, the N-type well region 908, the high voltage P-type well region 903, the P-type well region 907, the N-type doped region 912, and the bonding pad 90 form a discharge path, so that the charge on the ground terminal TGND is conducted to the bonding pad 90 through the discharge path. That is, the discharge path is from the ground terminal TGND through a P-N-P-N junction and finally to the bonding pad 10. . From the perspective of the equivalent circuit of the electrostatic discharge protection device 9, referring to FIG. 6, when an electrostatic discharge event occurs on the bonding pad 90 to cause a negative voltage, the PNP BJT 20 and the NPN BJT 21 are turned on. At this time, the second collector/emitter of the PNP BJT 20 acts as an emitter (indicated by a hollow arrow). The PNP BJT 20 and the NPN BJT 21 form a silicon controlled rectifier (SCR). Corresponding to the discharge path on the semiconductor structure in FIG. 1, the charge on the ground terminal TGND is sequentially conducted to the bonding pad 90 via the emitter and base of the PNP BJT 20, the collector, base, and emitter of the NPN BJT 21.

Referring to FIG. 9 , the high voltage P-type well region 903 and the N-type well region 908 form a third parasitic diode, and the P-type well region 909 and the N-type well region 908 form a fourth parasitic diode. The breakdown voltage of each of the third parasitic diode and the fourth parasitic diode can be changed by changing the position of the N-type well region 908 relative to the N-type deep well region 906.

Referring to FIG. 10 , the boundary of the N-type well region 908 is surrounded by the N-type deep well region 906. The sidewalls W908A and W908B of the N-type well region 908 both contact the N-type deep well region 906, that is, the sidewalls W908A and W908B are both in the N-type deep well region 906. Therefore, the N-type well region 908 does not overlap with the N-type well region 908. Compared with FIG. 9 , the breakdown voltage of the third parasitic diode formed in the high voltage P-type well region 903 and the N-type well region 908 in FIG. 10 is larger. In addition, in the embodiment of FIG. 10 , the breakdown voltage of the third parasitic diode is greater than the breakdown voltage of the fourth parasitic diode formed in the P-type well region 909 and the N-type well region 908 , which is beneficial for triggering the formation of a discharge path when a positive electrostatic discharge event occurs on the bonding pad 90 .

Referring to FIG. 11, the boundary of the P-type well region 909 is surrounded by the high voltage P-type well region 904. The sidewalls W909A and W909B of the P-type well region 909 both contact the high voltage P-type well region 904, that is, the sidewalls W909A and W909B are both in the high voltage P-type well region 904. Therefore, the P-type well region 909 does not overlap with the N-type deep well region 906. Compared with FIG. 9, the breakdown voltage of the fourth parasitic diode formed in the P-type well region 909 and the N-type well region 908 in FIG. 11 is larger. In addition, in the embodiment of FIG. 11 , the breakdown voltage of the fourth parasitic diode is greater than the breakdown voltage of the third parasitic diode formed in the high voltage P-type well region 903 and the N-type well region 908 , which is beneficial for triggering the formation of a discharge path when a negative electrostatic discharge event occurs on the bonding pad 90 .

According to the above embodiments, the electrostatic discharge protection device 1 (or electrostatic discharge protection device 5, or electrostatic discharge protection device 9) provided in this case provides a bidirectional discharge path. When a positive electrostatic discharge event or a negative electrostatic discharge event occurs on the bonding pad 10 (or bonding pad 90), a current path formed by a P-N-P-N junction of a silicon-controlled rectifier is provided to quickly discharge the current.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

1, 5, 9: ESD protection device 10: Bonding pad 20: P-type-N-type-P-type junction bipolar transistor (PNP BJT) 21, 22: N-type-P-type-N-type junction bipolar transistor (NPN BJT) 23, 24: NMOS transistor 90: Bonding pad 100: Semiconductor substrate 101: Epitaxial layer 102: Buried layer 103~106: Well region 107~112: Doped region 113~116: Isolator 117, 118: Gate structure 119: Interface 500~502: Doped region 503~505: Isolator 900: Semiconductor substrate 901: Epitaxial layer 902: Buried layer 903~906: Well area 907~916: Doped area 917~923: Isolator 924: Interface N20: Node TGND: Ground terminal W111A, W111B: Sidewall W908A, W908B: Sidewall W909A, W909B: Sidewall

FIG. 1 is a schematic cross-sectional view of an electrostatic discharge (ESD) protection device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an equivalent circuit of an electrostatic discharge protection device according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of an electrostatic discharge protection device according to an embodiment of the present invention. FIG. 6 is a schematic diagram of an equivalent circuit of an electrostatic discharge protection device according to another embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of an electrostatic discharge protection device according to an embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of an electrostatic discharge protection device according to another embodiment of the present invention.

1: Electrostatic discharge protection device

10:Joint pad

100:Semiconductor substrate

101: Epitaxial layer

102: Buried layer

103~106: Well area

107~112: Mixed area

113~116: Isolation

117,118: Gate structure

119: Interface

TGND: ground terminal

W111A, W111B: Side wall

Claims (21)

An electrostatic discharge protection device includes: A semiconductor substrate having a first conductivity type; An epitaxial layer located on the semiconductor substrate, wherein the epitaxial layer has the first conductivity type; A first well region arranged in the epitaxial layer, wherein the first well region has the first conductivity type; A second well region arranged in the epitaxial layer, wherein the second well region has the first conductivity type; A third well region arranged in the epitaxial layer and located between the first well region and the second well region, wherein the third well region has a second conductivity type opposite to the first conductivity type; A first doped region arranged on the first well region, wherein the first doped region has the first conductivity type; A second doped region is disposed on the first well region, wherein the second doped region has the second conductivity type; A third doped region is disposed on the second well region, wherein the third doped region has the first conductivity type; A fourth doped region is disposed on the second well region, wherein the fourth doped region has the second conductivity type; A fifth doped region is disposed on the third well region, wherein the fifth doped region has the second conductivity type; A sixth doped region is disposed in the fifth doped region, wherein the sixth doped region has the second conductivity type; Wherein, the first doped region and the second doped region are coupled to a bonding pad, and the third doped region and the fourth doped region are coupled to a ground terminal; and Wherein, when an electrostatic discharge event occurs on the bonding pad, a discharge path is formed between the bonding pad and the ground terminal. The electrostatic discharge protection device of claim 1 further includes: a first gate structure disposed on the first well region and between the second doped region and the fifth doped region; and a second gate structure disposed on the second well region and between the fifth doped region and the fourth doped region; wherein the first gate structure is coupled to the bonding pad, and the second gate structure is coupled to the ground terminal. As in claim 2, the electrostatic discharge protection device, wherein the fifth doped region extends toward the first well region and the second well region and contacts the first well region and the second well region. The electrostatic discharge protection device of claim 2, wherein: the fifth doped region has a first sidewall and a second sidewall opposite to the first sidewall; the first sidewall of the fifth doped region contacts the third well region; and the fifth doped region extends toward the second well region, and the second sidewall of the fifth doped region contacts the second well region. The electrostatic discharge protection device of claim 2, wherein: the fifth doped region has a first side wall and a second side wall opposite to the first side wall; the fifth doped region extends toward the first well region, and the first side wall of the fifth doped region contacts the first well region; and the second side wall of the fifth doped region contacts the third well region. The electrostatic discharge protection device of claim 2 further includes: A buried layer located on an interface between the semiconductor substrate and the epitaxial layer and connected to a bottom surface of the first well region and a bottom surface of the third well region; Wherein, the buried layer has the second conductivity type. The electrostatic discharge protection device of claim 6 further comprises: A fourth well region disposed in the epitaxial layer; Wherein the fourth well region has the second conductivity type; and Wherein the first well region is disposed between the third well region and the fourth well region, and the buried layer is further connected to a bottom surface of the fourth well region. The electrostatic discharge protection device of claim 1, further comprising: a seventh doping region disposed on the first well region, wherein the seventh doping region has the first conductivity type; and an eighth doping region disposed on the second well region, wherein the eighth doping region has the first conductivity type; wherein the first doping region and the second doping region are disposed in the seventh doping region, and the third doping region and the fourth doping region are disposed in the eighth doping region. An electrostatic discharge protection device as claimed in claim 8, wherein a boundary of the fifth doped region is surrounded by the third well region. An electrostatic discharge protection device as claimed in claim 9, wherein a boundary of the eighth doped region is surrounded by the second well region. As in claim 9, the electrostatic discharge protection device, wherein the eighth doped region is further disposed on the third well region. The electrostatic discharge protection device of claim 8, wherein: the fifth doped region has a first sidewall and a second sidewall opposite to the first sidewall; the first sidewall of the fifth doped region contacts the third well region; and the fifth doped region extends toward the second well region, and the second sidewall of the fifth doped region contacts the second well region. The electrostatic discharge protection device of claim 8, wherein: the fifth doped region has a first side wall and a second side wall opposite to the first side wall; the fifth doped region extends toward the first well region, and the first side wall of the fifth doped region contacts the first well region; and the second side wall of the fifth doped region contacts the third well region. An electrostatic discharge protection device as claimed in claim 13, wherein a boundary of the eighth doped region is surrounded by the second well region. The electrostatic discharge protection device of claim 13, wherein the eighth doped region is further disposed on the third well region. The electrostatic discharge protection device of claim 8, wherein the second doped region and the sixth doped region are separated by a first isolator, and the fourth doped region and the sixth doped region are separated by a second isolator. The electrostatic discharge protection device of claim 8 further comprises: A ninth doping region disposed in the seventh doping region and coupled to the bonding pad; wherein the ninth doping region has the second conductivity type, and the first doping region is located between the ninth doping region and the second doping region. The electrostatic discharge protection device of claim 8 further includes: a ninth doping region disposed in the seventh doping region and coupled to the bonding pad, wherein the ninth doping region has the second conductivity type, and the first doping region is located between the ninth doping region and the second doping region; a tenth doping region disposed in the second well region and coupled to the ground terminal, wherein the tenth doping region has the first conductivity type, and the fourth doping region is located between the third doping region and the tenth doping region. The electrostatic discharge protection device of claim 8 further includes: A buried layer located on an interface between the semiconductor substrate and the epitaxial layer and connected to a bottom surface of the first well region and a bottom surface of the third well region; Wherein, the buried layer has the second conductivity type. The electrostatic discharge protection device of claim 19 further comprises: a fourth well region disposed in the epitaxial layer; wherein the fourth well region has the second conductivity type; and wherein the first well region is disposed between the third well region and the fourth well region, and the buried layer is further connected to a bottom surface of the fourth well region. As in claim 20, the electrostatic discharge protection device, wherein the buried layer is further connected to a bottom surface of the second well region.

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