TWI509768B - Esd protection circuit - Google Patents

Description

Electrostatic discharge protection circuit

The present invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit having low leakage current.

Protecting components from electrostatic discharge has been a challenge for those skilled in the art. Conventional ESD protection circuits mainly include a diode-coupled end electrically coupled to the input-in pad and the other end connected to the ground. Used to dissipate high current through the circuit. In general, the diode junction has a well opposite to the substrate for receiving the two ends of the diode. However, one end of the diode and the well and the substrate form a parasitic bipolar transistor (BJT). It becomes a leakage path that is undesired during normal operation, for example, when a voltage of 10 volts is applied to the input pad, and thus the power consumption caused by the electrostatic discharge protection circuit becomes a major disadvantage.

In addition to leakage, the challenge for traditional ESD protection circuit design is to gradually reduce the layout area. Due to the pursuit of small-sized electronic components, the limitations of circuit designers are gradually reduced, in addition to protecting the input pads. The electrostatic discharge is also necessary for the reverse negative voltage electrostatic discharge, so it is usually necessary to reserve an additional area for adding an antistatic discharge to dissipate the negative voltage. However, the sacrificed area will reduce the density of the transistor.

Therefore, how to avoid unnecessary leakage current from the electrostatic discharge protection circuit and how to design a negative electrostatic discharge under the minimum area It is an important issue.

The object of the present invention is to provide an electrostatic discharge protection circuit having a well embedded in a substrate having a conductivity type opposite to that of the substrate, and the well surrounding the diode To dissipate the electrostatic discharge current. In addition, a doped region is formed in the well and electrically coupled to an input pad. One end of the diode is also electrically coupled to the input pad at the same time, so that a potential barrier can be formed to prevent leakage current from the diode. The body flows into the well. Further, the well and the substrate form an additional channel for dissipating the electrostatic discharge current from the ground terminal, and therefore, the area required for designing an electrostatic discharge for negative pressure can be reduced.

In order to achieve the above object, the present invention can be electrically coupled to an input (or input/output) pad by providing an electrostatic discharge protection circuit, and the circuit can include a first component which can be a PNP BJT, having an emitter electrical coupling. Connect to the input pad. The protection circuit can also have a second component, such as a diode, the first pole of the second component being electrically coupled to the emitter of the first component and the input pad. The second component can also be a diode bond, and a second pole is electrically coupled to the ground. The circuit may further have a third component, one end of which is electrically coupled to the input pad, the other end is electrically coupled to the ground, and the third component may be represented by a diode, and the third component is The second element is in the opposite direction. The protection circuit can further include a fourth component having a grounded gate NMOS structure, one end of the NMOS structure being electrically coupled to the second pole of the second component and the other end being coupled to ground.

In order to achieve the above object, the present invention can be electrically coupled to an input (or input/output) pad by providing an electrostatic discharge protection circuit, the circuit comprising a substrate having a first conductivity type, and a second conductivity in the substrate. A first well of the type, and a second well having a first conductivity type in the first well. The protection circuit further has a third doped region of N+ in the first well electrically coupled to the input pad, and is electrically coupled to the ground via a fourth doped region having a P+ in the substrate. Embodiments may have more than one second well located in the first well and arranged after the first second well. Each of the second wells has a first end and a second end, wherein the first end of the first second well is electrically coupled to the input pad, and the second end is electrically coupled to the first end of the subsequent second well, and The second well is arranged in the succeeding connection, and the last second well is electrically coupled to the ground.

The invention is described more fully hereinafter with reference to the embodiments of the invention and the accompanying drawings. The various exemplifications set forth herein are intended to be considered as a contin The word "or" used in the specification is a connection term, but is "and/or". In addition, the article "a" can be regarded as singular or plural. The term "coupled" or "connected" may mean that the elements are connected directly or indirectly through other elements.

1 is a diagram showing an equivalent circuit diagram of an electrostatic discharge protection circuit 10 in accordance with an embodiment of the present disclosure. The circuit 10 can be added A semiconductor circuit is electrically coupled to an input pad (or input/output pad) 110, an internal circuit 120, and a ground 130, so that the internal circuit 120 can be protected from electrostatic discharge or other electrical discharge. The circuit 10 includes at least a first component 101. The first component 101 can be, but is not limited to, a PNP BJT having an emitter electrically coupled to the input pad 110. The circuit 10 can also have a second component 102, which can be exemplified as a diode. The first pole of the second component 102 is electrically coupled to the emitter of the first component 101 and the input pad 110. The second component 102 can also be a diode bond 102' as shown in FIG. 1 and has a second pole 1022' electrically coupled to the ground. The circuit 10 can further have a third component 103 having one end 1032 electrically coupled to the input pad 110 and the other end 1031 electrically coupled to the ground terminal. The third component 103 can be selectively represented by a diode. The circuit 10 can further include a fourth component 104 having a grounded gate NMOS structure, one end of the NMOS structure being electrically coupled to the second pole 1022 of the second component 102 and the other end being coupled to ground. In this embodiment, if an electrostatic discharge current is introduced into the input pad 110, the discharge path of the electrostatic discharge current will flow from the second component 102 to the fourth component 104, and then from the fourth component 104 to the ground terminal 130. Conversely, if the electrostatic discharge current is introduced from the ground terminal 130, the discharge path of the electrostatic discharge current will flow from the ground terminal 130 to the third component 103, and then from the third component 103 to the input pad 110. Thus, this embodiment provides a primary discharge path for at least two electrostatic discharge currents, one for inflow from input pad 110 and one for inflow from ground terminal 130, the latter commonly referred to as negative stress electrostatic discharge. Another object of the present embodiment is to reduce the leakage current of the internal circuit 120 under normal operation, and a bias voltage, such as 10.5 volts, is applied to the input pad 110 during normal operation to drive the internal circuit 120, thus for self-coupling Electrostatic discharge protection The leakage current flowing out of the protection circuit 10 should be avoided or reduced. However, if the first element 101 is not properly designed, it may become a main leakage path. In the present embodiment, since the first element 101 is designed to apply a bias voltage to the input pad 110 as shown in FIG. 1, it can be in a cut-off state (two for the PNP BJT shown for the first element 101). For the PN interface, both are reverse biased or zero biased, so the path from the input pad 110 to the ground terminal 130 can be cut off to prevent leakage current generation.

2 depicts a semiconductor structure of an electrostatic discharge protection circuit 20 in accordance with another embodiment of the present disclosure. The ESD protection circuit 20 is electrically coupled to an input pad 110 for input and output or a high voltage input pad. The ESD protection circuit 20 includes a substrate 100 of a first conductivity type, and a substrate 100 is disposed in the substrate 100. And having a first well 200 of a second conductivity type, and a second well 210 located in the first well 200 and having a first conductivity type. In this embodiment, the first conductivity type is a P-type, the first well 200 is an N-type well, and the second well 210 is a P-type well. The protection circuit 20 has a diode junction 220 including at least one diode element 225, an N+ first doping region 240 in the first well 200 and electrically coupled to the input pad 110, and a substrate 100 The second doped region 290 is electrically coupled to the ground terminal 130. In the present embodiment, the substrate 100 is P-type, and the diode element 225 is the first diode of the diode junction 220. The first end 222 is electrically coupled to the input pad 110. In this embodiment, the first end 222 is a second end 222. The first end 222 is electrically coupled to the input pad 110. In this embodiment, the first end 222 is A P+ zone, the second end 224 is an N+ zone.

The contact surface of the substrate 100 and the first well 200 additionally forms a diode The diode is opposite to the direction of the diode junction 220 from the perspective of the input pad 110 (the diode junction 220 is P-N, N-P is described herein).

In this embodiment, a main discharge path of at least two electrostatic discharge currents is provided to dissipate the electrostatic discharge currents from different directions. When an electrostatic discharge current is introduced from the input pad 110, it may be referred to as forward electrostatic discharge, electrostatic discharge. The discharge path of the current will be connected from the diode 220 to the ground terminal 130. On the other hand, if the electrostatic discharge current is introduced from the ground terminal 130, referred to herein as a negative voltage electrostatic discharge, the discharge path of the electrostatic discharge current will flow from the substrate 100, through the N+ first doping region 240, to the input pad 110. . Therefore, the present embodiment provides a main discharge path of at least two electrostatic discharge currents, one for flowing from the input pad 110 and one for flowing from the ground terminal 130, the latter being commonly referred to as a negative stress type electrostatic discharge. . The present invention embeds the first well 200 in the substrate 100 of opposite conductivity type and surrounds the diode junction 220, so that it is not necessary to additionally reserve an extra area to accommodate a negative voltage type electrostatic current discharge. Diode.

Another feature of the present disclosure is that leakage current from the diode junction 220 to the ground terminal 130 during normal operation can be reduced. In normal operation, a bias voltage is applied to the input pad 110 to drive the internal circuitry. Ideally, the protection circuit 20 electrically coupled to the input pad 110 should be non-conducting to avoid power consumption, but unfortunately, the diode is coupled. The first end 222 of the 220 and the first well 200 and the substrate 100 can form a path of leakage current. Therefore, the N+ doping region 240 is electrically coupled to the input pad 110, and the potential difference between the P well 210 and the N well 200 interface can form a barrier to prevent leakage current from the P well 210 from entering the N well. 200. For the first diode 225 in the diode junction 220, the potential between the P well 210 and the N well 200 is comparable, but for the second of the diode junction 220 that is second to the other subsequent connections In fact, the difference in potential between the P well 210 and the N well 200 may cause a larger potential difference from each other due to the series voltage drop, and thus a larger barrier is formed outside the dipole. Additionally, by adjusting the doping concentration or profile in each well, this embodiment can provide a larger barrier to reduce leakage current. 3 shows another embodiment having an impedance 270 between the first end 222 of the diode 225 and the input pad 110 to provide a large voltage drop across the diode terminal to reduce leakage current.

Referring to FIG. 2, the present embodiment further has a metal oxide semiconductor structure 280 (hereinafter referred to as a MOS structure) disposed between the ground terminal 130 and the diode junction 220. The structure includes a substrate 100 having a a third well 281 of a conductivity type, a third doped region 286 having a second conductivity type in the third well 281, and a fourth doped region 287 having a second conductivity type in the third well 281, and A gate 288 between the third doped region 286 and the fourth doped region 287. The third doped region 286 is electrically coupled to the second end 224 of the diode element 225 , and the fourth doped region 287 is electrically coupled to the second doped region 290 . The gate 288 is electrically coupled to the ground terminal 130 and can be commonly grounded to the fourth doping region 287. The MOS structure 280 can further include a second gate 289 between the gate 288 and the third doped region 286. The second gate 289 can be selectively coupled to the Vdd as needed.

4 illustrates an embodiment having a guard ring structure 300 between the diode junction 220 and the second doped region 290. The guard ring structure 300 can also be disposed between the diode junction 220 and the MOS structure 280. between. Protection ring structure 300 There is a fourth well 310, a fifth doped region 320 in the fourth well 310, and a sixth doped region 340 in the substrate 100. In the present embodiment, the fourth well 310 is an N-type well and the fifth doped region 320 is an N+ doped region. The fifth doped region can be electrically coupled to the voltage of Vdd to capture electrons flowing in the substrate 100. The sixth doped region 340 can be a P+ doped region and electrically coupled to the ground terminal 130 for capturing on the substrate. A positive charge flowing in 100 is a hole.

5 illustrates another embodiment, an ESD protection circuit 30 includes at least a substrate 100 having a first conductivity type, a first well 200 having a second conductivity type in the substrate 100, and a first well 200 A second well 210 having a first conductivity type. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. In the second well 210, there is also a P-type first doped region 222 and an N-type second doped region 224, wherein the first doped region 222 is electrically coupled to the input pad 110. Further, in the first well 200, there is an N+ third doping region 240, and in the substrate 100, there is a P+ fourth doping region 290, and the N+ third doping region 240 is electrically coupled to the input pad 110 and P+ The fourth doped region 290 is electrically coupled to the ground terminal 130. As illustrated in the specification, embodiments may have more than one second well 210 located in the first well 200 and arranged after the first second well 210. Each of the second wells 210 has its corresponding P-type first doped region 222 and N-type second doped region 224, and is connected in series as shown in FIG. For an embodiment having only one second well 210, the N-type second doped region 224 is electrically coupled to the ground terminal 130, and for a series connected second well 210, the rightmost second well 210 is The second doped region 224 of the N-type is electrically coupled to the ground terminal 130. The second well 210, the first doped region 222 and the second doped region 224 form a first diode 225, wherein the first doped region 222 is the first diode 225 The first end, the second doped region 224 is the second end of the first diode 225. The fourth doped region 290 of P+, the substrate 100, the first well 200 and the third doped region 240 of N+ form a second diode, wherein the fourth doped region 290 of P+ is the second diode The first end of the N+ and the third doped region 240 of N+ are the second ends of the second diode.

This embodiment provides a main discharge path of two electrostatic discharge currents to dissipate the electrostatic discharge current, wherein one channel is introduced from the input pad 110, to the first doping region 222, to the second well 210, and then to the first The second doped region 224 is finally connected to the ground terminal 130. The other channel is from the fourth doped region 290 to the substrate 100, to the first well 200 and the third doped region 240, and finally to the input pad 110. The second type of channel is also referred to as a negative stress type electrostatic discharge channel for distinguishing it from the electrostatic discharge channel introduced from the input pad 110.

Since the first well 200 surrounds the second well 210, and the third doping region 240 and the first doping region 222 are electrically coupled to the input pad 110, when a bias is applied to the input pad 110, The junction of a well 200 with the second well 210 does not produce a forward bias. Therefore, the leakage current flowing from the second well 210 to the first well 200 will be greatly reduced. In another embodiment shown in FIG. 6, an impedance 270 may be further added between the first doping region 222 and the input pad 110 to have a larger interface on the first well 200 and the second well 210. The pressure differential, and thus a greater potential difference, can prevent leakage current from flowing from the second well 210 to the first well 200.

The embodiment may further have a third well 281 having a P-type in the substrate 100, and a fifth doping region 286 having an N-type in the third well 281, and A sixth doped region 287 having an N-type in the third well 281. The fifth doped region 286 is electrically coupled to the second doped region 224 and the sixth doped region 287 is electrically coupled to the fourth doped region 290 . A gate 288 between the fifth and sixth doped regions is electrically coupled to the ground terminal 130. The embodiment may further include another gate 289 between the gate 288 and the fifth doping region 286, wherein the gate 289 is electrically coupled to Vdd.

FIG. 7 depicts another embodiment further having an N-type fourth well 310 in the substrate 100 and a fourth well 310 interposed between the N+ second doped region 224 and the P+ fourth doped region 290, also in this embodiment. A seventh doped region 320 having an N-type in the fourth well 310 and an eighth doped region 340 having a P-type in the substrate 100, wherein the eighth doped region 340 is interposed Between the second doped region 224 and the fourth doped region 290, or between the second doped region 224 and the fifth doped region 286.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

10‧‧‧Electrostatic discharge protection circuit

20‧‧‧Electrostatic discharge protection circuit

30‧‧‧Electrostatic discharge protection circuit

100‧‧‧Substrate

101‧‧‧ first component

102‧‧‧second component

103‧‧‧ third component

104‧‧‧ fourth component

110‧‧‧ input pad

120‧‧‧Internal circuits

130‧‧‧ Grounding terminal

200‧‧‧First Well

210‧‧‧Second well

220‧‧‧ diode junction

222‧‧‧ first end

224‧‧‧ second end

225‧‧‧ first diode

240‧‧‧Doped area

270‧‧‧ Impedance

280‧‧‧MOS structure

281‧‧‧ third well

286‧‧‧Doped area

287‧‧‧Doped area

288‧‧‧ gate

289‧‧‧second gate

290‧‧‧Doped area

300‧‧‧Protection ring structure

310‧‧‧fourth well

320‧‧‧Doped area

340‧‧‧Doped area

1011‧‧‧射极

1021‧‧‧ first pole

1022‧‧‧second pole

102'‧‧‧ diode junction

1022'‧‧‧Second pole

1031‧‧ ‧One end of diode 103

1032‧‧‧The other end of the diode 103

1 shows an equivalent circuit diagram of an electrostatic discharge protection circuit in an embodiment; FIG. 2 depicts a semiconductor structure of an electrostatic discharge protection circuit in an embodiment; 3 is a schematic view showing the addition of an impedance to the semiconductor structure of the ESD protection circuit of the embodiment of FIG. 2; FIG. 4 is a view showing the semiconductor structure of the ESD protection circuit of another embodiment; FIG. 5 shows the electrostatic discharge in an embodiment. A cross-sectional view of the protection circuit; FIG. 6 is a schematic view showing the addition of an impedance to the ESD protection circuit of the embodiment of FIG. 5; and FIG. 7 is a cross-sectional view showing the ESD protection circuit of an embodiment.

20‧‧‧Electrostatic discharge protection circuit

100‧‧‧Substrate

110‧‧‧ input pad

130‧‧‧ Grounding

200‧‧‧First Well

210‧‧‧Second well

220‧‧‧ diode junction

222‧‧‧ first end

224‧‧‧ second end

240‧‧‧First doped area

281‧‧‧ third well

286‧‧‧Doped area

287‧‧‧Doped area

288‧‧‧ gate

289‧‧‧second gate

290‧‧‧Doped area

Claims (17)

An ESD protection circuit is coupled to an input pad, wherein the ESD protection circuit comprises: a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type; a second well having a first conductivity type in the well; a first doped region in the second well having a first conductivity type, the first doped region being electrically coupled to the input pad; and one located at the second a second doped region having a second conductivity type in the well; a third doped region in the first well having a second conductivity type, the third doped region being electrically coupled to the input pad; and a The substrate has a fourth doped region of a first conductivity type. The electrostatic discharge protection circuit of claim 1, wherein the electrostatic discharge current is discharged by a passage between the fourth doping region and the input pad. The electrostatic discharge protection circuit of claim 1, wherein a potential formed in the first well is higher than in the second well. The electrostatic discharge protection circuit of claim 2, further comprising a first diode, wherein the first doped region is the first end of the diode and the second doped region is the second The second end of the polar body. The electrostatic discharge protection circuit of claim 4, wherein the discharge process of the electrostatic discharge current is sequentially from the input pad to the first doped region, and then from the first doped region to the second doped The impurity region is then from the second doped region to the ground. The electrostatic discharge protection circuit of claim 2, wherein the discharge process of the electrostatic discharge current sequentially flows from the fourth doping region to the substrate, and then from the substrate to the first well, and then from the first Well to the third doped region. The electrostatic discharge protection circuit of claim 4, further comprising a second diode, wherein the fourth doped region is the first end of the second diode and the third doped region is The second end of the second diode discharges an electrostatic discharge current from the first end to the second end. The electrostatic discharge protection circuit of claim 1, further comprising: a third well located in the substrate and having a first conductivity type; and a fifth doping in the third well and being a second conductivity type a sixth doped region in the third well and having a second conductivity type; a gate between the fifth doped region and the sixth doped region; and a second conductive region in the substrate a fourth well of the fourth well between the second doped region and the fourth doped region; a seventh doped region in the fourth well and of the second conductivity type; and a first conductivity type An eight-doped region, wherein the fifth doped region is electrically coupled to the second doped region and the sixth doped region is electrically connected to the fourth doped region, and the first doped region An eight-doped region is between the second doped region and the fourth doped region. The electrostatic discharge protection circuit of claim 1, further comprising an impedance between the input pad and the first doping region. An ESD protection circuit is coupled to an input pad, wherein the ESD protection circuit comprises: a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type; a diode component in the well, the diode component comprising a first end having a first conductivity type and a second end having a second conductivity type, wherein the first end is electrically coupled to the input pad; a first doped region of the second conductivity type and located in the first well, the first doped region is electrically coupled to the input pad; and a second doped region having a first conductivity type and located in the substrate The second doped region is electrically coupled to ground. The electrostatic discharge protection circuit of claim 10, wherein the input pad and the second doping section have a channel for discharging the electrostatic discharge current. The electrostatic discharge protection circuit of claim 10, wherein the potential formed in the first well is higher than in the second well. The electrostatic discharge protection circuit of claim 11, wherein the discharge channel of the electrostatic discharge current sequentially flows from the input pad to the diode element, and then from the diode element to the ground. The electrostatic discharge protection circuit of claim 11, wherein the discharge channel of the electrostatic discharge current sequentially flows from the second doping region to the substrate, and then from the substrate to the first well, and then The first well to the first doped region is further from the first doped region to the input pad. The electrostatic discharge protection circuit of claim 14, wherein the channel comprises a second diode. The electrostatic discharge protection circuit of claim 11, further comprising: a third well located in the substrate and of the first conductivity type; and being located in the third well and being of the second conductivity type a third doped region; a fourth doped region in the third well and a second conductivity type, a gate between the third doped region and the fourth doped region; and an NMOS The NMOS structure is interposed between the diode element and the second doped region, wherein the third doped region is electrically coupled to the second end of the diode element and the fourth doped region is electrically connected The second doped region. The electrostatic discharge protection circuit of claim 16, further comprising: an impedance between the input pad and the first end of the diode element; And a guard ring structure interposed between the diode element and the second doped region, wherein the guard ring structure comprises a fourth well and a fifth doped region in the fourth well And a sixth doped region in the substrate.