TWI431774B - Semiconductor device and lateral diffused metal-oxide-semiconductor transistor - Google Patents

Description

Semiconductor device and laterally diffused MOS transistor

The present invention relates to a semiconductor device, and more particularly to a semiconductor device incorporating a silicon controlled rectifier (SCR) in a laterally diffused metal-oxide-semiconductor transistor (LDMOS). .

With the continuous advancement of semiconductor process micro-shrinking technology, how to improve the reliability of semiconductor devices is becoming more and more important. However, in the process of manufacturing, processing, assembling, transporting, and using semiconductor devices, the entire process is subject to the threat of electrostatic discharge (ESD). Without proper protection measures, the semiconductor device may be damaged. Sales. Therefore, the ESD protection component is designed as a technology necessary for any semiconductor device. At present, especially in high voltage component products, the tolerance of ESD protection components must be as high as 8 kV. In the prior art, in order to increase the ESD protection tolerance and save the chip area, a silicon controlled rectifier (SCR) can be applied as an ESD protection component. However, if the holding voltage of the controlled rectifier is too low, the controlled rectifier will be triggered when the ESD occurs, even at the normal operating voltage of the component, and a latch-up will occur to damage the circuit.

There is a need in the art for a semiconductor device having an ESD protection element that can adjust the holding voltage to improve the above disadvantages.

In view of this, an embodiment of the present invention provides a semiconductor device including a substrate having a first conductivity type, a gate disposed on the substrate, and a source doped region formed in the substrate And adjacent to a first side of the gate, wherein the source doped region has a second conductivity type opposite to the first conductivity type; a drain doped region is formed in the substrate, and Adjacent to a second side of the first gate opposite to the first side, wherein the gate doped region is formed by staggering a plurality of first doped regions having the first conductivity type and having the second conductive The plurality of second doped regions are of a type.

Another embodiment of the present invention provides a laterally diffused metal oxide semiconductor (LDMOS) comprising a p-type substrate; a gate disposed on the p-type substrate; and a source doped region formed on the p a first side of the gate and adjacent to the gate; a drain doped region formed in the p-type substrate adjacent to the second side of the gate opposite to the first side The side, wherein the above-mentioned drain doping region is composed of a plurality of p-type doped regions and a plurality of n-type doped regions arranged in a staggered manner.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

Fig. 1 is a top plan view showing a semiconductor device 500a according to an embodiment of the present invention. Fig. 2a is a cross-sectional view taken along line A-A' of Fig. 1, and Fig. 2b is a cross-sectional view taken along line B-B' of Fig. 1. As shown in FIG. 1, the semiconductor device 500a in the embodiment of the present invention may include two laterally diffused metal-oxide-semiconductor transistors (hereinafter referred to as LDMOS) which are symmetrically and in parallel and share a common drain. The transistor, but the number of transistors depends on the design, and the number is not limited. . The main components of the semiconductor device 500a may include a substrate 200, gates 202a and 202b, source doped regions 204a and 204b, and a common drain doped region 206, wherein the gates 202a and 202b, the source doped regions 204a and 204b The doped region 206 and the doped region 206 are elongated in shape, and the gates 202a and 202b, the source doped regions 204a and 204b, and the drain doped region 206 are parallel to each other. As shown in FIGS. 2a and 2b, the gate 202a and the source doped region 204a are separated by a shallow trench spacer 201, and the gate 202a and the drain doped region 206 are separated by a shallow trench spacer 201. Separated. In one embodiment of the invention, the drain doping region 206 can be coupled to a high power supply VDD, and the source doping region 204a or 204b can be coupled to a ground GND.

In the embodiment of the present invention, the substrate 200 may be a germanium substrate. In other embodiments, silicon germanium (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI) may be utilized. , or other commonly used semiconductor substrates. The substrate 200 can be implanted with p-type or n-type impurities to change its conductivity type for design needs. In the embodiment of the present invention, the conductivity type of the substrate 200 is, for example, a p-type, and the semiconductor device 500a of the embodiment of the present invention is, for example, an n-type LDMOS.

As shown in FIG. 1, the gates 202a and 202b of the semiconductor device 500a of the embodiment of the present invention are disposed on the substrate 200. In the embodiment of the present invention, the gates 202a and 202b may be composed of a gate insulating layer of a lower layer and a gate layer of an upper layer, wherein the gate insulating layer may include, for example, an oxide or a nitride. A commonly used dielectric material such as oxynitride, oxycarbide or a combination thereof. The gate insulating layer 224 may also include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), hafnium silicate (HfSiO ₄ ). Zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO ₄ ), yttrium oxide (Y ₂ O ₃ ), lanthanum oxide High dielectric constant (high-k, La ₂ O ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), or combinations thereof A dielectric material having a dielectric constant greater than 8). The gate layer may include germanium or polysilicon. The gate layer is preferably doped with a dopant to reduce its sheet resistance. In other embodiments, the gate layer comprises amorphous silicon.

As shown in FIG. 1, the source doping regions 204a and 204b of the embodiment of the present invention are formed in the substrate 200 and adjacent to one side of the gates 202a and 202b, respectively. For example, source doped region 204a is adjacent to side edge 214 of gate 202a. In the embodiment of the present invention, the conductivity types of the source doping regions 204a and 204b are opposite to those of the substrate 200. For example, if the conductivity type of the substrate 200 is p-type, the conductivity types of the source doping regions 204a and 204b are Type n. In addition, the gate doped region 206 of the embodiment of the present invention is formed in the substrate 200, which may be a common drain region of two LDMOSs. As shown in FIG. 1, the drain doped region 206 is adjacent the opposite side of the gate 202a or 202b adjacent to the sides of the source doped regions 204a and 204b. For example, the drain doped region 206 is adjacent to the side edge 216 of the gate 202a, while the side edge 214 and the side edge 216 are opposite sides of each other. In the embodiment of the present invention, the gate doped region 206 is composed of a plurality of first doped regions 208a and a plurality of second doped regions alternately arranged along a long axis direction 300 of the drain doped region 206. 208b constitutes. As shown in FIG. 1, the side of the first doped region 208a and 202a of the gate 216 of the pitch D ₁ and D and the spacing of the second doped region 208b of the gate 202a of the side 216 is equal to _2, and the first doped The impurity region 208a has the same width W as the second doping region 208b. In an embodiment of the invention, the first doped region 208a and the second doped region 208b have opposite conductivity types. If the conductivity type of the first doping region 208a and the substrate 200 are p-type and the conductivity type of the second doping region 208b is n-type, the total area of the first doping region 208a and the gate doping region 206 are The ratio of the total area is greater than 0 and less than 1.

As shown in the first, second, and second embodiments, the semiconductor device 500a of the embodiment of the present invention may further include third doping regions 210a and 210b formed in the substrate 200 and surrounding the gates 202a and 202b and the source doping, respectively. The regions 204a and 204b, wherein the third doping regions 210a and 210b and the conductivity type of the substrate may be the same p-type. In the embodiment of the present invention, the third doping regions 210a and 210b may be regarded as p-type body regions 210a and 210b as a channel region and a source of the semiconductor device 500a. a part of. The semiconductor device 500a of the embodiment of the present invention may further include a fourth doping region 212 formed in the substrate 200 and surrounding the gate doping region 206. If the conductivity type of the substrate 200 is p-type, the conductivity type of the fourth doping region 212 is n-type. In the embodiment of the present invention, the fourth doping region 212 can be regarded as an n-type drift region 212, which is a part of the drain of the semiconductor device 500a.

Fig. 3 is a top plan view showing a semiconductor device 500b according to another embodiment of the present invention. In another embodiment of the invention, the gate 202c is annular in shape, the source doped regions 204a and 204b and the drain doped region 206 are elongated, and the gate doped region 206 is gated 202c. Surrounded. In addition, the shape of the third doping region 210c surrounding the source doping regions 204a and 204b and the gate 202c is also annular. As shown in FIG. 3, the first doped region 208a is equal to the distance d ₁ from the side 216 of the gate 202c and the distance d ₂ between the second doped region 208b and the side 216 of the gate 202c, and is first The doped region 208a and the second doped region 208b have the same width W.

4 is a schematic diagram showing an equivalent circuit of a semiconductor device 500a or 500b according to an embodiment of the present invention. The gate doped region 206 of the semiconductor device 500a or 500b is staggered by a plurality of first doped regions 208a and a plurality of second doped regions 208b having opposite conductivity types along the long axis direction of the drain doped region 206. Composition. In one embodiment of the present invention, the first doped region 208a and the second doped region 208b of the drain doped region 206 can be coupled to a high power supply VDD, and the source doped region 204a can be coupled to A ground 埠 GND. In an embodiment of the present invention, as shown in FIG. 4, if the conductivity type of the substrate 200 is p-type, the p-type in the fourth doping region 212 of the semiconductor device 500a, for example, an n-type drift doping region. The first doped region 208a and the n-type second doped region 208b are combined with a third doped region 210a such as a p-type body region to form a parasitic p-type n-type -p type bipolar junction transistor 410 (hereinafter referred to as PNP BJT). The p-type first doping region 208a can be regarded as the emitter of the parasitic PNP BJT 410, the n-type second doping region 208b and the first n-type drift region. The four-doped region 212 can be regarded as the base of the parasitic PNP BJT 410, and the third doped region 210a, which is, for example, a p-type body region, can be regarded as the parasitic PNP BJT. The collector of 410. In addition, for example, a fourth doping region 212 of an n-type drift region, a third doping region 210a and an n-type such as a p-type body region The source doped region 204a constitutes a parasitic n-type p-type n-type junction bipolar junction transistor (hereinafter referred to as NPN BJT). The fourth doping region 212, for example, an n-type drift region may be regarded as an emitter of the parasitic NPN BJT 420, for example, a p-type body doped region (p-type) The third doped region 210a of the body region can be regarded as the base of the parasitic NPN BJT 420, and the n-type source doped region 204a can be regarded as the collector of the parasitic NPN BJT 420. The PNP BJT 410 and the NPN BJT 420 may constitute a parasitic silicon controlled rectifier (hereinafter referred to as SCR). When subjected to ESD or zapping from a high power supply VDD, the parasitic SCR 600 is triggered to form a path from the high power supply VDD to the ground GND. Therefore, a large number of holes are injected into the p-type substrate 200 from the p-type first doping region 208a via the fourth doping region 212, which is, for example, an n-type drift region, and The n-type source doped region 204a in the third doped region 210a of the p-type body region leads the hole to the ground 埠 GND. It can be seen that the voltage controlled rectifier 600 can conduct a large amount of ESD transient current without damaging the semiconductor device 500a or 500b. In addition, the holding voltage of the SCR 600 can be adjusted by adjusting the area ratio of the first doping region 208a and the second doping region 208b to avoid triggering the SCR 600 even when the ESD is generated, even at the normal operating voltage of the component. The latch-up occurs and the circuit is damaged. Therefore, the semiconductor device 500a or 500b of the embodiment of the present invention can integrate an ESD protection component such as a controlled rectifier in a drain-doped region of a laterally diffused metal oxide semiconductor (LDMOS), thereby eliminating the need for an additional mask, Process and wafer area to make ESD protection components.

Table 1 is an n-type LDMOS device having p-type first doped regions of different areas prepared according to an embodiment of the present invention (starting voltage (Vt) = 200 V, channel length (L) = 0.9 μm, channel width (W) ) = 500 μm) and an n-type LDMOS device having a p-type first doped region (starting voltage (Vt) = 200 V, channel length (L) = 0.9 μm, channel width (W) = 500 μm), in ESD A comparison table of the withstand voltage test results of the human body mode (HBM) (in which the drain-doped region receives the ESD current, the source-doped region is grounded, and the gate is floating).

As can be seen from the first table, the n-type LDMOS device which does not have the p-type first doping region does not have the ESD protection function, and the withstand voltage in the ESD human body discharge mode (HBM) is only 0.12 kV. An n-type LDMOS device having a p-type first doped region having different areas prepared according to an embodiment of the present invention has an withstand voltage of more than 8 kV in an ESD human body discharge mode (HBM), and can pass an ESD human body discharge mode (HBM). ) the standard.

The semiconductor devices 500a and 500b of the embodiments of the present invention have the following advantages. The semiconductor device 500a and 500b of the embodiment of the present invention are doped with a plurality of first doped regions 208a and a plurality of second doped regions 208b having opposite conductivity types along the length of the drain doping region 206. The axial direction is arranged alternately. An ESD protection element such as a voltage controlled rectifier (SCR) can be integrated into the drain doped region of a laterally diffused metal oxide semiconductor (LDMOS). Thus, the semiconductor devices 500a and 500b of the embodiments of the present invention are semiconductor devices having both an ESD protection function and a laterally diffused metal oxide semiconductor (LDMOS) function, and can manufacture ESD protection components without additional mask, process, and wafer area. . In addition, the holding voltage of the ESD protection component such as a controlled rectifier (SCR) can be adjusted by adjusting the area ratio of the first doping region 208a and the second doping region 208b to avoid ESD, even in the case of ESD The component controls the rectifier (SCR) under normal operating voltage, and latch-up occurs to damage the circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is defined as defined in the scope of the patent application.

200. . . Substrate

201. . . Shallow trench spacer

202a, 202b, 202c. . . Gate

204a, 204b. . . Source doping region

206. . . Bipolar doping zone

208a. . . First doped region

208b. . . Second doped region

210a, 210b, 210c. . . Third doped region

212. . . Fourth doped region

214. . . First side

216. . . Second side

300. . . Long axis direction

410. . . P-type-n-p-type junction bipolar transistor

420. . . N-type-p-n-type junction double-carrier transistor

500a, 500b. . . Semiconductor device

600. . . Voltage controlled rectifier

VDD. . . High power supply

GND. . . Grounding埠

d ₁ , d ₂ . . . spacing

W. . . width

Fig. 1 is a top plan view showing a semiconductor device according to an embodiment of the present invention.

Fig. 2a is a cross-sectional view taken along line A-A' of Fig. 1.

Fig. 2b is a cross-sectional view taken along line B-B' of Fig. 1.

Fig. 3 is a top plan view showing a semiconductor device according to another embodiment of the present invention.

4 is a schematic diagram showing an equivalent circuit of a semiconductor device according to an embodiment of the present invention.

200. . . Substrate

202a, 202b. . . Gate

204a, 204b. . . Source doping region

206. . . Bipolar doping zone

208a. . . First doped region

208b. . . Second doped region

210a, 210b. . . Third doped region

212. . . Fourth doped region

214. . . First side

216. . . Second side

300. . . Long axis direction

d ₁ , d ₂ . . . spacing

W. . . width

Claims (27)

A semiconductor device comprising: a substrate having a first conductivity type; a gate disposed on the substrate; a source doped region formed in the substrate and adjacent to the first of the gates a side, wherein the source doped region has only a second conductivity type opposite to the first conductivity type; and a drain doped region is formed in the substrate adjacent to the gate relative to the first a second side of one side, wherein the drain doped region is composed of a plurality of first doped regions having the first conductivity type and a plurality of second doped regions having the second conductivity type . The semiconductor device of claim 1, wherein the gate, the source doped region, and the drain doped region have an elongated shape. The semiconductor device of claim 1, wherein the gate is annular in shape, the source doped region and the drain doped region are elongated, wherein the drain doped region is The gate is surrounded. The semiconductor device of claim 1, wherein the gate, the source doped region, and the drain doped region are parallel to each other. The semiconductor device of claim 1, wherein the plurality of the first doped regions and the plurality of the second doped regions are staggered along a long axis direction of the drain doped region, and plural The first doped region and the plurality of the second doped regions have the same width. The semiconductor device of claim 1, wherein a plurality of the first doped regions and the plurality of second doped regions are equal to a pitch of the second side of the gate. The semiconductor device of claim 1, further comprising: a third doped region formed in the substrate and surrounding the gate and the source doped region, wherein the third doped region has The first conductivity type; and a fourth doping region formed in the substrate and surrounding the gate doping region, wherein the fourth doping region has the second conductivity type. The semiconductor device of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type. The semiconductor device of claim 8, wherein a ratio of a total area of the first doped region to a total area of the drain doped region is greater than 0 and less than 1. The semiconductor device of claim 1, wherein the gate and the source doped region are separated by a shallow trench spacer. The semiconductor device of claim 1, wherein the gate and the drain doping region are separated by a shallow trench spacer. The semiconductor device of claim 7, wherein the first doped region, the adjacent second doped region and the third doped region form a first bipolar transistor. The semiconductor device of claim 7, wherein the fourth doped region, the third doped region and the source doped region form a second bipolar transistor. The semiconductor device of claim 12, wherein the first bipolar transistor and the second bipolar transistor form a controlled rectifier. A laterally diffused metal oxide semi-transistor (LDMOS) comprising: a p-type substrate; a gate disposed on the p-type substrate; a source doped region formed in the p-type substrate adjacent to a first side of the gate, wherein the source is doped The doped region is formed by a single n-type source doped region; and a drain doped region is formed in the p-type substrate adjacent to a second side of the gate opposite to one of the first side edges, The gate doped region is composed of a plurality of p-type doped regions and a plurality of n-type doped regions arranged in a staggered manner. The laterally diffused MOS transistor according to claim 15, wherein the gate, the source doped region and the drain doped region have an elongated shape. The laterally diffused MOS transistor according to claim 15, wherein the gate has a ring shape, and the source doped region and the drain doped region have an elongated shape, wherein the buck is The doped region is surrounded by the gate. The laterally diffused MOS transistor according to claim 15, wherein the gate, the source doped region and the drain doped region are parallel to each other. The laterally diffused MOS transistor according to claim 15, wherein the plurality of n-type doped regions and the plurality of p-type doped regions are staggered along a long axis direction of the drain doped region. And a plurality of the n-type doped regions and the plurality of the p-type doped regions have the same width. The laterally diffused MOS transistor according to claim 15, wherein an interval between each of the n-type doped regions and each of the p-type doped regions and the second side of the gate is equal . The laterally diffused MOS semi-transistor as described in claim 15 of the patent application, further comprising: a p-type body doped region formed in the substrate and surrounding the gate and the source doped region; and an n-type drift doped region formed in the substrate and surrounding the gate doped region . The laterally diffused MOS transistor according to claim 15, wherein a ratio of a total area of the p-type doped region to a total area of the drain-doped region is greater than 0 and less than 1. The laterally diffused MOS transistor according to claim 15, wherein the gate and the source doped region are separated by a shallow trench spacer. The laterally diffused MOS transistor according to claim 15, wherein the gate and the drain doping region are separated by a shallow trench spacer. The laterally diffused MOS transistor according to claim 21, wherein the p-type doped region, the adjacent n-type doped region and the p-type body doped region form a first double carrier Transistor. The laterally diffused MOS transistor according to claim 21, wherein the n-type diffusion doping region, the p-type body doping region and the source doping region form a second bipolar transistor. . The laterally diffused MOS transistor according to claim 25 or 26, wherein the first bipolar transistor and the second bipolar transistor constitute a sigma rectifier.