TW201539745A - High voltage semiconductor device and method for manufacturing the same - Google Patents

Abstract

A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT.

Description

High voltage semiconductor component and method of manufacturing same 【0001】

The present invention relates to a high voltage semiconductor device and a method of fabricating the same, and more particularly to a high voltage semiconductor device having ESD protection and a method of fabricating the same.

【0002】

With the development of semiconductor technology, power integrated circuit process integration technology (Bipolar CMOS DMOS, BCD) has been widely used in the manufacture of high voltage semiconductor components. In the high-voltage semiconductor components fabricated by the power integrated circuit process integration technology, the operating voltage of the semiconductor components is getting higher and higher, and the electrostatic-static discharge (ESD) protection on the wafer becomes a very important task item. .

[0003]

In general, high voltage semiconductor components typically have low on-state resistance (Rdson) characteristics. Therefore, when an electrostatic discharge is generated, the electrostatic current is easily concentrated on the surface of the substrate or the edge of the source. High voltage currents and high electric fields cause physical damage to the surface junction region. The electrical requirements of low on-resistance are required based on high voltage semiconductor components. The surface or sidewall of the high voltage semiconductor component cannot be increased. Therefore, how to design a better electrostatic protection structure in accordance with the basic electrical requirements is a serious challenge.

[0004]

Furthermore, the breakdown voltage of the high voltage semiconductor component is always higher than the operation voltage. The trigger voltage is usually much higher than the breakdown voltage. Therefore, during electrostatic discharge, the protection component or internal circuitry is generally at risk of damage before the high voltage semiconductor component initiates electrostatic protection. In order to reduce the trigger voltage, it is usually necessary to construct an additional static protection circuit.

[0005]

In addition, high voltage semiconductor components generally have a low holding voltage characteristic. High-voltage semiconductor components may be triggered by unwanted noise, or power-on peak voltage or serge voltage, and latch-up occurs during normal operation. )effect.

[0006]

Furthermore, high voltage semiconductor components typically have a field plate effect. The distribution of the electric field is easily disturbed, so that electrostatic discharge currents tend to concentrate on the surface or the edge of the drain when an electrostatic discharge event occurs.

【0007】

Some of the current methods of electrostatic protection require additional masking or processing steps. One of the traditional methods of electrostatic protection of high voltage semiconductor components is to provide additional components, and these added components are only used for electrostatic protection. These additional components are usually diodes, bipolar transistors (BJT), or metal oxide semiconductor transistors (MOS) that increase the size of the surface or sidewalls. , or a Silicon Controlled Rectifier (SCR). Among them, the controlled rectifier has the characteristics of low holding voltage, so the latch-up effect easily occurs during normal operation.

[0008]

The present invention relates to a high voltage semiconductor device having ESD protection and a method of fabricating the same. The high voltage semiconductor component of the embodiment incorporates a normally open low voltage semiconductor transistor and a high voltage semiconductor transistor to provide electrostatic protection without the need for additional components providing electrostatic protection. The high voltage semiconductor component of the embodiment not only provides electrostatic protection, but also improves the electronic characteristics of the high voltage semiconductor component under direct current application.

【0009】

According to an embodiment, a high voltage semiconductor device is provided comprising a high voltage semiconductor transistor (HVMOS) and a normally-on LVMOS electrically connected high voltage semiconductor transistor. The HVMOS has a first collector and a first emitter. The normally-on LVMOS has a second collector and a second emitter, wherein the second collector of the normally-on LVMOS is electrically connected to the first emitter of the HVMOS, thereby forming a second emitter Electro-static discharge bipolar transistor (ESD BJT), such as an NPN-type electrostatic protection bipolar transistor.

[0010]

According to an embodiment, a method for fabricating a high voltage semiconductor device includes: forming a high voltage semiconductor transistor (HVMOS) on a substrate, the HVMOS having a first collector and a first emitter; and forming a normally open type The low-voltage semiconductor transistor (normally-on LVMOS) is electrically connected to the HVMOS, and the LVMOS has a second collector and a second emitter, wherein the second collector of the normally-on LVMOS is electrically connected to the first emitter of the HVMOS Thus, an electrostatic protection bipolar transistor is formed.

[0011]

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

[0035]

100‧‧‧High-voltage semiconductor components
110‧‧‧High Voltage Semiconductor Transistor (HVMOS)
120‧‧‧Normally open low voltage semiconductor transistor (normally-on LVMOS)
190‧‧‧Internal circuits
20‧‧‧P type substrate
21‧‧‧High pressure N-well
23‧‧‧ Thick oxides
24‧‧‧Thin oxide layer
26‧‧‧ Vacant or primary doped areas
27‧‧‧ patterned polycrystalline layer
271‧‧‧ first hole
272‧‧‧Second hole
28‧‧‧NPN District
285‧‧‧Poly Island
C1‧‧‧ first episode
C2‧‧‧Second episode
E1‧‧‧first emitter
E2‧‧‧second emitter
P-body‧‧‧P body
D1‧‧‧High voltage bungee
D2‧‧‧Low-voltage bungee
G1‧‧‧High voltage gate
G2‧‧‧ low voltage gate
S/B‧‧‧Source/base
FOX‧‧ field oxide
P+‧‧‧P type heavily doped area
N+, 29‧‧‧N type heavily doped area
P1, P2‧‧‧ trigger point
Vt1, Vt2‧‧‧ trigger voltage
It1, It2‧‧‧ trigger current
(I), (II), C1, C2‧‧‧ IV curves.

[0012]

Fig. 1A is a circuit diagram of a high voltage semiconductor element having electrostatic protection according to an embodiment of the present invention.

Fig. 1B is an equivalent circuit diagram of Fig. 1A.

Fig. 1C is an equivalent circuit diagram of Fig. 1B.

Figure 2 is a top plan view of a high voltage semiconductor device with electrostatic protection according to an embodiment of the present invention.

3A-3C are cross-sectional views along the line A-A', B-B', and C-C' of FIG. 2, respectively.

Fig. 4A shows TLP curves (I) and (II) representing conventional MOS elements and embodiment high voltage semiconductor elements, respectively.

Figure 4B is an enlarged view of the circled area in Figure 4A.

Fig. 5 is a direct current (DC) I-V characteristic curve (on-resistance) of a conventional MOS device and an embodiment high voltage semiconductor device in an on state.

Fig. 6 is an I-V characteristic curve of the gate saturation current (Idsat) of the conventional MOS device and the embodiment high voltage semiconductor device.

[0013]

In the embodiments disclosed herein, a high voltage semiconductor device having electrostatic protection and a method of fabricating the same are proposed. Embodiments suggest that a high voltage semiconductor device comprising a high voltage semiconductor transistor (HVMOS) and a normally-on low voltage semiconductor transistor (normally-on LVMOS) electrically connected to a high voltage semiconductor transistor, thereby forming an electrostatic protection bipolar transistor ( Electro-static discharge bipolar transistor (ESD BJT), such as an NPN type electrostatic protection bipolar transistor. The high voltage semiconductor component of the embodiment not only provides electrostatic protection, but also improves the electronic characteristics of the high voltage semiconductor component under direct current application. The high-voltage semiconductor component according to the embodiment combines a normally-open type low-voltage semiconductor transistor and a high-voltage semiconductor transistor, and does not need to additionally add an element for providing electrostatic protection, so that the total area of the high-voltage semiconductor element is not increased, and Traditional high voltage semiconductor transistors and other areas. In normal operation, the normally-on low-voltage semiconductor transistor and the high-voltage semiconductor transistor are turned on at the same time. Moreover, in normal operation, the high voltage semiconductor component of the embodiment can be triggered by a higher trigger current, thereby avoiding unwanted latch-up effects during normal operation.

[0014]

Compared with the conventional high voltage semiconductor transistor, the high voltage semiconductor device of the embodiment has a lower on-state resistance (Rdson), a higher saturation current of the drain (Idsat) and a comparison. High breakdown voltage and other characteristics. Furthermore, the high voltage semiconductor components of the embodiments can be fabricated using standard power integrated circuit process integration techniques (Bipolar CMOS DMOS, BCD) and triple well processes without the need for additional masks or additional processes. Therefore, the high voltage semiconductor element of the embodiment can be fabricated by a simple method without using a time consuming and expensive process.

[0015]

The disclosed embodiments can be applied to many different types of high voltage semiconductor components, and the disclosure is not limited to a certain application. The following embodiments are presented in conjunction with the drawings to explain in detail one of the electrostatic protection high voltage semiconductor components and methods of fabricating the same as disclosed in the present disclosure. However, the disclosure is not limited to this. The descriptions of the embodiments, such as the details of the structure and the choice of materials, etc., are for illustrative purposes only and are not intended to limit the scope of the disclosure.

[0016]

Furthermore, the disclosure does not show all possible embodiments. The structure and process may be modified and modified to meet the needs of the actual application without departing from the spirit and scope of the disclosure. Therefore, other implementations not presented in the present disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

[0017]

Fig. 1A is a circuit diagram of a high voltage semiconductor element having electrostatic protection according to an embodiment of the present invention. A high voltage semiconductor device 100 includes a high voltage semiconductor transistor (HVMOS) 110 and a normally-on low voltage semiconductor transistor (normally-on LVMOS) 120 electrically coupled to the high voltage semiconductor transistor 110. The high voltage semiconductor transistor 110 has a first collector C1 and a first emitter E1. The normally-open low-voltage semiconductor transistor 120 has a second collector C2 and a second emitter E2, wherein the second collector C2 of the normally-on low-voltage semiconductor transistor 120 is electrically connected. Up to the first emitter E1 of the high voltage semiconductor transistor 110. The low voltage gate LV gate G2 of the normally-on low-voltage semiconductor transistor 120 is connected to a high voltage HV gate G1 of the high voltage semiconductor transistor 110 and electrically connected to an internal circuit 190.

[0018]

Please refer to both Figure 1B and Figure 1C. Fig. 1B is an equivalent circuit diagram of Fig. 1A. Fig. 1C is an equivalent circuit diagram of Fig. 1B. The portions selected by the dotted circles in FIGS. 1A and 1B are part of the circuit that can be combined. According to an embodiment, a high voltage semiconductor component incorporating a high voltage semiconductor transistor 110 and a normally open low voltage semiconductor transistor 120 can form an electro-static discharge bipolar transistor (ESD BJT), such as an NPN type ESD BJT. .

[0019]

Please refer to Figure 2 and Figure 3A~3C at the same time. Figure 2 is a top plan view of a high voltage semiconductor device with electrostatic protection according to an embodiment of the present invention. 3A to 3C are cross-sectional views taken along the line A-A', B-B', and C-C' of Fig. 2, respectively. The hatching A-A' position in Fig. 2 corresponds to the low voltage gate G2 of the normally open low voltage semiconductor transistor (LVMOS) 120 of the high voltage semiconductor device 100 and the high voltage gate G1 of the high voltage semiconductor transistor (HVMOS) 110. The position of the hatching B-B' in Fig. 2 corresponds to the source/base (S/B) of the normally-on LVMOS 120 of the high-voltage semiconductor device 100. The position of the hatching C-C' in Fig. 2 corresponds to the drain (D2) of the normally-on LVMOS 120 of the high-voltage semiconductor device 100.

[0020]

In an embodiment, a high voltage semiconductor device 100 includes a patterned polysilicon layer 27 formed on a substrate 20, and the patterned polysilicon layer 27 has a poly-gate portion formed continuously. As the low voltage gate G2 of the normally-on LVMOS 120 and the high voltage gate G1 of the HVMOS 110, as shown in FIG. Furthermore, the patterned polysilicon layer 27 has a plurality of first hollows 271 and a plurality of second hollows 272 alternately and separately arranged and arranged along a column direction, for example along Arranged in the y-direction. The first hole 271 corresponds to a plurality of source/base regions (S/B regions) of the normally-on LVMOS 120, and the second hole 272 corresponds to a plurality of drain regions D2 of the normally-on LVMOS 120. In one embodiment, the normally-on LVMOS 120 and HVMOS 110 share the same source/base (S/B). Furthermore, the drain region D1 of the HVMOS 110 is located on the outer side of the normally-on LVMOS 120, and is also arranged in the row direction (for example, arranged in the y-direction), and the row direction of the drain region D1 of the HVMOS 110 is arranged. It is parallel to the drain region D2 and the source/base region (S/B) of the normally-on LVMOS 120.

[0021]

In the embodiment, the following is an example of fabricating a high voltage semiconductor device on a first conductive substrate, such as a P-type substrate 20. FIG. 3A illustrates the position of the low voltage gate G2 of the normally-on LVMOS 120 of the high voltage semiconductor device 100 and the position of the high voltage gate G1 of the HVMOS 110. As shown in Fig. 3A, HVMOS 110 and LVMOS 120 are disposed in a high voltage N-type well (HVNW) 21 of a P-type substrate 20. HVMOS 110 further includes N-type wells (NWs), P-type wells (PWs) partially overlapping N-type wells, insulators adjacent to LVMOS 120 such as field oxides (FOX), thick oxides above field oxides, The N-type heavily doped region (N+) corresponds to the drain D1 and the high voltage gate G1. The normally-on LVMOS 120 includes a P-body in a high-voltage N-well (HVNW) 21, a thin oxide layer 24 connected to a thick oxide 23, and a low-voltage gate G2, wherein the P-type system is self-P-type substrate. The surface of 20 extends downward. As shown in FIG. 3A, the low voltage gate G2 of the normally-on LVMOS 120 includes a polysilicon portion partially covering the P-body and connected to the high voltage gate G1 of the HVMOS 110.

[0022]

In one embodiment, the normally-on LVMOS 110 may suitably form a depletion region or a native implant region 26 in the high-pressure N-well 21, wherein the depletion region or the native doping region 26 The surface extends downward from the surface of the P-type substrate 20, and the P-body is located in the depletion region or the native doping region 26. When the same gate voltage is applied to an embodiment element having and without a depletion region or a native doping region 26, the former embodiment (having a depletion region or a native doping region 26) has a lower on-resistance (Rdson) Good electrical properties such as higher buckling saturation current (Idsat).

[0023]

Fig. 3B shows not only the position of the HVMOS 110 of the high voltage semiconductor device 100 but also the source/base (S/B) of the normally open LVMOS 120. The components of the HVMOS 110 of FIG. 3B are the same as those of FIG. 3A and will not be repeated here. The source/base (S/B) region of the normally-on LVMOS 120 of the embodiment, except for the P-type body in the depletion region or the native doping region 26, the thin oxide layer 24 and the pattern connecting the thick oxide 23 In addition to the polysilicon layer 27 (forming the low voltage gate G2 of FIG. 3A), an NPN region 28 is further included in the P-type body, and the NPN region 28 extends downward from the surface of the P-type substrate 20, and the NPN region 28 includes two N layers. A heavily doped region (N+) and a P-type heavily doped region (P+) between the two N-type heavily doped regions. Furthermore, the source/base (S/B) region of the normally-on LVMOS 120 of the embodiment further includes a polysilicon island 285 and a first hole 271 of the patterned polysilicon layer 27 surrounding the polycrystalline island. 285. A polycrystalline germanium island 285 is formed on and connected to the P-type heavily doped region (P+) of the NPN region 28, and the first hole 271 surrounding the polycrystalline germanium island 285 exposes at least two N-type heavily doped regions of the NPN region 28. District (N+). In one embodiment, the first hole 271 exposes two N-type heavily doped regions of the NPN region 28 and a portion of the P-type heavily doped region (P+), as shown in FIG. 3B.

[0024]

The 3C diagram shows not only the position of the HVMOS 110 of the high voltage semiconductor device 100 but also the position of the drain (D2) of the normally open LVMOS 120. The components of the HVMOS 110 of FIG. 3C are the same as those of FIG. 3A and will not be repeated here. The drain region of the normally-on LVMOS 120 of the embodiment, except for the P-type body in the depletion region or the native doping region 26, the thin oxide layer 24 connecting the thick oxide 23, and the patterned polysilicon layer 27 (forming FIG. 3A) In addition to the low voltage gate G2), an N-type heavily doped region 29 is further included in the P-type body and the second hole 272 in the patterned polysilicon layer 27. The N-type heavily doped region 29 extends downward from the surface of the P-type substrate 20, and the second hole 272 exposes at least the N-type heavily doped region 29.

[0025]

In the embodiment, the low voltage gate G2 of the normally-on LVMOS 120 is connected to the high voltage gate G1 of the HVMOS 110. Furthermore, the low voltage drain (LV drain, D2) of the normally open LVMOS 120 is connected to the high voltage source (HV source) of the HVMOS 110. In the embodiment, the normally-on LVMOS 120 is disposed perpendicular to the HVMOS 110 (eg, 90-degree rotation) to reduce the size of the high-voltage semiconductor device 100 to which the present disclosure is applied.

[0026]

According to the high voltage semiconductor device disclosed in the embodiment, a HVMOS 110 and a normally open LVMOS 120 are electrically connected to the HVMOS 110 to form an electrostatic protection bipolar transistor (ESD BJT), such as an NPN type electrostatic protection bipolar transistor. The equivalent circuit diagram is shown in Figure 1A, 1B or 1C. In normal operation, the normally-on low-voltage semiconductor transistor and the high-voltage semiconductor transistor are turned on at the same time. When the high-voltage semiconductor device of the embodiment is generated by an electrostatic discharge event, the current of the electrostatic discharge is evacuated from the deeper path of the BJT, thereby achieving an electrostatic protection effect. Furthermore, the high-voltage semiconductor device of the embodiment incorporates the normally-on LVMOS 120 and the HVMOS 110, and there is no need to additionally provide an element for providing electrostatic protection, so that the total area of the high-voltage semiconductor element is not increased, and the same area as the conventional HVMOS can be used. Moreover, in normal operation, the high voltage semiconductor component of the embodiment can be triggered by a higher trigger current, thereby avoiding a latch-up effect.

[0027]

The present disclosure further performs a Transmission Line Pulse (TLP) test to observe the characteristics of the electrostatic discharge protection of the embodiment and the conventional MOS element under electrostatic bombardment. When performing a transmission line pulse test, the component is subjected to continuous transient pulses and an I-V (current-voltage) curve is obtained.

[0028]

Fig. 4A shows TLP curves (I) and (II) representing conventional MOS elements and embodiment high voltage semiconductor elements, respectively. Figure 4B is an enlarged view of the circled area in Figure 4A. The points P1 and P2 of the TLP curves (I) and (II) represent the trigger points of the conventional MOS element and the embodiment high voltage semiconductor element, respectively. Once the component is triggered, the voltages of the conventional MOS component and the embodiment high voltage semiconductor component are pulled back and a current flows under a linear on-resistance. The trigger voltage Vt1 and the trigger current It1 of the conventional MOS device trigger point P1, and the trigger voltage Vt2 and the trigger current It2 of the embodiment high-voltage semiconductor element trigger point P2 are also indicated in FIGS. 4A and 4B. 4A and 4B clearly show that the high voltage semiconductor component of the embodiment is triggered by a higher trigger current It2 (e.g., about 400-500 mA), which is about 3 to 4 times the trigger current It1 of the conventional MOS device. The location of a latching noise (e.g., about 100-200 mA) is also indicated in Figure 4B. The trigger current It2 of the high voltage semiconductor device of the embodiment is much higher than the latch noise. Therefore, the high voltage semiconductor device of the embodiment can be triggered by a higher trigger current during normal operation, solving the latch problem that the conventional MOS device can generate.

[0029]

Furthermore, the high voltage semiconductor device of the embodiment not only provides electrostatic protection, but also improves the electronic characteristics of the high voltage semiconductor device under direct current application. In normal operation, the normally open LVMOS and HVMOS are both turned on at the same time. The high voltage semiconductor device of the embodiment has lower on-resistance (Rdson), higher drain saturation current (Idsat), and higher breakdown voltage than conventional high voltage semiconductor transistors.

[0030]

Fig. 5 is a direct current (DC) I-V characteristic curve (on-resistance) of a conventional MOS device and an embodiment high voltage semiconductor device in an on state. In Fig. 5, the curve C1 (symbol -◆-) is the on-resistance (Rdson) of the conventional MOS device, and the curve C2 (symbol -■-) is the on-resistance of the high voltage semiconductor device of the embodiment. The results of Fig. 5 show that the on-resistance (C2) of the high voltage semiconductor device of the embodiment is lower than the on-resistance (C1) of the conventional MOS device.

[0031]

Fig. 6 is an I-V characteristic curve of the gate saturation current (Idsat) of the conventional MOS device and the embodiment high voltage semiconductor device. Similarly, the curve C1 (symbol -◆-) is the gate saturation current of the conventional MOS device, and the curve C2 (symbol -■-) is the gate saturation current of the high voltage semiconductor device of the embodiment. The results of Fig. 6 indicate that the embodiment high voltage semiconductor device has a higher drain saturation current (C2).

[0032]

In general, high voltage ESD protection is usually the placement of high voltage electrostatic components in the circuit, while low voltage MOS semiconductors are commonly used in low voltage components. According to the above, the high voltage semiconductor device of the embodiment has an HVMOS and a normally-on LVMOS electrically connected to the HVMOS to form an electrostatic protection bipolar transistor (for example, an NPN type ESD BJT). The high voltage semiconductor component of the embodiment not only provides electrostatic protection, but also improves the electronic characteristics of the high voltage semiconductor component under direct current application. In normal operation, the normally open LVMOS and HVMOS are turned on at the same time. Compared to conventional MOS devices, the high voltage semiconductor device of the embodiment can be triggered by a higher trigger current, thereby avoiding a latch-up effect. Furthermore, the high-voltage semiconductor device of the embodiment does not need to additionally add an element for providing electrostatic protection, so that the total area of the high-voltage semiconductor element is not increased, and the same area as the conventional HVMOS can be used. In addition, the high voltage semiconductor device of the embodiment has characteristics such as lower on-resistance (Rdson), higher gate saturation current (Idsat), and higher breakdown voltage. In one embodiment, although the surface or side area of the embodiment elements is increased to achieve electrostatic discharge protection, the effective width of the embodiment elements is only 33% to 50% of the standard high voltage MOS, and the embodiment elements still have low on-resistance and The same electronic properties of the bungee saturation current. Furthermore, the high voltage semiconductor components of the embodiments can be fabricated by standard power integrated circuit process integration technology (BCD) and triple well process without the need for additional masks or additional processes. Therefore, the high voltage semiconductor element of the embodiment can be fabricated by a simple method without using a time consuming and expensive process.

[0033]

Furthermore, the embodiments of the present disclosure can be applied to many different types of high voltage semiconductor components, and are not limited to a particular application or manner. For example, the high voltage semiconductor component of the embodiment can be applied to any process and any operating voltage. The high voltage semiconductor component of the embodiment can be fabricated in any standard process without adding any photomask. The high-voltage semiconductor component with electrostatic protection in the embodiment can be applied to the twin well process if the N+ buried layer is removed, and can also be applied to the non-EPI process with the Mitsui process technology. Embodiments can also be applied to single or dual polysilicon processes. Furthermore, the description in the embodiments, such as the detailed structure and material selection, are for illustrative purposes only, and may be appropriately adjusted or changed as needed for practical application. For example, in Mitsui process technology applications, the N+ buried layer can be fabricated using N-type epitaxial, or deep N-type wells, or multi-layer stacked N+ buried layers. In the case of dual well process technology, the N+ buried layer can also be removed. The local oxidation of silicon (LOCOS) may be shallow trench isolation (STI). The P-well (PW) may be a P-well and a P+ buried layer or a stack formed with P-type doping. The N-type well (NW) can be N-type doped. HVMOS 110 can be any high voltage component for DC application.

[0034]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

110‧‧‧High Voltage Semiconductor Transistor (HVMOS)

120‧‧‧Normally open low voltage semiconductor transistor (normally-on LVMOS)

20‧‧‧P type substrate

27‧‧‧ patterned polycrystalline layer

271‧‧‧ first hole

272‧‧‧Second hole

D1‧‧‧High voltage bungee

D2‧‧‧Low-voltage bungee

G1‧‧‧High voltage gate

G2‧‧‧ low voltage gate

S/B‧‧‧Source/base

Claims (10)

[Item 1] A high voltage semiconductor component comprising:
a high voltage semiconductor transistor (HVMOS) having a first collector and a first emitter; and a normally open low voltage semiconductor transistor (LVMOS) electrically connected to the high voltage semiconductor a transistor, and the normally-on low-voltage semiconductor transistor has a second collector and a second emitter, wherein the second collector of the normally-on low-voltage semiconductor transistor Optionally connected to the first emitter of the high voltage semiconductor transistor. [Item 2] The high voltage semiconductor device according to claim 1, wherein the high voltage semiconductor transistor electrically connected to the normally open low voltage semiconductor crystal system forms an NPN type electrostatic protection bipolar transistor (NPN ESD BJT), A low voltage gate (LV gate) of the normally-on low-voltage semiconductor transistor is connected to a high voltage gate (HV gate) of the high voltage semiconductor transistor, and a low voltage drain system of the normally-open low-voltage semiconductor transistor a high voltage source of the high voltage semiconductor transistor is commonly connected, the normally open low voltage semiconductor transistor and the high voltage semiconductor transistor system share the same source/base (S/B), and the normally open low voltage semiconductor The electro-crystalline system is disposed perpendicular to the high voltage semiconductor transistor. [Item 3] The high voltage semiconductor device according to claim 1, wherein the high voltage semiconductor transistor and the normally open low voltage semiconductor crystal system are disposed in a high voltage N-type well (HVNW) of a P-type substrate, and the The open type low voltage semiconductor transistor further includes:
a P-body is in the high-pressure N-type well, and the P-type system extends downward from a surface of the P-type substrate;
a depletion region or a native implant region in the high voltage N-type well, wherein the depletion region or the native doped region extends downward from the surface of the P-type substrate, and the A P-type body is located in the depletion region or the native doped region; and a low-voltage gate system includes a polysilicon portion covering the P-type body and connecting a high voltage gate of the high voltage semiconductor transistor. [Item 4] The high voltage semiconductor device according to claim 1, wherein the high voltage semiconductor transistor and the normally open low voltage semiconductor crystal system are disposed in a high voltage N-type well (HVNW) of a P-type substrate, and the The open type low voltage semiconductor transistor further includes:
a P-body is in the high-pressure N-type well, and the P-type system extends downward from a surface of the P-type substrate;
A low voltage source/bulk (S/B) region, including:
An NPN region is in the P-type body, and the NPN region extends downward from the surface of the P-type substrate, the NPN region includes two N-type heavily doped regions, and is located between the two N-type heavily doped regions a P-type heavily doped region; and a polycrystalline germanium body and a first hole surrounding the polycrystalline germanium island, wherein the polycrystalline germanium island system is formed on the P-type heavily doped region of the NPN region, and the first hole Exposing at least the N-type heavily doped regions of the NPN region; and a low-voltage drain region, comprising:
An N-type heavily doped region is in the P-type body, and the N-type heavily doped region extends downward from the surface of the P-type substrate; and a second hole is formed in a polysilicon layer, and the second The hole exposes at least the N-type heavily doped region. [Item 5] The high voltage semiconductor device of claim 1, further comprising a patterned polysilicon layer formed on a substrate, wherein the patterned polysilicon layer comprises:
a polysilicon gate portion continuously formed as one of the low voltage gate of the normally-on low voltage semiconductor transistor and one of the high voltage gate of the high voltage semiconductor transistor;
The plurality of first holes and the plurality of second holes are alternately and separately arranged, wherein the first holes are opposite to a plurality of source/base regions of the normally open low voltage semiconductor transistor, The second holes are opposite to a plurality of drain regions of the normally open low voltage semiconductor transistor.
Wherein each of the source/base regions comprises a polycrystalline island and one of the first holes surrounds the polycrystalline island, the polycrystalline island being connected to one of the P-types a doped region, wherein the first hole exposes at least two N-type heavily doped regions on both sides of the P-type heavily doped region;
Each of the drain regions includes an N-type heavily doped region located in a P-type body extending downward from the surface of the substrate, wherein the second hole exposes the N-type heavily doped region. [Item 6] A method of manufacturing a high voltage semiconductor device, comprising:
Forming a high voltage semiconductor transistor (HVMOS) on a substrate, the high voltage semiconductor transistor having a first collector and a first emitter; and forming a normally open low voltage semiconductor The crystal (LVMOS) is electrically connected to the high voltage semiconductor transistor, and the normally open low voltage semiconductor transistor has a second collector and a second emitter, wherein the normally open low voltage The second collector of the semiconductor transistor is electrically coupled to the first emitter of the high voltage semiconductor transistor, thereby forming an electrostatic protection bipolar transistor. [Item 7] The manufacturing method of claim 6, wherein a low-voltage gate of the normally-on low-voltage semiconductor transistor is connected to a high-voltage gate of the high-voltage semiconductor transistor, the normally-on low-voltage semiconductor transistor A low voltage drain is connected to a high voltage source of the high voltage semiconductor transistor, and the normally open low voltage semiconductor transistor and the high voltage semiconductor crystal system share the same source/base (S/B). The normally open low voltage semiconductor electro-crystalline system is disposed perpendicular to the high voltage semiconductor transistor. [Item 8] The manufacturing method of claim 6, wherein the high voltage semiconductor transistor and the normally-open low-voltage semiconductor electro-crystal system are formed in a high-pressure N-well (HVNW) of a P-type substrate, and the normally-on Type low voltage semiconductor transistors further include:
a P-body in the high-pressure N-type well, and the P-type system extends downward from a surface of the P-type substrate; and a depletion region or a native implant a region in the high-pressure N-type well, wherein the depletion region or the native doped region extends downward from the surface of the P-type substrate, and the P-type system is formed in the depletion region or the native doped region . [Item 9] The manufacturing method of claim 8, wherein the low voltage source/base (S/B) region of the normally-on low-voltage semiconductor transistor further comprises:
An NPN region is formed in the P-type body, and the NPN region extends downward from the surface of the P-type substrate, wherein the NPN region comprises two N-type heavily doped regions, and a P-type heavily doped region is located Between the two N-type heavily doped regions; and a polycrystalline germanium body and a first hole surrounding the polycrystalline germanium island, wherein the polycrystalline germanium island system is formed on the P-type heavily doped region of the NPN region, and the first The holes expose at least the N-type heavily doped regions of the NPN region;
Wherein the low voltage drain region of the normally open low voltage semiconductor transistor comprises:
An N-type heavily doped region is in the P-type body, and the N-type heavily doped region extends downward from the surface of the P-type substrate; and a second hole is formed in a polysilicon layer, and the second The hole exposes at least the N-type heavily doped region. [Item 10] The manufacturing method of claim 6, further comprising forming a patterned polysilicon layer in a substrate, wherein the patterned polysilicon layer comprises:
a polysilicon gate portion continuously formed as one of the low voltage gate of the normally-on low voltage semiconductor transistor and one of the high voltage gate of the high voltage semiconductor transistor;
The plurality of first holes and the plurality of second holes are alternately and separately arranged, wherein the first holes are opposite to a plurality of source/base regions of the normally open low voltage semiconductor transistor, and the second holes a plurality of drain regions corresponding to a normally open low voltage semiconductor transistor,
Each of the source/base regions includes a polycrystalline germanium body and one of the first holes surrounds the polycrystalline germanium island, and the polycrystalline germanium island is connected to one of the p-type P-types. a dummy region, wherein the first hole exposes at least two N-type heavily doped regions on both sides of the P-type heavily doped region,
Each of the drain regions includes an N-type heavily doped region located in a P-type body extending downward from the surface of the substrate, wherein the second hole exposes the N-type heavily doped region.