TWI708394B - Seimiconductor device with separate active region and method of fabricating the same - Google Patents

Abstract

The present disclosure provides a semiconductor device having a separate active region and a method of fabricating the same. The semiconductor device includes a substrate, a plurality of isolation islands, a source region, and a drain region. The substrate includes a first active region, a second active region, and a plurality of separate active regions. The separated active regions are connected to the first active region and the second active region, and are alternately disposed with the isolation islands. The gate structure includes a body portion and a plurality of extensions. The body portion disposed on a portion of the first active region. The extensions are coupled to the body portion and extend from the body portion to the plurality of isolation islands. The source region and the drain region are respectively located in the substrate in the first active region and the second active region.

Description

Semiconductor device with separated active area and manufacturing method thereof

The invention relates to a semiconductor device and a manufacturing method thereof.

High-voltage (HV) transistors (such as metal-oxide-semiconductor field-effect transistors (MOSFETs)) can act as high-voltage switching regulators and power management integrated circuits (integrated circuit, IC) in the high-voltage switch. In order to deal with the high voltages involved in these and other high voltage applications, it is desirable to make the high voltage transistors have high breakdown voltage and low on-resistance.

The present invention describes embodiments of semiconductor devices with separated active regions and methods for fabricating such devices, which can achieve high breakdown voltage and low on-resistance.

The embodiment of the present invention provides a semiconductor device including a substrate, a plurality of isolation islands, a gate structure, a source region and a drain region. The substrate includes a first active area, a second active area, and a plurality of separate active areas. The plurality of separate active regions extend in a first direction and are arranged in a second direction, are located between the first active region and the second active region, and are respectively connected to the first active region and the second active region.区连接。 Area connection. A plurality of isolation islands are located in the substrate and alternately arranged with the plurality of separate active regions in the second direction. The gate structure is located on the substrate. The gate structure includes a main body and a plurality of extensions. The main body portion extends in the second direction and is disposed on a part of the first active area. The plurality of extension portions are connected to the main body portion, extend from the main body portion in the first direction to the plurality of isolation islands, and are connected to the plurality of separate active areas in the second direction Set alternately on. The source region is located in the substrate of the first active region. The drain region is located in the substrate of the second active region.

The embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps. An isolation structure is formed in a substrate, the isolation structure includes a plurality of isolation islands, and the isolation structure defines a first active region, a second active region, and is located in the first active region and the second active region in the substrate Between the plurality of separate active regions, wherein the plurality of separate active regions extend in the first direction, are respectively connected to the first active region and the second active region, and are connected to the plurality of isolated islands in the second Alternately set in the direction. A gate structure is formed on the substrate. The gate structure includes a main body and a plurality of extensions. The main body portion extends in the second direction and is disposed on a part of the first active area. The plurality of extension portions are connected to the main body portion, extend from the main body portion to the first upward to the plurality of isolation islands, and alternate with the plurality of separate active regions in the second direction Set up. A source region is formed in the substrate of the first active region. A drain region is formed in the substrate of the second active region.

The semiconductor device of the embodiment of the present invention can achieve high breakdown voltage and low on-resistance.

The details of one or more disclosed embodiments are set forth in the drawings and the following description. Based on the description, drawings and the scope of patent application, other features, aspects and advantages will become obvious.

The embodiment of the present invention provides a semiconductor device. This semiconductor device is, for example, a high voltage transistor device with high breakdown voltage and low on-resistance. The high-voltage transistor device has a separate active region for separating the isolation structure between the source region and the drain region into a plurality of isolated islands.

The technology disclosed herein can optimize the on-resistance and breakdown voltage of the high-voltage transistor device without the need for an additional mask (such as a photoresist mask). High-voltage transistor devices can be fabricated by standard processes, such as the triple well process, bipolar-complementary metal-oxide-semiconductor (CMOS)- double-diffused metal-oxide-semiconductor (DMOS), BCD) process, non-epitaxially-grown layer (non-EPI) process with Mitsui process or twin well process (twin well process) and/or Single poly or double poly process (single poly or double poly process). The high-voltage transistor device may be a low-side switching metal oxide semiconductor (MOS) transistor, a high-side switching MOS transistor, a completely isolated switching MOS transistor, or a high-voltage low surface electric field (RESURF) LDMOS transistor. High-voltage transistors can be n-channel metal oxide semiconductor (n-channel MOS, NMOS) transistors, p-channel metal oxide semiconductor (p-channel MOS, PMOS) transistors, or complementary metal oxide semiconductor (CMOS) transistors . The technology can be applied to any suitable structure, any suitable process, and/or any suitable operating voltage. In addition to high-voltage devices, the technology can also be used for direct current (DC) applications and/or low-voltage applications.

The technique can be applied to any suitable transistor device in any suitable substrate. For illustration purposes only, some examples in the following description are about n-channel laterally diffused (LD) metal oxide semiconductor field effect transistors (or LDMOS transistors) as a type of high voltage transistor. The n-channel LDMOS transistor may be located in a p-type semiconductor substrate, or alternatively, may be located in a p-type epitaxial layer formed on the substrate. Some examples in the following description are about making a single transistor by a manufacturing process, or forming multiple transistors at the same time. In addition, in the following description, the p-type may be doped with boron or boron fluoride (BF ₂ ) dopants; the n-type may be doped with phosphorus or arsenic dopants, for example.

FIG. 1A shows a top view of an exemplary semiconductor device having a separate active region according to one or more embodiments. FIG. 1B shows an enlarged view of the area R in FIG. 1A. Fig. 2A is a cross-sectional view taken along the line I-I' of Fig. 1B. Fig. 2B is a cross-sectional view taken along the line II-II' of Fig. 1B. The two high voltage (HV) transistor devices in FIG. 1A share a source region. However, the high voltage transistor device of the present invention is not limited to this.

1A, 1B, 2A and 2B, the semiconductor device 10 is, for example, a high-voltage transistor device. The high-voltage transistor device may be an LDNMOS transistor or a drain extended NMOS transistor. The semiconductor device 10 is formed in a p-type semiconductor substrate 100. The p-type semiconductor substrate 100 may be a p-type silicon wafer or a p-type epitaxial layer formed on the substrate. The p-type semiconductor substrate 100 may have a p-type doping concentration of 10 ¹⁴ cm ^-3 to 10 ¹⁶ cm ^-3 .

In an embodiment, the semiconductor device 10 is configured to be completely isolated from the substrate 100 so as to be able to be biased independently. The semiconductor device 10 may include an n-type doped buried layer (NBL) 102 and an n-type well 108. The n-type deep well region 102 is also called an n-type doped buried layer. The n-type well area 108 is also called the first well area. The n-type deep well region 102 is configured to provide vertical isolation; the n-type well region 108 is configured to provide lateral isolation. In an embodiment, the n-type deep well region 102 may have an n-type doping concentration of 10 ¹⁶ cm ^-3 to 10 ¹⁹ cm ^-3 . The high voltage n-type well region 108 may have an n-type doping concentration of 10 ¹⁵ cm ^-3 to 10 ¹⁸ cm ^-3 .

An isolation structure 104 is formed in the p-type semiconductor substrate 100. The isolation structure 104 electrically isolates the semiconductor device 10 from other transistor devices and devices formed on the p-type semiconductor substrate 100. The isolation structure 104 is, for example, a shallow trench isolation (STI) or a thick field oxide (FOX) layer. The isolation structure 104 may include a single layer or multiple layers. The material of the isolation structure 104 includes silicon oxide, silicon nitride, or a combination thereof. The isolation structure 104 defines an active area AA in the substrate 100. The active area AA includes a first active area A1, a second active area A2, and a plurality of separate active areas SSA located between the first active area A1 and the second active area A2. The first active area A1 and the second active area A2 extend along the second direction D2 and are juxtaposed along the first direction D1. The plurality of divided active areas SSA extend along the first direction D1, connect the first active area A1 and the second active area A2, and are arranged along the second direction D2. In addition, the partition active area SSA also partitions the isolation structure 104 between the first active area A1 and the second active area A2 into a plurality of isolation islands IOI. The plurality of separate active areas SSA and the plurality of isolation islands 101 alternate with each other along the second direction D2. In some embodiments, the top views of the first active area A1, the second active area A2, the separated active area SSA, and the isolation island IOI are respectively rectangular, for example. The length L1 in the first direction of the first active area A1 is, for example, greater than the length L2 of the second active area A2 in the first direction.

In the semiconductor substrate 100, p-well regions 110 are implanted and diffused with a higher p-type doping concentration (for example, 10 ¹⁶ cm ^-3 to 10 ¹⁸ cm ^-3 ) than the p-type semiconductor substrate 100. The p-well area 110 is also called the second well area. The p-well area 110 partially overlaps the first active area A1. In the first active region A1 of the p-well region 110 is formed a heavily doped p+ body contact region 124 (for example, having a p-type doping concentration of 10 ¹⁹ cm ^-3 to 10 ²¹ cm ^-3 ) and a dense The doped n+ source region 122 (for example, has an n-type doping concentration of 10 ¹⁹ cm ⁻³ to 10 ²¹ cm ⁻³ ). The p+ body contact region 124 may be farther from the gate structure 118 (described in detail later) than the n+ source region 122. The p-well region 110 may extend laterally beyond the p+ body contact region 124 and the n+ source region 122, and extend vertically below the p+ body contact region 124 and the n+ source region 122. The p+ body contact region 124 and the n+ source region 122 are in direct electrical contact with each other.

In the p-type substrate 100, an n-type doping drift (NDD) region is implanted and diffused with a higher n-type doping concentration (for example, 10 ¹⁶ cm ^-3 to 10 ¹⁸ cm ^-3 ) (Alternatively called the doped region) 106. The isolation island IOI is located in the n-type doped drift region 106. The n-type doped drift region 106 may extend laterally toward the gate structure 118 and partially overlap the first active region A1, but is laterally separated from the p-well region 110. The n-type doped drift region 106 also extends in the direction of the second active region A2, so that the separated active region SSA and the second active region A2 completely overlap with it. The second active region A2 of the n-type doped drift region 106 contains a heavily doped n+ drain region 120 (for example, with an n-type doping concentration of 10 ¹⁹ cm ⁻³ to 10 ²¹ cm ⁻³ ). The n+ drain region 120 may be more heavily doped than the n-type doped drift region 106.

The gate structure 118 is placed on the substrate 100 between the n+ source region 122 and the n+ drain region 120.

The gate structure 118 includes a gate dielectric layer 112, a gate electrode 114 and a spacer 116. The gate dielectric layer 112 may include silicon oxide (SiO ₂ ) or a high-dielectric constant dielectric material (for example, a high-dielectric constant larger than that of silicon oxide (SiO ₂ ) (3.9)). The gate electrode 114 partially covers the p-well region 110 and the n-type doped drift region 106. The gate electrode 114 is separated from the semiconductor substrate 100, the p-well region 110 and the n-type doped drift region 106 by the gate dielectric layer 112. The gate electrode 114 may include doped polysilicon (poly) disposed on the gate dielectric layer 112. The spacer 116 is located on the side wall of the gate electrode 114. The spacer 116 may be a single layer or multiple layers, for example, including silicon oxide, silicon nitride, or a combination thereof.

1B, the gate structure 118 is, for example, comb-shaped. The gate structure 118 covers a part of the first active area A1 and a part of the isolation structure 104. In some embodiments, the gate structure 118 includes a body portion P1 and a plurality of extension portions P2. The main body P1 extends in the second direction D2, covering part of the first active area A1, so that the first active areas A1 on both sides of the main body P1 are exposed. The extension part P2 extends in the first direction D1 and is connected to the main body part P1. Each extension P2 covers part of the first active area A1 and part of the isolation island IOI. The plurality of extension parts P2 and the plurality of separate active areas SSA are alternately arranged in the second direction D2.

On the other hand, the gate structure 118 includes a plurality of long portions 118L and a plurality of short portions 118S. The plurality of long portions 118L and the plurality of short portions 118S alternate with each other in the second direction D2. The long portion 118L has a length L3 in the first direction D1; the short portion 118S has a length L4 in the first direction D1. The length L4 is equal to the length of the main body P1 in the first direction D1. The length L3 is equal to the sum of the length of the body portion P1 in the first direction D1 and the length of the extension portion P2 in the first direction D1.

2A, one side of the short portion 118S of the gate structure 118 exposes the n+ source region 122 and the p+ body contact region 124. The short portion 118S covers part of the p-well region 110, the substrate 100, and the n-type doped drift region 106 of the first part. The p-well area 110 covered by the short portion 118S and the surface of the substrate 100 serve as the channel area. One side of the short portion 118S of the gate structure 118 exposes the second portion of the n-type doped drift region 106 and the n+ drain region 120. There is no isolation structure in the n-type doped drift region 106, which can provide the semiconductor device 10 with low on-resistance.

In other words, the gate electrode 114 of the short portion 118S is adjacent to the n+ source region 122 at one end, and extends above the first portion of the n-type doped drift region 106 at the other end. The second portion of the n-type doped drift region 106 (from the other end of the gate electrode 114 to the n+ drain region 120) is adjacent to the first portion of the n-type doped drift region 106 and has a lateral distance D. The second portion of the n-type doped drift region 106 can be regarded as the drift region 109 for charge carriers to move from the n+ source region 122 to the n+ drain region 120. The on-resistance of the semiconductor device 10 is related to the doping concentration of the drift region 109 (that is, the concentration of the n-type doped drift region 106) and the lateral distance D. The higher the doping concentration of the drift region 109, the lower the on-resistance; the longer the lateral distance D, the higher the on-resistance.

2B, one side of the long portion 118L of the gate structure 118 exposes the n+ source region 122 and the p+ body contact region 124. The long portion 118L covers part of the p-well region 110, the substrate 100, and part of the isolation island 101. The p-well region 110 covered by the long portion 118L and the surface of the substrate 100 serve as a channel region. One side of the long portion 118L of the gate structure 118 exposes another part of the isolation island IOI and the n+ drain region 120. The arrangement of the isolation island IOI can provide the semiconductor device 10 with a high breakdown voltage.

The barrier (PRO) 126 is formed on the substrate 100, covers a plurality of separate active regions SSA and a plurality of isolation islands IOI, and exposes the first active region A1 and the second active region A2. In some embodiments, the barrier 126 covers the n-type doped drift region 106 and the isolation island IOI, and exposes the p+ body contact region 124, the n+ source region 122, the gate structure 118, and the n+ drain region 120. In other embodiments, the blocking portion 126 also covers a portion of the long portion 118L and a portion of the short portion 118S of the gate structure 118. The barrier 126 may be a single layer or multiple layers. The material of the blocking portion 126 includes silicon oxide, silicon nitride, or a combination thereof.

The metal silicide layer 130 is formed on the p+ body contact region 124, the n+ source region 122, the gate structure 118, and the n+ drain region 120 that are not covered by the barrier 126. The metal silicide layer 130 may include cobalt silicide, titanium nitride/titanium silicide, titanium nitride/titanium/cobalt silicide, polycrystalline cobalt silicide or titanium nitride/polycrystalline titanium silicide, titanium nitride/titanium/polycrystalline cobalt silicide.

The embodiment of the present invention can optimize the on-resistance and breakdown voltage of the semiconductor device 10 by changing and designing the length and width of the separation active region SSA and the plurality of isolation islands IOI, and the doping concentration of the drift region 109. For example, increasing the doping concentration of the drift region 109, shortening the length of the separated active region SSA in the first direction D1 or increasing the ratio of the length of the separated active region SSA to the isolation island IOI in the second direction D2 can reduce the semiconductor device 10 on resistance. On the contrary, the breakdown voltage of the semiconductor device 10 can be increased.

3A to 3E are top views showing an exemplary manufacturing process for manufacturing a semiconductor device according to an embodiment of the present invention. 4A to 4E show cross-sectional views taken along the line III-III' in FIGS. 3A to 3E. Fig. 4F shows a cross-sectional view taken along the line IV-IV' in Fig. 3E.

3A and 4A, an n-type deep well region 102 is formed in the substrate 100. The substrate 100 is, for example, a p-type semiconductor substrate, such as a p-type silicon substrate. The method for forming the n-type deep well region 102 is, for example, forming an ion implantation mask on the substrate 100, and then performing an ion implantation process to implant n-type dopants into the substrate 100. After that, the implant mask is removed.

Next, an isolation structure 104 is formed in the substrate 100. The isolation structure 104 includes a plurality of isolation islands IOI. The formation method of the isolation structure 104 is, for example, a shallow trench isolation method. The steps of the shallow trench isolation method are as follows. A plurality of trenches are formed in the substrate 100 by lithography and etching processes. After that, an insulating material is formed on the substrate 100 and in the trench. Then, a planarization process is performed by a chemical mechanical polishing method or an etching back method to remove the insulating material on the substrate 100. The insulating material includes silicon oxide, silicon nitride, or a combination thereof formed by chemical vapor deposition or thermal oxidation. The isolation structure 104 defines an active area AA in the substrate 100. The active area AA includes a first active area A1, two second active areas A2, and a plurality of separate active areas SSA. The first active area A1 is located between the two second active areas A2. The separate active areas SSA are respectively located between the first active area A1 and the second active area A2.

3B and 4B, an n-type doped drift region 106, an n-type well region 108, and a p-well region 110 are formed in the substrate 100 above the n-type deep well region 102. The doping concentration of the n-type well region 108 may be the same as the doping concentration of the n-type deep well region 102, and slightly higher or slightly lower than the doping concentration of the n-type deep well region 102. The n-type well region 108 and the p-well region 110 can form an implantation mask on the substrate 100, and then perform an ion implantation process to implant the n-type dopant and the p-type dopant into the substrate 100 respectively. After that, the implant mask is removed. The n-type well region 108 partially overlaps the second active region A2, a plurality of separated active regions SSA, and the isolation structure 104. The n-type well region 108 may be annular, and the bottom surface of the n-type well region 108 is deeper than the bottom surface of the isolation structure 104 and is adjacent to the top surface of the n-type deep well region 102. Therefore, the n-type well region 108 and the n-type deep well region 102 can jointly enclose an independent region, and the transistor device formed in this independent region can be completely isolated from the substrate 100 to be able to be biased independently.

3B and 4B, the doping concentration of the n-type doped drift region 106 may be slightly higher than the doping concentration of the n-type well region 108. The n-type doped drift region 106 may form an implantation mask on the substrate 100, and then perform an ion implantation process to implant n-type dopants into the substrate 100. After that, the implant mask is removed. The implant mask has two openings O1. The opening O1 exposes part of the first active area A1, and exposes a plurality of separated active areas SSA, a plurality of isolation islands 101, two second active areas A2, and a part of the isolation structure 104 adjacent to the second active area A2. Therefore, the n-type doped drift region 106 partially overlaps the first active region A1, completely overlaps the plurality of separate active regions SSA, the plurality of isolation islands IOI, and the two second active regions A2, and overlaps the n-type well region 108 And the isolation structure 104 partially overlaps. The n-type doped drift region 106 extends vertically downward from the surface of the substrate 100 until its bottom surface is adjacent to the top surface of the n-type deep well region 102 (as shown in FIG. 3B), or between the top surface of the n-type deep well region 102 and Between the bottom surfaces of the isolation island IOI (not shown). In other words, the n-type doped drift region 106 surrounds a plurality of isolation islands IOI.

The doping concentration of the p-well region 110 is slightly higher than the doping concentration of the substrate 100. The p-well regions 110 can respectively form implantation masks on the substrate 100, and then perform an ion implantation process to implant n-type dopants in the substrate 100. After that, the implant mask is removed. The implant mask has an opening O2. The opening O2 exposes part of the central area of the first active area A1. The n-type doped drift region 106 partially overlaps the first active region A1 and is laterally separated from the p-well region 110. The p-well region 110 extends vertically downward from the surface of the substrate 100, but its bottom surface is not adjacent to the top surface of the n-type deep-well region 102, but is longitudinally separated. For the sake of brevity of the drawing, FIGS. 3C and 3D will no longer show the p-well region 110 and the opening O2.

Referring to FIG. 3C and FIG. 4C, two gate structures 118 are formed on the substrate 100. The gate structure 118 includes a gate dielectric layer 112, a gate electrode 114 and a spacer 116. The gate structure 118 is formed, for example, by forming a gate dielectric material layer and a gate electrode material layer on the substrate 100, and then patterning the gate dielectric material layer and the gate electrode material layer through a lithography and etching process. After that, a spacer material layer is formed, and then an anisotropic etching process is performed on the spacer material layer. The gate structure 118 is, for example, comb-shaped (as shown in FIG. 3C). The gate structure 118 includes a plurality of long portions 118L and a plurality of short portions 118S that alternate with each other in the second direction D2. The multiple long portions 118L and multiple short portions 118S of the gate structure 118 cover part of the p-well region 110, part of the n-type doped drift region 106, and part of the multiple isolation islands IOI. A part of the isolation island IOI is covered by the long part 118L, and another part of the isolation island IOI is exposed by the long part 118L of the gate structure 118. The isolation island IOI is not covered by the short portion 118S of the gate structure 118.

3C and 4C, a p + body contact region 124 and an n + source region 122 are formed in the first active region A1, and an n + drain region 120 is formed in the two second active regions A2. The doping concentration of the p+ body contact region 124 is higher than the doping concentration of the p-well region 110. The doping concentration of the n+ source region 122 and the n+ drain region 120 is higher than the doping concentration of the n-type doped drift region 106. The p+ body contact region 124, the n+ source region 122 and the n+ drain region 120 can respectively form an implantation mask on the substrate 100, and then perform an ion implantation process to implant p-type or n-type dopants in the substrate 100 . After that, the implant mask is removed. The n+ source region 122 and the n+ drain region 120 can be formed at the same time.

3D and 4D, a barrier (PRO) 126 is formed on the substrate 100 to cover part of the gate structure 118, the n-type doped drift region 106 in the plurality of separate active regions SSA, and the plurality of isolation islands IOI , The other part of the gate structure 118, the p+ body contact region 124 and the n+ source region 122 in the first active region A1, and the n+ drain region 120 in the second active region A2 are exposed. In some embodiments, the blocking portion 126 does not cover the gate electrode 114 (not shown) of the gate structure 118.

3E, 4E, and 4F, a self-aligned silicidation process is performed to form a metal silicide layer 130 on the gate electrode 114, the p+ body contact region 124, the n+ source region 122, and the n+ drain region 120.

FIG. 5 is a graph of the drain electrical characteristics of the semiconductor device of the present invention and the conventional semiconductor device.

Please refer to FIG. 5, the semiconductor device of the present invention has smooth drain saturation current curves C1, C2, C3, and C4. The saturation current curves C1' and C2' of the conventional semiconductor device are quite steep. It can be seen from FIG. 5 that, compared with the prior art, the semiconductor device of the present invention has a smoother saturation current curve.

In the embodiment of the present invention, by forming a plurality of separate active regions SSA connecting the first active region and the second active region, the current at the short part of the gate electrode can flow through the separated active region SSA in a shorter path. The drift region of low and medium resistance can reduce the on-resistance of the transistor device. Through experiments, the on-resistance of the conventional semiconductor device is about 14 ohm-square millimeter, and the on-resistance of the semiconductor device of the present invention can be reduced to 9.4 ohm-square millimeter.

In addition, through the arrangement of multiple isolation islands IOI between the first active region and the second active region, the transistor device can be maintained at a predetermined breakdown voltage.

In addition, the long portion of the gate electrode extends to a plurality of isolation islands IOI, which can be used as a partial field plate to uniform electric field.

Therefore, the embodiments of the present invention may not need to add additional photomasks and manufacturing processes. By changing and designing the length and width of the separation active region SSA and the plurality of isolation islands IOI, the length of the gate electrode, and the doping concentration of the drift region, The on-resistance and breakdown voltage of the transistor device are optimized.

Although this document may elaborate many details, these details should not be construed as limiting the scope of the claimed invention or the claimed content, but merely describing the unique features of the specific embodiment. Certain features described in this document in the context of separate embodiments can also be implemented in a single embodiment in combination. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although each feature may be described above as functioning in certain combinations and even initially claimed as such, one or more features in the claimed combination may be removed from the combination in some cases, and so It is claimed that the combination can be changed into a sub-combination or a variation of the sub-combination. Similarly, although the operations are depicted in a specific order in the drawings, this should not be understood as a requirement: these operations should be performed in the specific order shown or in a sequential order, or all the operations described should be performed, To achieve the desired result.

This article only discloses a few examples and embodiments. The examples and embodiments and other embodiments can be changed, modified, and enhanced based on the disclosed content.

10: Semiconductor device 100: base 102: n-type deep well area 104: Isolation structure 106: n-type doped drift region 108: n-type well area 109: Drift Zone 110:p well area 112: gate dielectric layer 114: gate electrode 116: Clearance Wall 118: Gate structure 118L: Long part 118S: short part 120: n+ drain area 122: n+ source region 124: p+ body contact area 126: Block 130: metal silicide layer A1: The first active area A2: The second active area AA: active area D: Horizontal distance D1: First direction D2: second direction IOI: Isolation Island O1, O2: opening P1: Main body P2: Extension R: area SSA: separate active area C1, C1’, C2, C2’, C3, C4: Curve L1, L2, L3, L4: length I-I’, II-II’, III-III, IV-IV’: Tangent

FIG. 1A shows a top view of a semiconductor device having a divided active region according to one or more embodiments. FIG. 1B shows an enlarged view of the area R in FIG. 1A. Fig. 2A is a cross-sectional view taken along the line I-I' of Fig. 1B. Fig. 2B is a cross-sectional view taken along the line II-II' of Fig. 1B. 3A to 3E are top views showing an exemplary manufacturing process for manufacturing a semiconductor device according to an embodiment of the present invention. 4A to 4E show cross-sectional views taken along the line III-III' in FIGS. 3A to 3E. Fig. 4F shows a cross-sectional view taken along the line IV-IV' in Fig. 3E. FIG. 5 is a graph of the drain electrical characteristics of the semiconductor device of the present invention and the conventional semiconductor device.

118: Gate structure

126: Block

130: metal silicide layer

A1: The first active area

A2: The second active area

AA: active area

D1: First direction

D2: second direction

IOI: Isolation Island

L1, L2, L3, L4: length

P1: Main body

P2: Extension

SSA: separate active area

I-I’, II-II’: Tangent

Claims (10)

A semiconductor device includes: a substrate, including: a first active region; a second active region; and a plurality of separate active regions, extending in a first direction and arranged in a second direction, located between the first active region and Between the second active regions and respectively connected to the first active region and the second active region; a plurality of isolation islands, located in the substrate, alternate with the plurality of separated active regions in the second direction Provided; a gate structure located on the substrate, the gate structure comprising: a main body part extending in the second direction and disposed on part of the first active region; a plurality of extension parts, and the The main body portion is connected, extends from the main body portion to the plurality of isolation islands in the first direction, and is alternately arranged with the plurality of separate active regions in the second direction; the source region is located at the In the substrate of the first active region; and a drain region in the substrate of the second active region. According to the semiconductor device described in claim 1, wherein the gate structure is comb-shaped. The semiconductor device according to claim 1, wherein the gate structure includes a plurality of long portions and a plurality of short portions that alternate with each other, and the plurality of long portions Alternate with a plurality of separate active regions, and cover part of the plurality of isolation islands, and the plurality of short portions do not cover part of the plurality of isolation islands. The semiconductor device described in item 1 of the scope of the patent application further includes: a doped region located in the substrate, wherein the plurality of isolation islands and the drain region are located in the doped region, and the The gate structure covers part of the doped region. The semiconductor device according to claim 4, further comprising: a first well region located in the substrate, wherein the first well region partially overlaps the doped region, and the drain region and Part of the plurality of isolation islands is located in the first well region; a second well region is located in the substrate, wherein the second well region and the first well region have different conductivity types, and the The source region is located in the second well region, and the body portion of the gate structure covers a portion of the second well region; and a doped buried layer is located in the substrate and is separated from the first well region. The well area extends below the second well area and is electrically connected to the first well area. The semiconductor device described in claim 1 further includes a barrier layer covering the plurality of separate active regions between the main body portion and the drain region of the gate structure, and Covering part of the substrate of the first active region; and a metal silicide layer located on the source region, the drain region, and the gate structure. A method for manufacturing a semiconductor device includes: forming an isolation structure in a substrate, the isolation structure including a plurality of isolation structures Island, the isolation structure defines a first active region, a second active region, and a plurality of separate active regions between the first active region and the second active region in the substrate, wherein the plurality of separate active regions The active region extends in the first direction, is respectively connected to the first active region and the second active region, and is alternately arranged with a plurality of isolation islands in the second direction; a gate structure is formed on the substrate, the The gate structure includes: a main body part that extends in the second direction and is disposed on a part of the first active region; a plurality of extension parts connected to the main body part, from the main body part to the second Extending to the plurality of isolation islands in one direction, and being alternately arranged with the plurality of separate active regions in the second direction; forming a source region in the substrate of the first active region; and A drain region is formed in the substrate of the second active region. The method for manufacturing a semiconductor device as described in claim 7 further includes forming a doped region in the substrate, wherein the plurality of isolation islands and the drain region are located in the doped region, and The gate structure covers part of the doped region. The method for manufacturing a semiconductor device as described in claim 8 further includes: forming a doped buried layer in the substrate; forming a first well region in the substrate, wherein the first well region is The doped buried layer is connected and partially overlaps the doped region, and the drain region is located The first well region; a second well region is formed in the substrate, wherein the second well region and the first well region have different conductivity types, and the source region is located in the second In the well region, the main body of the gate structure covers part of the second well region. The method for manufacturing a semiconductor device as described in the seventh item of the scope of the patent application further includes: forming a barrier layer on the substrate to cover the gap between the main body portion and the drain region of the gate structure Forming a metal silicide layer on the substrate separating the active regions and a portion of the first active region; and forming a metal silicide layer on the body portion of the source region, the drain region, and the gate structure .

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