201017880 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種靜電放電防護裝置，特別是有關 於一種閘極絕緣雙接面電晶體(IGB T)靜電放電防護元件。 【先前技術】 傳統高電壓靜電放電（Electrostatic Discharge，簡稱 Φ ESD)防護元件包括橫向擴散金氧半功率電晶體(LDM0S Power Transistor)、金氧半電晶體(M0SFET)、石夕控整流器 (SCR)、雙載子電晶體(BJT)、二極體(Diode)和場氧化電晶 體(Field Oxide Device，FOD)。在高壓靜電放電防護上由 於其過高的觸發電壓（trigger voltage)和過低的持有電壓 (holding voltage)，不是造成内部電路先損壞就是造成問鎖 效應(latch-up)發生，所以要加上額外的驅動電路或是透過 調變佈局參數(layout parameter)去使觸發電壓降低和使持 φ 有電壓超過元件之工作電壓（operation voltage)，如此才可 作為高壓靜電放電防護元件。 在傳統的超高壓元件(ultra-HV device)中，往往利用絕 緣層上有矽(SOI)基底及其相關的製程，隔離個別的元件， 以減少因高壓操作造成元件間的寄生效應。而利用絕緣層 上有矽（SOI)基底及其相關的製程對ESD元件的散熱造成 不利的影響，因此業界亟需有效地處理ESD元件的散熱問 題。尤其是，在超高壓元件的製程中’井區（well)的控散濃 度均偏低，使得相對的阻抗也就偏高，不利於ESD元件的 97010 /0516-A41790TW/fmal 6 201017880 更均勻一致的啟動（uniform turn-on)。 【發明内容】 有鑑於此，為了克服上述先前技術的缺點，因而利用 閘極絕緣雙接面電晶體（IGBT)元件做為靜電放電防護元 件，並改良IGBT元件的汲極區域的佈局，使其能夠更均 勻一致的啟動，以提升ESD的保護效能。 本發明之一實施例提供一種閘極絕緣雙接面電晶體 φ (IGBT)靜電放電防護元件包括：一半導體基底；一圖案化 的隔離區設置於該半導體基底上，定義一第一主動區及一 第二主動區；一高壓N-型井區於該半導體基底的該第一主 動區中；一 P-型體摻雜區於該半導體基底的該第二主動區 中，其中該高壓N-型井區和該P-型體摻雜區相隔一特定距 離，露出該半導體基底；一 P-型濃摻雜汲極區設置於該高 壓N-型井區中；一對相鄰的一 N-型和一 P-型濃摻雜源極 區設置於該P-型體摻雜區中；以及一閘極結構於該半導體 φ 基底上，其一端與該N-型濃摻雜源極區相接，其另一端延 伸至該圖案化的隔離區上。 本發明另一實施例提供一種閘極絕緣雙接面電晶體 (IGBT)靜電放電防護元件包括：一半導體基底；一高壓N-型井區於該半導體基底中；一圖案化的隔離區設置於該高 壓N-型井區上，定義一第一主動區及一第二主動區；一 N-型雙擴散區設置於該高壓N-型井區的該第一主動區 中；一 P-型濃摻雜汲極區設置於該N-型雙擴散區中；一 P-型體摻雜區於該高壓N-型井區的該第二主動區中，其中 97010 / 0516-A41790TW/final 7 201017880 該N-型雙擴散區和該P-型體摻雜區相隔一特定距離，露出 該高壓N-型井區；一對相鄰的一 N-型和一 P-型濃摻雜源 極區設置於該P-型體摻雜區中；以及一閘極結構於該高壓 N-型井區上，其一端與該N-型濃摻雜源極區相接，其另一 端延伸至該圖案化的隔離區上。 本發明又一實施例提供一種閘極絕緣雙接面電晶體 (IGBT)靜電放電防護元件包括：一半導體基底；一高壓N-型井區於該半導體基底中；一圖案化的隔離區設置於該高 ❹ 壓N-型井區上，定義一第一主動區及一第二主動區；一 P-型雙擴散區設置於該高壓N-型井區的該第一主動區中；一 P-型濃摻雜汲極區設置於該P-型雙擴散區中；一 P-型體摻 雜區於該高壓N-型井區的該第二主動區中，其中該P-型雙 擴散區和該P-型體摻雜區相隔一特定距離，露出該高壓N-型井區；一對相鄰的一 N-型和一 P-型濃摻雜源極區設置於 該P-型體摻雜區中；以及一閘極結構於該高壓N-型井區 上，其一端與該N-型濃摻雜源極區相接，其另一端延伸至 ® 該圖案化的隔離區上。 本發明又一實施例提供一種閘極絕緣雙接面電晶體 (IGBT)靜電放電防護元件包括：一半導體基底；一高壓P-型井區於該半導體基底中；一高壓N-型井區於該半導體基 底中；一圖案化的隔離區設置於該半導體基底上，定義一 第一主動區於該高壓N·型井區及一第二主動區和一第三 主動區於該高壓P-型井區；一 P-型濃摻雜汲極區設置於該 第一主動區中；一 N-型濃摻雜源極區設置於該第二主動區 97010 /0516-A41790TW/final 8 201017880 中，且一 p-型濃摻雜源極區設置於該第三主動區中；以及 一閘極結構於該高壓P-型井區上，其一端與該N-型濃摻雜 源極區相接，其另一端延伸至該圖案化的隔離區上。 本發明再一實施例提供一種閘極絕緣雙接面電晶體 (IGBT)靜電放電防護元件包括：一半導體基底；一圖案化 的隔離區設置於該半導體基底上，定義一第一主動區及一 第二主動區；一閘極結構設置於該半導體基底的該第一主 動區上；一 N-型雙擴散區位於該閘極結構的一側，且設置 © 該半導體基底的該第一主動區中；一 N-型井區設置於該 N-型雙擴散區中，其底部延伸至該半導體基底；一 P-型濃 摻雜汲極區設置於該N-型井區中；一 N-型濃摻雜源極區設 置於該閘極結構的另一侧的該半導體基底中；以及一 P-型 濃擴散區設置於該半導體基底的該第二主動區中。 為使本發明之上述目的、特徵和優點能更明顯易懂，下文特 舉較佳實施例，並配合所附圖式，作詳細說明如下： ^ 【實施方式】 以下以各實施例詳細說明並伴隨著圖式說明之範例， 做為本發明之參考依據。在圖式或說明書描述中，相似或 相同之部分皆使用相同之圖號。且在圖式中，實施例之形 狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式 中各元件之部分將以分別描述說明之，另外，特定之實施 例僅為揭示本發明使用之特定方式，其並非用以限定本發 明。 第1A圖係顯示根據本發明之一實施例的閘極絕緣雙 97010 / 0516-A41790TW/final 9 201017880 接面電晶體(IGBT)靜電放電防護元件的剖面示意圖。於第 1A圖中，一閘極絕緣雙接面電晶體(IGBT)靜電放電防護 (ESD)元件100a包括一半導體基底110以及一圖案化的隔 離區130a、130b、130c設置於該半導體基底110上，定義 一第一主動區OD1及一第二主動區OD2。根據本發明之一 實施例，該半導體基底110為一絕緣層上有矽（SOI)基底， 例如一 P-型矽基底101，其上有一埋藏氧化層102，和一 P-型蟲晶層103形成於埋藏氧化層102上。一隔離區1〇5 ® 使IGBT-ESD元件100a與基底110上的其他元件隔離。 一高壓N-型井區115形成於該半導體基底的該第一主 動區OD1中，一 P-型體摻雜區120於該半導體基底的該第 二主動區OD2中，其中該高壓N-型井區115和該p-型體 摻雜區120相隔一特定距離，露出該半導體基底。一擴散 區113自該南壓N-型井區115向該P-型體捧雜區12〇延伸 靠近。一 P-型濃摻雜汲極區117設置於該高壓N_型井區 鲁 115中，以及汲極電極145a、145b與該P-型濃摻雜汲極區 1Π電性接觸。一對相鄰的一 N-型濃摻雜源極區124和一 P-型濃擴散區122設置於該P-型體摻雜區12〇中，源極電 極135a、135b分別與N-型濃摻雜源極區124和p-型濃擴 散區122電性接觸。一閘極結構140於該半導體基底上， 其一端與該N-型濃摻雜源極區124相接，其另_端延伸至 該圖案化的隔離區130b上。 根據本發明之一實施例’ P-型濃摻雜汲極區117的面 積可大於第一主動區0D1’但小於高壓N-型井區115的面 97010 / 0516-A41790TW/final 201017880 積’其平面佈局如第1B圖所示β 第2Α圖係顯示根據本發明另一實施例的IGBT-ESD元 件的剖面示意圖。於第2α圖中，IGBT-ESD元件100b與 第1A圖的IGBT-ESD元件1〇〇a實質上相同，為求簡明之 故’在此省略相同的敘述。不同之處在於，p_型濃摻雜汲 極區217a的面積小於該高壓N_型井區115的面積，其平 面佈局如第2B圖所示。在高壓型井區115中’高壓N-型井區115與P-型濃摻雜汲極區217a之間，存在一異型摻 ® 雜的介面’可分散並降低ESD電壓約0.7V。根據本發明另 一實施例，P-型濃摻雜汲極區217b為複數個分離的島區， 設置於高壓N-型井區115中，其平面佈局如第2C圖所示。 由於各個島區217b與高壓N-型井區115之間，皆存在一 異型摻雜的介面’可分散並降低ESD電壓，使得IGBT-ESD 元件能的更均勻一致的啟動（uniform turn-on)。 第3 A圖係顯示根據本發明又一實施例的IGBT-ESD元 件的剖面示意圖。於第3A圖中，一 IGBT-ESD元件300a ’ 包括一半導體基底310，例如P-型矽基底，及一高壓N-型 井區315設置於該半導體基底310中。一圖案化的隔離區 330a、330b、330c設置於該高壓N-型井區315上，定義一 第一主動區及一第二主動區。一 N-型雙擴散區316a設置 於高壓N-型井區315的第一主動區中，一 P-型濃摻雜汲極 區317設置於N-型雙擴散區316a中。一 P-型體摻雜區320 設置於該高壓N-型井區315的第二主動區中，其中該N-型雙擴散區316a和該P-型體摻雜區320相隔一特定距離， 97010 / 0516-A41790TW/final 11 201017880 露出該高壓N-型井區。一對相鄰的一 N-型濃摻雜源極區 324和一 P-型濃擴散區322設置於該P-型體摻雜區320 中。一閘極結構340於該高壓N-型井區315上’其一端與 該N-型濃摻雜源極區324相接，其另一端延伸至該圖案化 的隔離區330b上。 第3B圖係顯示根據本發明又一實施例的IGBT-ESD元 件的剖面示意圖。於第3B圖中，一 IGBT-ESD元件300b 與第3A圖的IGBT-ESD元件300a實質上相同，為求簡明 之故，在此省略相同的敘述。不同之處在於，IGBT-ESD 元件300b具有一 P-型雙擴散區316b設置於高壓N-型井區 315的第一主動區中，一 p_型濃摻雜汲極區317設置於該 P-型雙擴散區316b中。由於P-型濃摻雜汲極區317和P-型雙擴散區316b皆為P-型摻雜，因此更能增進ESD元件 的效能。 第4A圖係顯示根據本發明又一實施例的IGBT-ESD元 件的剖面示意圖。於第4A圖中，一 IGBT-ESD元件400a 包括一半導體基底410, 一高壓N-型井區415b於該半導體 基底中’ 一高壓P-型井區415c於該半導體基底中。一圖案 化的隔離區430a-430d設置於該半導體基底上，定義一第 一主動區於該高壓N-型井區415b及一第二主動區和一第 三主動區於該高壓P-型井區415c。高壓P·型井區415a設 置於隔離區430a下方。一 P-型濃摻雜沒極區417設置於該 第一主動區中’一 N-型濃摻雜源極區424設置於該第二主 動區中，且一 P-型濃摻雜擴散區422設置於該第三主動區 97010 /0516-A41790TW/final 12 201017880 中。一閘極結構440於該高壓p_型井區415c上，其一端與 該N-型濃摻雜源極區424相接，其另一端延伸至該圖案化 的隔離區430b上。 第4B圖係顯示根攄本發明又一實施例的IGBT_ESD元 件的剖面示意圖。於第4B圖中，一 igbt_ESd元件4〇〇b 包括一半導體基底410，例如一[型矽基底4〇1，其上有 一 P-型磊晶層403，以及一义型埋藏層4〇2設置於該p_ 型矽基底401與該P-型磊晶層4〇3之間。一高壓N_型井區 ❿ 415b於該半導體基底中，一高壓p_型井區415c於該半導 體基底中。一圖案化的隔離區430a-430f設置於該半導體 基底上’定義一第一主動區於該高壓N-型井區415b及一 第二主動區和一第三主動區於該高壓P-型井區415c。高壓 N-型井區415d設置於隔離區430e下方。一；P-型濃摻雜汲 極區417設置於該第一主動區中，一 N-型濃摻雜源極區424 設置於該第二主動區中，且一 P-型濃摻雜擴散區422設置 於該第三主動區中。再者，一額外的P·型濃摻雜區416設 ® 置於高壓P-型井區415a中，及一額外的P-型濃摻雜區426 設置於高壓P-型井區415e中。一閘極結構440於該高壓 P-型井區415c上，其一端與該N-型濃摻雜源極區424相 接，其另一端延伸至該圖案化的隔離區430c上。 第5圖係顯示根據本發明再一實施例的IGBT-ESD元 件的剖面示意圖。於第5圖中，一 IGBT-ESD元件500包 括：一半導體基底510,及一圖案化的隔離區530a-530c 設置於該半導體基底510上，定義一第一主動區及一第二 97010 /0516-A41790TW/final 13 201017880 主動區。一閘極結構540設置於該半導體基底的該第一主 動區上，一 N·型雙擴散區516位於該閘極結構54〇的一 側’且汉置該半導體基底510的該第一主動區中。'一 N-型井區515設置於該N-型雙擴散區516中’其底部延伸至 該半導體基底510, 一 型濃摻雜汲極區517設置於該N-型井區515中。一 N_型濃摻雜源極區524設置於該閘極結 構540的另一側的該半導體基底中，一义型輕摻雜(NLDD) 區524’延伸至該閘極結構54〇的間隙壁下方。一 p_型濃擴 ❹散區522 §免置於該半導體基底的該第二主動區中。 應注意的是，本發明各實施例的IGBT_ESD元件的 型濃摻雜没極區的面積小於該高壓N_型井區的面積，使得 高壓N-型井區與型濃摻雜汲極區之間，存在一異型摻雜 的介面’可分散並降低ESD電壓約〇.7V。更有甚者，P-型濃摻雜沒極區為複數個分離的島區，設置於高壓N_型井 區中’使得各個島區與高壓N_型井區之間，皆存在一異型 ❿ 摻雜的介面，可分散並降低ESD電壓，使得IGBT-ESD元 件能的更均勻一致的啟動(uniform turn_on)。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍’任何所屬技術領域中具有通常知識者，在 不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 【圖式簡單說明】 第1A圖係顯示根據本發明之一實施例的閘極絕緣雙 97010 / 0516-A41790TW/final 201017880 接面電晶體(IGBT)靜電放電防護元件的剖面示意圖； 第1B圖係顯示第1A圖的IGBT-ESD元件的第一主動 區的平面佈局； 第2A圖係顯示根據本發明另一實施例的IGBT-ESD元 件的剖面示意圖； 第2B和2C圖分別顯示第2A圖的IGBT-ESEf元件的 第一主動區不同實施例的平面佈局； 第3A圖係顯示根據本發明又一實施例的IGBT-ESD元 ® 件的剖面示意圖； 第3B圖係顯示根據本發明又一實施例的IGBT-ESD元 件的剖面示意圖； 第4A圖係顯示根據本發明又一實施例的IGBT-ESD元 件的剖面示意圖； 第4B圖係顯示根據本發明又一實施例的IGBT-ESD元 件的剖面示意圖；以及 第5圖係顯示根據本發明再一實施例的IGBT-ESD元 ®件的剖面示意圖。 【主要元件符號說明】 100a、100b、300a、300b、400a、400b、500〜IGBT-ESD 元件； 101、401~ P-型矽基底； 102〜埋藏氧化層； 402〜N-型埋藏層； 103、403~ P-型磊晶層； 97010 /0516-A41790TW/fmal 15 201017880 105〜隔離區； 110、310、410、510〜半導體基底； 115、315、415匕、415(1、515〜高壓1^-型井區； 415a、415c、415e〜高壓P-型井區； 316a、516〜N-型雙擴散區； 316b〜P-型雙擴散區； 416〜額外的P-型濃摻雜區；201017880 IX. Description of the Invention: [Technical Field] The present invention relates to an electrostatic discharge protection device, and more particularly to a gate insulated double junction transistor (IGB T) electrostatic discharge protection device. [Prior Art] Traditional high voltage electrostatic discharge (Electrostatic Discharge, Φ ESD) protection components include laterally diffused gold oxide half power transistor (LDM0S Power Transistor), gold oxide semi-transistor (M0SFET), and stone-controlled rectifier (SCR) , Bi-carrier transistor (BJT), diode (Diode) and Field Oxide Device (FOD). In the high-voltage electrostatic discharge protection, due to its excessive trigger voltage and low holding voltage, it is not caused by internal circuit damage or latch-up, so it is necessary to add The additional driver circuit can be used as a high voltage ESD protection component by adjusting the layout parameter to lower the trigger voltage and holding the voltage above the operating voltage of the component. In conventional ultra-HV devices, a germanium-on-insulator (SOI) substrate and its associated process are often utilized to isolate individual components to reduce parasitic effects between components due to high voltage operation. The use of a germanium (SOI) substrate on the insulating layer and its associated processes adversely affects the heat dissipation of the ESD components, so there is an urgent need in the industry to effectively address the heat dissipation of ESD components. In particular, in the process of ultra-high voltage components, the well control concentration of the well is low, so that the relative impedance is high, which is not conducive to the ESD component 97010 /0516-A41790TW/fmal 6 201017880 more uniform Start (uniform turn-on). SUMMARY OF THE INVENTION In view of the above, in order to overcome the disadvantages of the prior art described above, a gate insulated double junction transistor (IGBT) element is used as an electrostatic discharge protection element, and the layout of the drain region of the IGBT element is improved. Enables more uniform startup to improve ESD protection. An embodiment of the present invention provides a gate insulated double junction transistor φ (IGBT) electrostatic discharge protection device including: a semiconductor substrate; a patterned isolation region disposed on the semiconductor substrate, defining a first active region and a second active region; a high voltage N-type well region in the first active region of the semiconductor substrate; a P-type body doped region in the second active region of the semiconductor substrate, wherein the high voltage N- The well region and the P-type body doped region are separated by a specific distance to expose the semiconductor substrate; a P-type densely doped drain region is disposed in the high voltage N-type well region; a pair of adjacent one N a -type and a P-type heavily doped source region are disposed in the P-type body doped region; and a gate structure is on the semiconductor φ substrate, one end thereof and the N-type heavily doped source region Docked, the other end extends to the patterned isolation region. Another embodiment of the present invention provides a gate insulated double junction transistor (IGBT) electrostatic discharge protection component comprising: a semiconductor substrate; a high voltage N-type well region in the semiconductor substrate; a patterned isolation region disposed on a first active region and a second active region are defined on the high-pressure N-type well region; an N-type double diffusion region is disposed in the first active region of the high-pressure N-type well region; a P-type a concentrated doped drain region is disposed in the N-type double diffusion region; a P-type body doped region is in the second active region of the high voltage N-type well region, wherein 97010 / 0516-A41790TW/final 7 201017880 The N-type double diffusion region and the P-type body doped region are separated by a specific distance to expose the high voltage N-type well region; a pair of adjacent one N-type and one P-type concentrated dopant source a region is disposed in the P-type body doped region; and a gate structure is disposed on the high voltage N-type well region, one end of which is connected to the N-type heavily doped source region, and the other end thereof extends to the Patterned isolation area. A further embodiment of the present invention provides a gate insulated double junction transistor (IGBT) electrostatic discharge protection component comprising: a semiconductor substrate; a high voltage N-type well region in the semiconductor substrate; a patterned isolation region disposed on a first active region and a second active region are defined on the high-pressure N-type well region; a P-type double diffusion region is disposed in the first active region of the high-pressure N-type well region; a type-rich doped drain region is disposed in the P-type double diffusion region; a P-type body doped region is in the second active region of the high voltage N-type well region, wherein the P-type double diffusion The region and the P-type body doped region are separated by a specific distance to expose the high voltage N-type well region; a pair of adjacent N-type and a P-type heavily doped source region are disposed in the P-type In the body doped region; and a gate structure on the high voltage N-type well region, one end of which is connected to the N-type heavily doped source region, and the other end of which extends to the patterned isolation region . Another embodiment of the present invention provides a gate insulated double junction transistor (IGBT) electrostatic discharge protection component comprising: a semiconductor substrate; a high voltage P-type well region in the semiconductor substrate; and a high voltage N-type well region a patterned isolation region is disposed on the semiconductor substrate, defining a first active region in the high voltage N·well region and a second active region and a third active region in the high voltage P-type a P-type densely doped drain region is disposed in the first active region; an N-type heavily doped source region is disposed in the second active region 97010 /0516-A41790TW/final 8 201017880 And a p-type heavily doped source region is disposed in the third active region; and a gate structure is disposed on the high-voltage P-well region, one end of which is connected to the N-type heavily doped source region The other end extends to the patterned isolation region. According to still another embodiment of the present invention, a gate insulated double junction transistor (IGBT) electrostatic discharge protection component includes: a semiconductor substrate; a patterned isolation region is disposed on the semiconductor substrate, defining a first active region and a a second active region; a gate structure is disposed on the first active region of the semiconductor substrate; an N-type double diffusion region is located on one side of the gate structure, and the first active region of the semiconductor substrate is disposed An N-type well region is disposed in the N-type double diffusion region, the bottom portion of which extends to the semiconductor substrate; a P-type densely doped drain region is disposed in the N-type well region; A type of heavily doped source region is disposed in the semiconductor substrate on the other side of the gate structure; and a P-type dense diffusion region is disposed in the second active region of the semiconductor substrate. The above described objects, features and advantages of the present invention will become more apparent from the aspects of the appended claims appended claims The examples accompanying the drawings illustrate the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the various elements of the drawings are described in the following description, and the specific embodiments are merely illustrative of specific ways of using the invention, and are not intended to limit the invention. 1A is a cross-sectional view showing a gate insulating double 97010 / 0516-A41790TW/final 9 201017880 junction transistor (IGBT) electrostatic discharge protection element in accordance with an embodiment of the present invention. In FIG. 1A, a gate insulated double junction transistor (IGBT) electrostatic discharge protection (ESD) device 100a includes a semiconductor substrate 110 and a patterned isolation region 130a, 130b, 130c disposed on the semiconductor substrate 110. A first active area OD1 and a second active area OD2 are defined. According to an embodiment of the invention, the semiconductor substrate 110 is an SOI substrate on an insulating layer, such as a P-type germanium substrate 101 having a buried oxide layer 102 thereon and a P-type germane layer 103 thereon. Formed on the buried oxide layer 102. An isolation region 1〇5® isolates the IGBT-ESD device 100a from other components on the substrate 110. A high voltage N-type well region 115 is formed in the first active region OD1 of the semiconductor substrate, and a P-type body doped region 120 is in the second active region OD2 of the semiconductor substrate, wherein the high voltage N-type The well region 115 and the p-type body doped region 120 are separated by a specific distance to expose the semiconductor substrate. A diffusion region 113 extends from the south pressure N-type well region 115 to the P-type body doping region 12A. A P-type heavily doped drain region 117 is disposed in the high voltage N-type well region 115, and the drain electrodes 145a, 145b are in electrical contact with the P-type heavily doped drain region. A pair of adjacent N-type heavily doped source regions 124 and a P-type dense diffusion region 122 are disposed in the P-type body doped region 12A, and the source electrodes 135a, 135b are respectively associated with the N-type The heavily doped source region 124 and the p-type dense diffusion region 122 are in electrical contact. A gate structure 140 is disposed on the semiconductor substrate, one end of which is in contact with the N-type heavily doped source region 124, and the other end of which extends to the patterned isolation region 130b. According to an embodiment of the present invention, the area of the P-type densely doped drain region 117 may be larger than the first active region 0D1' but smaller than the surface of the high-pressure N-type well region 115 97010 / 0516-A41790TW/final 201017880 The planar layout is as shown in Fig. 1B. Fig. 2 is a cross-sectional view showing an IGBT-ESD element according to another embodiment of the present invention. In the second α diagram, the IGBT-ESD element 100b is substantially the same as the IGBT-ESD element 1A of Fig. 1A, and is simplified for the sake of brevity. The same description will be omitted. The difference is that the area of the p-type densely doped yttrium region 217a is smaller than the area of the high-pressure N-type well region 115, and its planar layout is as shown in Fig. 2B. Between the high-pressure N-type well region 115 and the P-type densely doped drain region 217a in the high-pressure well region 115, there is a hetero-doped interface that is dispersible and reduces the ESD voltage by about 0.7V. In accordance with another embodiment of the present invention, the P-type heavily doped drain region 217b is a plurality of discrete island regions disposed in the high pressure N-type well region 115, the planar layout of which is illustrated in Figure 2C. Since each of the island regions 217b and the high-voltage N-type well region 115 has a hetero-doped interface that can disperse and lower the ESD voltage, enabling uniform turn-on of the IGBT-ESD components. . Fig. 3A is a schematic cross-sectional view showing an IGBT-ESD element according to still another embodiment of the present invention. In Fig. 3A, an IGBT-ESD device 300a' includes a semiconductor substrate 310, such as a P-type germanium substrate, and a high voltage N-type well region 315 is disposed in the semiconductor substrate 310. A patterned isolation region 330a, 330b, 330c is disposed on the high voltage N-type well region 315 defining a first active region and a second active region. An N-type double diffusion region 316a is disposed in the first active region of the high voltage N-type well region 315, and a P-type densely doped drain region 317 is disposed in the N-type double diffusion region 316a. A P-type body doping region 320 is disposed in the second active region of the high voltage N-type well region 315, wherein the N-type double diffusion region 316a and the P-type body doping region 320 are separated by a specific distance. 97010 / 0516-A41790TW/final 11 201017880 Expose the high pressure N-type well area. A pair of adjacent N-type heavily doped source regions 324 and a P-type dense diffusion region 322 are disposed in the P-type body doped region 320. A gate structure 340 is coupled to the N-type heavily doped source region 324 at one end of the high voltage N-type well region 315 and extends to the patterned isolation region 330b at the other end. Fig. 3B is a schematic cross-sectional view showing an IGBT-ESD element according to still another embodiment of the present invention. In Fig. 3B, one IGBT-ESD element 300b is substantially the same as the IGBT-ESD element 300a of Fig. 3A, and the same description is omitted here for brevity. The difference is that the IGBT-ESD element 300b has a P-type double diffusion region 316b disposed in the first active region of the high voltage N-type well region 315, and a p_type densely doped drain region 317 is disposed at the P - Type double diffusion zone 316b. Since the P-type densely doped drain region 317 and the P-type double diffusion region 316b are all P-type doped, the performance of the ESD component can be further improved. Fig. 4A is a schematic cross-sectional view showing an IGBT-ESD element according to still another embodiment of the present invention. In Fig. 4A, an IGBT-ESD device 400a includes a semiconductor substrate 410 in which a high voltage N-type well region 415b is in the semiconductor substrate. A high voltage P-type well region 415c is in the semiconductor substrate. A patterned isolation region 430a-430d is disposed on the semiconductor substrate, defining a first active region in the high voltage N-type well region 415b and a second active region and a third active region in the high voltage P-type well Area 415c. A high pressure P type well region 415a is disposed below the isolation region 430a. A P-type heavily doped non-polar region 417 is disposed in the first active region, wherein an N-type heavily doped source region 424 is disposed in the second active region, and a P-type heavily doped diffusion region 422 is disposed in the third active area 97010 /0516-A41790TW/final 12 201017880. A gate structure 440 is disposed on the high voltage p_type well region 415c, one end of which is in contact with the N-type heavily doped source region 424, and the other end of which extends to the patterned isolation region 430b. Fig. 4B is a schematic cross-sectional view showing an IGBT_ESD element according to still another embodiment of the present invention. In FIG. 4B, an igbt_ESd device 4〇〇b includes a semiconductor substrate 410, such as a [type germanium substrate 4〇1 having a P-type epitaxial layer 403 thereon, and a german buried layer 4〇2 arrangement. Between the p_ type germanium substrate 401 and the p-type epitaxial layer 4〇3. A high voltage N_type well region ❿ 415b is in the semiconductor substrate, and a high voltage p_ type well region 415c is in the semiconductor substrate. A patterned isolation region 430a-430f is disposed on the semiconductor substrate to define a first active region in the high voltage N-type well region 415b and a second active region and a third active region in the high voltage P-type well Area 415c. A high pressure N-type well region 415d is disposed below the isolation region 430e. a P-type densely doped drain region 417 is disposed in the first active region, an N-type heavily doped source region 424 is disposed in the second active region, and a P-type dense doping diffusion A zone 422 is disposed in the third active zone. Furthermore, an additional P-type heavily doped region 416 is placed in the high pressure P-type well region 415a, and an additional P-type densely doped region 426 is disposed in the high pressure P-type well region 415e. A gate structure 440 is disposed on the high voltage P-type well region 415c, one end of which is connected to the N-type heavily doped source region 424, and the other end of which extends to the patterned isolation region 430c. Fig. 5 is a schematic cross-sectional view showing an IGBT-ESD element according to still another embodiment of the present invention. In FIG. 5, an IGBT-ESD device 500 includes a semiconductor substrate 510, and a patterned isolation region 530a-530c is disposed on the semiconductor substrate 510 to define a first active region and a second 97010 /0516. -A41790TW/final 13 201017880 Active zone. A gate structure 540 is disposed on the first active region of the semiconductor substrate, and an N· type double diffusion region 516 is located on a side of the gate structure 54〇 and the first active region of the semiconductor substrate 510 is disposed. in. An 'N-type well region 515 is disposed in the N-type double diffusion region 516' and a bottom portion thereof extends to the semiconductor substrate 510, and a type of densely doped drain region 517 is disposed in the N-type well region 515. An N-type heavily doped source region 524 is disposed in the semiconductor substrate on the other side of the gate structure 540, and a light-doped (NLDD) region 524' extends to the gap of the gate structure 54〇 Below the wall. A p_ type concentrated diffusion region 522 is erected in the second active region of the semiconductor substrate. It should be noted that the area of the concentrated doped non-polar region of the IGBT_ESD element of the embodiments of the present invention is smaller than the area of the high-pressure N_-type well region, so that the high-pressure N-type well region and the type rich doped drain region There is a hetero-doped interface that can disperse and lower the ESD voltage by about 77V. What's more, the P-type concentrated doping non-polar region is a plurality of separated island regions, which are disposed in the high-pressure N_-type well region, so that there is a heterogeneity between each island region and the high-pressure N_-type well region.掺杂 The doped interface disperses and reduces the ESD voltage, enabling a more uniform turn-on of the IGBT-ESD components. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the invention, and the invention may be practiced without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a cross-sectional view showing a gate insulating double 97010 / 0516-A41790TW/final 201017880 junction transistor (IGBT) electrostatic discharge protection element according to an embodiment of the present invention; A plan layout of a first active region of the IGBT-ESD device of FIG. 1A is shown; FIG. 2A is a cross-sectional view showing an IGBT-ESD device according to another embodiment of the present invention; FIGS. 2B and 2C are respectively showing a second FIG. Planar layout of different embodiments of the first active region of the IGBT-ESEf device; FIG. 3A is a schematic cross-sectional view showing an IGBT-ESD element® device according to still another embodiment of the present invention; FIG. 3B is a view showing still another embodiment of the present invention FIG. 4A is a schematic cross-sectional view showing an IGBT-ESD device according to still another embodiment of the present invention; FIG. 4B is a cross-sectional view showing an IGBT-ESD device according to still another embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a cross-sectional view showing an IGBT-ESD element® according to still another embodiment of the present invention. [Description of main component symbols] 100a, 100b, 300a, 300b, 400a, 400b, 500~IGBT-ESD components; 101, 401~P-type germanium substrate; 102~ buried oxide layer; 402~N-type buried layer; 403~ P-type epitaxial layer; 97010 /0516-A41790TW/fmal 15 201017880 105~ isolation region; 110, 310, 410, 510~ semiconductor substrate; 115, 315, 415, 415 (1, 515~ high voltage 1 ^-type well area; 415a, 415c, 415e~ high pressure P-type well area; 316a, 516~N-type double diffusion area; 316b~P-type double diffusion area; 416~ additional P-type densely doped area ;
117、217a、217b、317、417、517〜P-型濃摻雜汲極區； 120、320〜P-型體摻雜區； 122、322、422、522〜P-型濃擴散區； 124、324、424、524〜N-型濃摻雜源極區； 524’〜N-型輕摻雜(NLDD)區； 426〜額外的P-型濃摻雜區； 130a-130c、330a-330c、430a-430f、530a-530c〜圖案化 的隔離區， 135a、135b~源極電極； 140、340、440、540〜閘極結構； 145a、145b〜汲極電極； OD1〜第一主動區； OD2〜第二主動區。 97010 / 0516-A41790TW/final 16117, 217a, 217b, 317, 417, 517~P-type concentrated doped drain region; 120, 320~P-type body doped region; 122, 322, 422, 522~P-type dense diffusion region; 324, 424, 524~N-type heavily doped source regions; 524'~N-type lightly doped (NLDD) regions; 426~ additional P-type heavily doped regions; 130a-130c, 330a-330c 430a-430f, 530a-530c~ patterned isolation region, 135a, 135b~ source electrode; 140, 340, 440, 540~ gate structure; 145a, 145b~dip electrode; OD1~first active region; OD2 ~ second active area. 97010 / 0516-A41790TW/final 16