TWI594437B - Thin film transistor array and video display device - Google Patents
Thin film transistor array and video display device Download PDFInfo
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- TWI594437B TWI594437B TW103110807A TW103110807A TWI594437B TW I594437 B TWI594437 B TW I594437B TW 103110807 A TW103110807 A TW 103110807A TW 103110807 A TW103110807 A TW 103110807A TW I594437 B TWI594437 B TW I594437B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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Description
本發明係關於薄膜電晶體陣列及影像顯示裝置。 The present invention relates to thin film transistor arrays and image display devices.
由於資訊技術的急速發展，當今利用筆記型電腦或行動資訊終端等進行資訊的傳送、接收極為頻繁。在不久的將來，無需選擇場所即可交換資訊的U化社會(Ubiquitous society)可能即將來臨，此已成了眾所皆知之事實。於此社會中，有待更輕量且薄型之資訊終端。 Due to the rapid development of information technology, today's information transmission and reception using notebook computers or mobile information terminals are extremely frequent. In the near future, the Ubiquitous society, which can exchange information without having to choose a place, is about to come, and this has become a well-known fact. In this society, there is a need for a lighter and thinner information terminal.
此種資訊終端所使用的電子構件中，目前薄膜電晶體元件所使用的半導體材料之主流為矽系。由於使用矽系材料之薄膜電晶體元件的形成包含高溫步驟，薄膜電晶體元件之基板材料便要求可承受步驟溫度。因此，一般而言，作為供形成薄膜電晶體元件的基板係使用玻璃。 Among the electronic components used in such information terminals, the mainstream of semiconductor materials used in thin film transistors is currently a lanthanide system. Since the formation of the thin film transistor element using the lanthanide material involves a high temperature step, the substrate material of the thin film transistor element is required to withstand the step temperature. Therefore, in general, glass is used as a substrate for forming a thin film transistor element.
然而，在構成前述之資訊終端時使用玻璃的情況下，該資訊終端會變成較重、無柔軟性且因落下之衝擊而有破裂之可能的製品。因此，在玻璃上形成薄膜電晶體元件所引起之此等徵狀，就U化社會中的資訊終端而言可謂不理想。 However, in the case where glass is used in constituting the aforementioned information terminal, the information terminal becomes a product which is heavy, has no flexibility, and is likely to be broken due to the impact of falling. Therefore, the symptoms caused by the formation of thin film transistor elements on glass are not ideal for information terminals in the U-system.
對此，近年來作為薄膜電晶體之半導體材料 ，有機半導體係備受矚目。有機半導體材料由於不需要如矽系材料之高溫下熱處理步驟，而具有可裝設於可撓性塑膠基板上等優點。更且，由於能以印刷製程製作而無需使用真空製程，亦具有可降低成本等優點。 In this regard, in recent years, as a semiconductor material of a thin film transistor The organic semiconductor system is attracting attention. The organic semiconductor material has the advantages of being able to be mounted on a flexible plastic substrate because it does not require a high temperature heat treatment step such as a lanthanoid material. Moreover, since it can be produced by a printing process without using a vacuum process, it has the advantage of reducing cost.
為了自溶液形成半導體層，可列舉旋轉塗布法或浸漬法、噴墨法等方法。其中，透過應用印刷製程，可有效形成半導體層。例如在專利文獻1係利用柔版印刷來進行有機半導體溶液之圖案化。 In order to form a semiconductor layer from a solution, methods, such as a spin coating method, a dipping method, and an inkjet method, are mentioned. Among them, the semiconductor layer can be effectively formed by applying a printing process. For example, in Patent Document 1, patterning of an organic semiconductor solution is performed by flexographic printing.
更且，專利文獻2係藉由將半導體層作成條帶形狀，提升對準精確度，並可進一步提高生產效率。 Further, Patent Document 2 improves the alignment accuracy by making the semiconductor layer into a strip shape, and further improves the production efficiency.
在保護層的形成中，透過應用濕式製程，可簡便且以低成本形成保護層。例如專利文獻3係利用柔版形成印刷保護層，簡便地製作薄膜電晶體陣列。 In the formation of the protective layer, the protective layer can be formed simply and at low cost by applying a wet process. For example, Patent Document 3 uses a flexographic plate to form a printed protective layer, and a thin film transistor array can be easily fabricated.
[專利文獻1]日本特開2006-63334號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-63334
[專利文獻2]日本特開2008-235861號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2008-235861
[專利文獻3]國際公開第2010/107027號 [Patent Document 3] International Publication No. 2010/107027
然而，利用印刷法形成薄膜電晶體陣列時，相較於習知採用光微影的圖案化法，對準精確度較低，且圖案形狀之偏差變動亦大，因此需要更多的對準餘裕度(alignment margin)。其中，當利用印刷法形成半導體 層與保護層時，必須考量半導體層與保護層兩者之偏差變動來取得其對準餘裕度。特別是，若保護層的對準餘裕度較小，致保護層之絕緣性材料在汲極電極上露出時，會堵塞層間絕緣膜之通孔，使得汲極電極與像素電極無法導通。另一方面，對準餘裕度過多時，則薄膜電晶體陣列之解析度會下降，視覺辨識性亦降低。 However, when the thin film transistor array is formed by the printing method, the alignment precision is low and the variation of the pattern shape is large, which requires more alignment margin than the conventional patterning method using photolithography. Alignment margin. Among them, when using a printing method to form a semiconductor In the case of a layer and a protective layer, it is necessary to consider variations in the deviation between the semiconductor layer and the protective layer to obtain the alignment margin. In particular, if the alignment margin of the protective layer is small, the insulating material of the protective layer is exposed on the drain electrode, and the via hole of the interlayer insulating film is blocked, so that the drain electrode and the pixel electrode are not conductive. On the other hand, when the alignment margin is excessive, the resolution of the thin film transistor array is lowered, and the visibility is also lowered.
對此，本發明係提供一種透過取最大之保護層與層間絕緣膜之通孔的距離，可抑制保護層材料堵塞通孔，並可提高良率的薄膜電晶體陣列、及具備其之影像顯示裝置。 In view of the above, the present invention provides a thin film transistor array capable of suppressing clogging of via holes by a protective layer material by taking a distance between a maximum protective layer and an interlayer insulating film, and an image display having the same Device.
用以解決前述課題之本發明一形態係一種薄膜電晶體陣列，其係至少具備絕緣基板、閘極電極、閘極絕緣層、源極配線、與源極配線連接之源極電極、汲極電極、半導體層、被覆半導體層之保護層、層間絕緣膜、及像素電極的薄膜電晶體陣列，其中保護層係與源極配線平行的條帶形狀，且「用以達成汲極電極與像素電極之導通所設置的層間絕緣膜之通孔的中心位置」與「通過彼此相鄰的條帶形狀保護層間的中點且與條帶平行的直線」的距離為40μm以下。 An aspect of the present invention for solving the above problems is a thin film transistor array comprising at least an insulating substrate, a gate electrode, a gate insulating layer, a source wiring, a source electrode connected to a source wiring, and a drain electrode a semiconductor layer, a protective layer covering the semiconductor layer, an interlayer insulating film, and a thin film transistor array of the pixel electrode, wherein the protective layer is in a strip shape parallel to the source wiring, and "to achieve the gate electrode and the pixel electrode The distance between the center position of the through hole of the interlayer insulating film provided in the conduction direction and the "a line passing through the midpoint between the strip-shaped protective layers adjacent to each other and parallel to the strip" is 40 μm or less.
又，通孔的中心位置可位於：通過彼此相鄰的條帶形狀保護層間的中點且與條帶平行的直線上。 Further, the center position of the through hole may be located on a line parallel to the strip by the midpoint between the strip shape protection layers adjacent to each other.
又，半導體層可為有機半導體或氧化物半導體。 Further, the semiconductor layer may be an organic semiconductor or an oxide semiconductor.
又，半導體層可利用柔版印刷法、噴墨印刷 法、網版印刷法的任1種以上形成。 Moreover, the semiconductor layer can be flexographically printed, inkjet printed Any one or more of the method and the screen printing method are formed.
又，保護層可使用有機絕緣材料形成。 Also, the protective layer may be formed using an organic insulating material.
又，保護層可利用柔版印刷法、噴墨印刷法、網版印刷法的任1種以上形成。 Further, the protective layer can be formed by any one or more of a flexographic printing method, an inkjet printing method, and a screen printing method.
又，層間絕緣膜可利用柔版印刷法、噴墨印刷法、網版印刷法、凹版印刷法的任1種以上形成。 In addition, the interlayer insulating film can be formed by any one or more of a flexographic printing method, an inkjet printing method, a screen printing method, and a gravure printing method.
又，絕緣基板可為塑膠基板。 Further, the insulating substrate may be a plastic substrate.
又，本發明另一形態係一種影像顯示裝置，其係具備上述之薄膜電晶體陣列與影像顯示媒體。 Still another aspect of the invention provides an image display device comprising the above-described thin film transistor array and image display medium.
又，影像顯示媒體可採用電泳方式。 Moreover, the image display medium can be subjected to electrophoresis.
根據本發明薄膜電晶體陣列，能以高良率提供一種低成本且高品質的可撓性薄膜電晶體。藉著使且用以達成薄膜電晶體陣列之汲極電極與像素電極之導通所設置的層間絕緣膜之通孔的中心位置，位於與通過被覆半導體層的相鄰條帶形狀保護層間的中點的條帶平行的直線上，可取最大之對準餘裕度，可減少線寬之偏差變動或對準偏移所引起的良率下降，以提高可撓性薄膜電晶體之生產量。 According to the thin film transistor array of the present invention, a low-cost and high-quality flexible thin film transistor can be provided at a high yield. The center position of the through hole provided by the interlayer insulating film provided for the conduction between the drain electrode of the thin film transistor array and the pixel electrode is located at a midpoint between the protective layer of the adjacent strip shape passing through the coated semiconductor layer On the straight line parallel to the strip, the maximum alignment margin can be taken, and the yield variation caused by the deviation of the line width or the offset deviation can be reduced to increase the throughput of the flexible film transistor.
一種薄膜電晶體陣列，其係至少具備絕緣基板、閘極電極、閘極絕緣層、源極配線、與源極配線連接之源極電極、汲極電極、半導體層、被覆半導體層之保護層、層間絕緣膜、及像素電極，其中保護層係呈與源極配線平行的條帶形狀，且用以達成汲極電極與像素電極之導通所設置的層間絕緣膜之通孔的中心位置係位 於：距通過條帶形狀保護層與相鄰於其之條帶形狀保護層的中點且與條帶平行之直線40μm以內之距離處，藉此，可不考慮薄膜電晶體陣列之解析度，而取得最大保護層之對準餘裕度。更且，藉由將保護層形狀作成條帶狀，可提升與層間絕緣膜或半導體層之對準精確度。 A thin film transistor array comprising at least an insulating substrate, a gate electrode, a gate insulating layer, a source wiring, a source electrode connected to the source wiring, a drain electrode, a semiconductor layer, a protective layer covering the semiconductor layer, An interlayer insulating film and a pixel electrode, wherein the protective layer is in the shape of a strip parallel to the source wiring, and is used to achieve a center position of the through hole of the interlayer insulating film provided by the drain electrode and the pixel electrode. Wherein, the distance from the strip-shaped protective layer to the midpoint of the strip-shaped protective layer adjacent thereto and the line parallel to the strip is within a distance of 40 μm, whereby the resolution of the thin film transistor array can be ignored, Get the maximum margin of alignment of the protective layer. Moreover, by making the shape of the protective layer into a strip shape, the alignment accuracy with the interlayer insulating film or the semiconductor layer can be improved.
使通過層間絕緣膜之通孔的中心位置與相鄰條帶形狀保護層的中點且與條帶平行的直線的偏移量最大容許40μm，藉此，可進行假設有：圖案形狀之偏差變動或印刷機之對準誤差、步驟中加熱所致塑膠基材之伸縮，的圖案設計。 The offset amount of the center position of the through hole passing through the interlayer insulating film and the straight line parallel to the strip at the midpoint of the adjacent strip shape protective layer is allowed to be 40 μm at the maximum, thereby making it possible to assume a variation in the deviation of the pattern shape. Or the alignment error of the printing machine, the stretching of the plastic substrate caused by heating in the step, and the pattern design.
使半導體層採用有機半導體，藉此，可應用濕式製程，縱為大面積亦能以較短的產距時間形成薄膜電晶體陣列。 The semiconductor layer is made of an organic semiconductor, whereby a wet process can be applied, and a thin film transistor array can be formed with a short production time even for a large area.
使半導體層利用柔版印刷法、噴墨印刷法、網版印刷法形成，藉此，縱為大面積亦能以較短的產距時間形成薄膜電晶體陣列。 The semiconductor layer is formed by a flexographic printing method, an inkjet printing method, or a screen printing method, whereby a thin film transistor array can be formed with a short production time even in a large area.
使保護層使用有機絕緣材料形成，藉此，可應用濕式製程，縱為大面積亦能以較短的產距時間形成薄膜電晶體陣列。 The protective layer is formed using an organic insulating material, whereby a wet process can be applied, and a thin film transistor array can be formed with a short production time even for a large area.
使保護層利用柔版印刷法、噴墨印刷法、網版印刷法形成，藉此，縱為大面積亦能以較短的產距時間形成薄膜電晶體陣列。 The protective layer is formed by a flexographic printing method, an inkjet printing method, or a screen printing method, whereby a thin film transistor array can be formed with a short production time even in a large area.
使層間絕緣膜使用有機絕緣材料形成，藉此，可應用濕式製程，縱為具有大面積之薄膜電晶體陣列，亦能以較短的產距時間形成。 The interlayer insulating film is formed using an organic insulating material, whereby a wet process can be applied, and a thin film transistor array having a large area can be formed in a short production time.
使絕緣基板為塑膠基板，藉此，可製作輕量且為可撓性的薄膜電晶體陣列。 By making the insulating substrate a plastic substrate, a thin film transistor array which is lightweight and flexible can be produced.
1、2、3‧‧‧薄膜電晶體陣列 1, 2, 3‧ ‧ film transistor array
10‧‧‧絕緣基板 10‧‧‧Insert substrate
11‧‧‧閘極電極 11‧‧‧ gate electrode
12‧‧‧閘極絕緣膜 12‧‧‧Gate insulation film
13‧‧‧源極電極 13‧‧‧Source electrode
13a‧‧‧源極配線 13a‧‧‧Source wiring
14‧‧‧汲極電極 14‧‧‧汲electrode
15‧‧‧半導體層 15‧‧‧Semiconductor layer
16‧‧‧保護層 16‧‧‧Protective layer
17‧‧‧層間絕緣膜 17‧‧‧Interlayer insulating film
17a‧‧‧通孔 17a‧‧‧through hole
18‧‧‧像素電極 18‧‧‧pixel electrode
19‧‧‧電容電極 19‧‧‧Capacitance electrode
20‧‧‧電泳媒體 20‧‧‧ Electrophoresis media
第1圖係表示本發明之一實施形態者，其係表示薄膜電晶體陣列之概略構成的圖案配置平面圖。 Fig. 1 is a plan view showing a schematic configuration of a thin film transistor array, showing an embodiment of the present invention.
第2圖係由第1圖之圖案配置平面圖省略層間絕緣膜17之圖示而成的圖案配置平面圖。 Fig. 2 is a plan layout plan view in which the interlayer insulating film 17 is omitted from the pattern arrangement plan view of Fig. 1.
第3圖係表示本發明之一實施形態，其係薄膜電晶體陣列之相鄰2元件的剖面結構(沿第1圖之R-R’線切開者)。 Fig. 3 is a view showing an embodiment of the present invention, which is a cross-sectional structure of two adjacent elements of a thin film transistor array (cut along the line R-R' in Fig. 1).
第4圖係表示實施例1，其係薄膜電晶體陣列之相鄰2元件的剖面結構。 Fig. 4 is a view showing Embodiment 1, which is a sectional structure of adjacent two elements of a thin film transistor array.
第5圖係表示比較例1，其係表示薄膜電晶體陣列之概略構成的圖案配置平面圖。 Fig. 5 is a plan view showing a configuration of a comparative example 1 showing a schematic configuration of a thin film transistor array.
第6圖係表示比較例1，其係薄膜電晶體陣列之相鄰2元件的剖面結構(沿第5圖之R-R’線切開者)。 Fig. 6 is a view showing Comparative Example 1, which is a sectional structure of adjacent two elements of a thin film transistor array (cut along the line R-R' in Fig. 5).
以下，就本發明之實施形態，一面參照圖式一面加以說明。實施形態中，將對同一構成元件附予同一符號，並於實施形態間省略重複說明。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiment, the same components are denoted by the same reference numerals, and the description thereof will not be repeated.
第1圖至第3圖係表示本發明薄膜電晶體陣列1之一實施形態。第1圖係表示薄膜電晶體陣列1之圖案配置平面圖。此外，為了進行說明，第1圖之薄膜電晶體陣 列1已省略像素電極18之圖示。為了易於觀看，第2圖係由第1圖省略影線及層間絕緣膜17之圖示而成的圖案配置平面圖。第3圖係表示將第1圖之薄膜電晶體陣列1沿著通過通孔17a之R-R’線切開的剖面圖。 1 to 3 show an embodiment of the thin film transistor array 1 of the present invention. Fig. 1 is a plan view showing the pattern arrangement of the thin film transistor array 1. In addition, for the purpose of illustration, the thin film transistor array of FIG. Column 1 has omitted the illustration of pixel electrode 18. In order to facilitate the viewing, the second drawing is a plan layout view in which the hatching and the interlayer insulating film 17 are omitted from the first drawing. Fig. 3 is a cross-sectional view showing the thin film transistor array 1 of Fig. 1 cut along the line R-R' passing through the through hole 17a.
薄膜電晶體陣列1，在絕緣基板10上具備：閘極電極11、電容電極19、閘極絕緣層12、源極電極13、源極配線13a、汲極電極14、半導體層15、保護層16、層間絕緣膜17、及像素電極18。保護層16係包含有機絕緣材料，其係與源極配線13a平行的條帶形狀。為了使像素電極18與汲極電極14導通，如第2圖及第3圖所示，對層間絕緣膜17穿設之通孔17a的中心位置A係位於：通過彼此相鄰的條帶形狀保護層16間的中點且與條帶平行的直線C上；或與直線C之距離(中心位置A與直線C之最短距離)為40μm以下處。通孔17a的中心位置亦可位於直線C上。「彼此相鄰的兩個保護層16間」係指將各保護層16設為線時相鄰保護層16間的空間；「中點」在第2圖及第3圖中係指空間寬度的兩等分點。亦即，在第1圖及第2圖之平面圖上，「中點」係指位於距面向兩保護層16間的空間之各保護層16的端部等距離之線段上的點。中心位置A為通孔17a之對準位置的中心而意指與絕緣基板10面平行之平面上的點的位置，其係以平面上的二維座標表示的位置。 The thin film transistor array 1 includes a gate electrode 11, a capacitor electrode 19, a gate insulating layer 12, a source electrode 13, a source wiring 13a, a drain electrode 14, a semiconductor layer 15, and a protective layer 16 on the insulating substrate 10. The interlayer insulating film 17 and the pixel electrode 18. The protective layer 16 is made of an organic insulating material in a strip shape parallel to the source wiring 13a. In order to make the pixel electrode 18 and the drain electrode 14 conductive, as shown in FIGS. 2 and 3, the center position A of the through hole 17a through which the interlayer insulating film 17 is disposed is located by: strip shape protection adjacent to each other The midpoint between the layers 16 and the straight line C parallel to the strip; or the distance from the straight line C (the shortest distance between the center position A and the straight line C) is 40 μm or less. The center position of the through hole 17a may also be located on the straight line C. "Between two protective layers 16 adjacent to each other" means a space between adjacent protective layers 16 when each protective layer 16 is a line; "midpoint" refers to a space width in FIGS. 2 and 3 Two equal points. That is, in the plan views of Figs. 1 and 2, the "midpoint" refers to a point located on a line segment equidistant from the end of each of the protective layers 16 facing the space between the two protective layers 16. The center position A is the center of the aligned position of the through hole 17a and means the position of a point on a plane parallel to the surface of the insulating substrate 10, which is a position indicated by a two-dimensional coordinate on the plane.
本發明之絕緣基板10典型上為塑膠基板，可使用聚甲基丙烯酸甲酯、聚丙烯酸酯、聚碳酸酯、聚苯乙烯、聚環硫乙烷、聚醚碸、聚烯烴、聚對苯二甲酸乙 二酯、聚萘二甲酸乙二酯、環烯烴聚合物、聚醚碸、三乙酸纖維素、聚氟乙烯薄膜、乙烯-四氟乙烯、共聚合樹脂、耐候性聚對苯二甲酸乙二酯、耐候性聚丙烯、玻璃纖維強化丙烯酸樹脂薄膜、玻璃纖維強化聚碳酸酯、透明性聚醯亞胺、氟系樹脂、環狀聚烯烴樹脂等，惟本發明不限定於此等。此等可單獨，或作成以2種以上積層的複合基板使用。又，亦可使用在玻璃或塑膠基板上具有彩色濾光片之類的樹脂層的基板。 The insulating substrate 10 of the present invention is typically a plastic substrate, and polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polycyclohexane, polyether oxime, polyolefin, polyparaphenylene can be used. Formic acid B Diester, polyethylene naphthalate, cycloolefin polymer, polyether oxime, cellulose triacetate, polyvinyl fluoride film, ethylene-tetrafluoroethylene, copolymerized resin, weather resistant polyethylene terephthalate The weather resistant polypropylene, the glass fiber reinforced acrylic resin film, the glass fiber reinforced polycarbonate, the transparent polyimide, the fluorine resin, the cyclic polyolefin resin, etc., but the invention is not limited thereto. These may be used alone or in a composite substrate in which two or more layers are laminated. Further, a substrate having a resin layer such as a color filter on a glass or plastic substrate can also be used.
本發明之閘極電極11、源極電極13、源極配線13a、汲極電極14、像素電極18、電容電極19係較佳使用Au、Ag、Cu、Cr、Al、Mg、Li等低電阻金屬材料或氧化物材料。具體而言，可列舉氧化銦(In2O3)、氧化錫(SnO2)、氧化鋅(ZnO)、氧化鎘(CdO)、氧化銦鎘(CdIn2O4)、氧化鎘錫(Cd2SnO4)、氧化鋅錫(Zn2SnO4)、氧化銦鋅(InZnO)等。又，較佳亦為該氧化物材料中摻有雜質者。作為一例，可列舉氧化銦中摻有鉬或鈦者、氧化錫中摻有銻或氟者、氧化鋅中摻有銦、鋁、鎵者等。其中，氧化銦中摻有錫之氧化銦錫(ITO)係顯示特低電阻率。又，PEDOT(聚乙撐二氧噻吩)等有機導電性材料亦為較佳，在其為單質或與導電性氧化物材料積層複數層時，均可理想地使用。閘極電極11、源極電極13、源極配線13a、汲極電極14、像素電極18、電容電極19可全由相同材料形成，亦可由不同材料形成。惟，為了縮減步驟，較理想為源極電極13、源極配線13a與汲極電極14係使用同一材料。此等電極可利用真空蒸鍍法、離子鍍法、濺鍍 法、雷射剝蝕法、電漿CVD法、光CVD法、熱線(hot wire)CVD法等形成。另外，亦可藉由將上述之導電性材料調成印墨狀、糊狀者利用網版印刷、柔版印刷、噴墨法等實施塗布並進行燒成而形成；本發明不限定於此等。 The gate electrode 11, the source electrode 13, the source wiring 13a, the drain electrode 14, the pixel electrode 18, and the capacitor electrode 19 of the present invention preferably use low resistance such as Au, Ag, Cu, Cr, Al, Mg, or Li. Metal material or oxide material. Specific examples thereof include indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), cadmium oxide (CdO), indium cadmium oxide (CdIn 2 O 4 ), and cadmium tin oxide (Cd 2 ). SnO 4 ), zinc tin oxide (Zn 2 SnO 4 ), indium zinc oxide (InZnO), or the like. Further, it is preferable that the oxide material is doped with impurities. As an example, those in which indium oxide is doped with molybdenum or titanium, tin oxide is doped with antimony or fluorine, zinc oxide is doped with indium, aluminum or gallium may be mentioned. Among them, indium tin oxide (ITO) doped with tin in indium oxide exhibits an extremely low resistivity. Further, an organic conductive material such as PEDOT (polyethylenedioxythiophene) is also preferable, and it can be preferably used when it is a single substance or a plurality of layers are laminated with a conductive oxide material. The gate electrode 11, the source electrode 13, the source wiring 13a, the drain electrode 14, the pixel electrode 18, and the capacitor electrode 19 may all be formed of the same material or may be formed of different materials. However, in order to reduce the number of steps, it is preferable to use the same material for the source electrode 13, the source wiring 13a, and the drain electrode 14. These electrodes can be formed by a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD method, a photo CVD method, a hot wire CVD method, or the like. In addition, the conductive material may be formed into an ink form or a paste, and the coating may be formed by screen printing, flexographic printing, inkjet method, or the like, and calcined. The present invention is not limited thereto. .
本發明之閘極絕緣膜12可列舉氧化矽、氮化矽、氧化氮化矽、氧化鋁、氧化鉭、氧化釔、氧化鉿、鋁酸鉿、氧化鋯、氧化鈦等無機材料；或PMMA(聚甲基丙烯酸甲酯)等聚丙烯酸酯、PVA(聚乙烯醇)、PVP(聚乙烯酚)等，惟本發明不限定於此等。又，為了抑制閘極外漏電流，絕緣材料之較佳電阻率為1011Ωcm以上，更佳為1014Ωcm以上。 The gate insulating film 12 of the present invention may, for example, be an inorganic material such as cerium oxide, cerium nitride, cerium oxynitride, aluminum oxide, cerium oxide, cerium oxide, cerium oxide, cerium aluminate, zirconium oxide or titanium oxide; or PMMA ( Polyacrylate such as polymethyl methacrylate), PVA (polyvinyl alcohol), PVP (polyvinyl phenol), etc., but the present invention is not limited thereto. Further, in order to suppress the leakage current outside the gate, the preferable resistivity of the insulating material is 10 11 Ωcm or more, and more preferably 10 14 Ωcm or more.
作為本發明所使用之半導體層15，可列舉氧化物半導體或有機半導體。作為氧化物半導體材料，可列舉含有鋅、銦、錫、鎢、鎂、鎵等中1種以上之元素的氧化物，亦即可列舉氧化鋅、氧化銦、氧化銦鋅、氧化錫、氧化鎢、氧化鋅鎵銦等習知材料。作為有機半導體材料，可將聚噻吩、聚烯丙胺、茀聯噻吩共聚物、及如該等之衍生物的高分子有機半導體材料；及稠五苯、稠四苯、銅酞青、苝、6,13-雙(三異丙基矽烷基乙炔基)稠五苯(TIPS-稠五苯)、及如該等之衍生物的低分子有機半導體材料或經加熱處理等轉換為有機半導體的前驅物，作為半導體材料印墨使用。又，奈米碳管或者富勒烯等碳化合物或半導體奈米粒子分散液等亦可作為半導體層之材料使用。使用半導體材料印墨時，作為溶媒可列舉甲苯或二甲苯、茚烷、四氫萘、丙二醇甲醚乙酸酯等， 惟不限定於此等。為了形成半導體層15，可適宜使用將上述之導電性材料製成印墨狀、糊料狀者利用網版印刷、柔版印刷、噴墨法等之任1種以上進行塗布並乾燥之方法。 As the semiconductor layer 15 used in the present invention, an oxide semiconductor or an organic semiconductor can be cited. Examples of the oxide semiconductor material include oxides containing at least one element selected from the group consisting of zinc, indium, tin, tungsten, magnesium, and gallium, and examples thereof include zinc oxide, indium oxide, indium zinc oxide, tin oxide, and tungsten oxide. , such as zinc oxide gallium indium and other conventional materials. As the organic semiconductor material, a polythiophene, a polyallylamine, a thiophene copolymer, and a polymer organic semiconductor material such as the derivative; and condensed pentabenzene, condensed tetrathene, copper phthalocyanine, ruthenium, and 6 , 13-bis(triisopropyldecyl ethynyl) pentacene (TIPS-fused pentabenzene), and low molecular organic semiconductor materials such as these derivatives or precursors converted to organic semiconductors by heat treatment or the like Used as a semiconductor material ink. Further, a carbon compound such as a carbon nanotube or fullerene or a semiconductor nanoparticle dispersion or the like may be used as a material of the semiconductor layer. When ink is printed using a semiconductor material, examples of the solvent include toluene or xylene, decane, tetrahydronaphthalene, and propylene glycol methyl ether acetate. However, it is not limited to this. In order to form the semiconductor layer 15, a method in which one or more of screen printing, flexographic printing, and inkjet method are used for coating and drying the above-mentioned conductive material in the form of an ink or a paste is suitably used.
作為本發明使用之保護層16所使用的材料，可適宜使用聚乙烯酚、聚甲基丙烯酸甲酯、聚醯亞胺、聚乙烯醇、環氧樹脂、氟樹脂等的高分子溶液；分散有氧化鋁或氧化矽凝膠等粒子的溶液。又，保護層16之形成方法，可適宜採用利用網版印刷或柔版印刷、噴墨法等濕式法之任1種以上而直接形成圖案的方法。又，層間絕緣膜17，可利用柔版印刷法、噴墨印刷法、網版印刷法、凹版印刷法之任1種以上形成。 As a material used for the protective layer 16 used in the present invention, a polymer solution of polyvinyl phenol, polymethyl methacrylate, polyimine, polyvinyl alcohol, epoxy resin, fluororesin or the like can be suitably used; A solution of particles such as alumina or cerium oxide gel. In addition, as a method of forming the protective layer 16, a method of directly forming a pattern by any one or more of wet methods such as screen printing, flexographic printing, and inkjet method can be suitably employed. In addition, the interlayer insulating film 17 can be formed by any one or more of a flexographic printing method, an inkjet printing method, a screen printing method, and a gravure printing method.
就使用本發明之圖案形成方法所形成的薄膜電晶體之結構而言，不特別限定，可為頂部閘極型、底部閘極型之任一結構。 The structure of the thin film transistor formed by the pattern forming method of the present invention is not particularly limited, and may be any of a top gate type and a bottom gate type.
作為閘極電極之配置以外的結構差異，有半導體層位置不同的底部接觸型、頂部接觸型，惟本發明不限定於此等。 The difference in structure other than the arrangement of the gate electrodes is a bottom contact type or a top contact type in which the positions of the semiconductor layers are different, but the present invention is not limited thereto.
又，本案所揭示之可撓性薄膜電晶體陣列透過與採用電泳方式等的影像顯示媒體共同使用，可利用於作為可撓性電子紙張、可撓性有機EL顯示器等影像顯示裝置的開關元件。又，特別是，藉由將層間絕緣膜之通孔的中心位置形成於通過條帶形狀保護層間的中點且與條帶平行的直線上，可提高製造步驟中的良率或生產量。如考量到對準偏移等，只要使通孔中心位置與條帶 中點的位置之偏移限於40μm以內，則可在不妨礙汲極電極與層間絕緣膜之導通下形成保護層，並可提高生產量。依此，得以低成本且高品質地製作可應用於可撓性顯示器或IC卡、IC標籤等廣範圍的可撓性薄膜電晶體。 Further, the flexible film transistor array disclosed in the present invention can be used as a switching element of an image display device such as a flexible electronic paper or a flexible organic EL display, by being used together with an image display medium using an electrophoresis method or the like. Further, in particular, by forming the center position of the through hole of the interlayer insulating film on a straight line passing through the midpoint between the strip shape protective layers and parallel to the strip, the yield or throughput in the manufacturing step can be improved. If you consider the alignment offset, etc., just make the center position of the through hole and the strip When the offset of the position of the midpoint is limited to 40 μm, the protective layer can be formed without hindering the conduction between the drain electrode and the interlayer insulating film, and the throughput can be improved. According to this, it is possible to manufacture a wide range of flexible thin film transistors which can be applied to a flexible display, an IC card, an IC tag, and the like at low cost and high quality.
(實施例1) (Example 1)
在第4圖顯示實施例1之包含底部閘極底部接觸型可撓性薄膜電晶體的薄膜電晶體陣列2之剖面結構，並說明其製造方法。本薄膜電晶體其1元件之尺寸為300μm×300μm，在薄膜電晶體陣列全體中，有240×320個該元件。 The cross-sectional structure of the thin film transistor array 2 including the bottom gate bottom contact type flexible thin film transistor of Example 1 is shown in Fig. 4, and a manufacturing method thereof will be described. The thickness of one element of the thin film transistor is 300 μm × 300 μm, and there are 240 × 320 such elements in the entire film transistor array.
使用聚萘二甲酸乙二酯(PEN)薄膜作為絕緣基板10。在PEN薄膜上將鋁藉由濺鍍法予以成膜為100nm後，使用正型光阻進行光微影、蝕刻，其後將光阻剝離，藉此形成閘極電極11、電容電極19。 A polyethylene naphthalate (PEN) film was used as the insulating substrate 10. After the aluminum was formed into a film on the PEN film by sputtering to 100 nm, photolithography and etching were performed using a positive photoresist, and then the photoresist was peeled off to form the gate electrode 11 and the capacitor electrode 19.
接著，利用模頭塗布器塗布聚醯亞胺作為絕緣材料，於180℃加以乾燥1小時，得到閘極絕緣膜12。其次將金藉由蒸鍍法予以成膜為50nm，並使用正型光阻進行光微影及蝕刻，其後將光阻剝離，藉此形成源極電極13、源極配線13a及汲極電極14。 Next, polyimine was applied as an insulating material by a die coater, and dried at 180 ° C for 1 hour to obtain a gate insulating film 12. Next, gold is formed into a film by vapor deposition to a thickness of 50 nm, and photolithography and etching are performed using a positive photoresist, and then the photoresist is peeled off, thereby forming a source electrode 13, a source wiring 13a, and a drain electrode. 14.
使用混有四氫萘與6,13-雙(三異丙基矽烷基乙炔基)稠五苯(TIPS-稠五苯)的溶液作為半導體層形成用材料。對於半導體層15的形成係採用柔版印刷法。柔版印刷係使用感光性樹脂柔版與150線之網紋輥(Anilox roll)，形成寬100μm之條帶形狀之半導體層15。印刷後，於100℃加以乾燥60分鐘而形成半導體層15。 A solution in which tetrahydronaphthalene and 6,13-bis(triisopropyldecylethynyl) pentacene (TIPS-fused pentabenzene) are mixed is used as a material for forming a semiconductor layer. For the formation of the semiconductor layer 15, a flexographic printing method is employed. Flexographic printing uses a photosensitive resin flexo and a 150-line Anilox roll to form a strip-shaped semiconductor layer 15 having a width of 100 μm. After printing, it was dried at 100 ° C for 60 minutes to form a semiconductor layer 15.
接著形成保護層16。使用氟系樹脂作為保護層形成材料。對於保護層的形成係採用柔版印刷。作為柔版係使用感光性樹脂柔版，並使用150線網紋輥。使用條帶形狀之柔版，以覆蓋半導體層15的方式印刷線寬150μm之條帶形狀保護層16。保護層16之線寬的偏差變動為±10μm。其後，於100℃加以乾燥90分鐘而形成保護層16。 A protective layer 16 is then formed. A fluorine-based resin is used as a protective layer forming material. Flexographic printing is used for the formation of the protective layer. A photosensitive resin flexo was used as the flexo system, and a 150-line anilox roll was used. A strip-shaped protective layer 16 having a line width of 150 μm was printed in such a manner as to cover the semiconductor layer 15 using a flexographic strip shape. The variation in the line width of the protective layer 16 is ±10 μm. Thereafter, it was dried at 100 ° C for 90 minutes to form a protective layer 16.
接著形成層間絕緣膜17。使用環氧樹脂作為層間絕緣膜形成材料。採用網版印刷進行形成，於90℃加以乾燥1小時，作成層間絕緣膜17。層間絕緣膜17係以覆蓋陣列全體的方式所形成，其具有50μm見方之通孔17a，用以將像素電極18與汲極電極14導通。由於該通孔17a的中心位置A係位於通過保護層16之條帶間的中點且與條帶平行的直線C上，因此，縱使在保護層16之條帶線寬較設計值為寬的部位，也不會阻礙通孔部之導通。 Next, an interlayer insulating film 17 is formed. An epoxy resin is used as an interlayer insulating film forming material. The formation was carried out by screen printing, and dried at 90 ° C for 1 hour to form an interlayer insulating film 17. The interlayer insulating film 17 is formed to cover the entire array, and has a via hole 17a of 50 μm square for conducting the pixel electrode 18 and the drain electrode 14. Since the center position A of the through hole 17a is located on the straight line C passing through the midpoint between the strips of the protective layer 16 and parallel to the strip, even if the line width at the protective layer 16 is wider than the design value The part does not obstruct the conduction of the through hole.
其後，形成像素電極18。使用銀糊作為像素電極材料。對於像素電極18的形成係採用網版印刷，並使銀糊完全填充於通孔17a內。圖案形成後，於90℃加以乾燥1小時，藉此作成像素電極18。 Thereafter, the pixel electrode 18 is formed. Silver paste was used as the pixel electrode material. For the formation of the pixel electrode 18, screen printing is employed, and the silver paste is completely filled in the through hole 17a. After the pattern was formed, it was dried at 90 ° C for 1 hour to form a pixel electrode 18.
爾後，在對向電極之間夾持電泳媒體20來驅動本實施例之顯示器。雖發生保護層16之線寬偏差變動所致之線寬化(+10μm)、與保護層16之對準偏移(朝左側10μm)及層間絕緣膜17之對準偏移(朝左側10μm)，但由於層間絕緣膜17之通孔17a位於保護層16之條帶間的中央，故可達成像素電極18與汲極電極14間之導通，且可無 點缺陷地進行良好的影像顯示。 Thereafter, the electrophoretic medium 20 is sandwiched between the counter electrodes to drive the display of the embodiment. The line width (+10 μm) due to the variation in the line width deviation of the protective layer 16 and the alignment offset from the protective layer 16 (10 μm toward the left side) and the alignment offset of the interlayer insulating film 17 (10 μm toward the left side) occur. However, since the via hole 17a of the interlayer insulating film 17 is located at the center between the strips of the protective layer 16, the conduction between the pixel electrode 18 and the drain electrode 14 can be achieved, and Good image display with point defects.
(比較例1) (Comparative Example 1)
在第5圖、第6圖顯示包含比較例1之底部閘極底部接觸型可撓性薄膜電晶體的薄膜電晶體陣列3之圖案配置平面圖及剖面結構，並說明其製造方法。本薄膜電晶體其1元件之尺寸為300μm×300μm，在薄膜電晶體陣列全體，有240×320個該元件。 Fig. 5 and Fig. 6 show a plan layout plan view and a cross-sectional structure of a thin film transistor array 3 including a bottom gate bottom contact type flexible thin film transistor of Comparative Example 1, and a description thereof will be given. The thickness of one element of the thin film transistor is 300 μm × 300 μm, and there are 240 × 320 such elements in the entire film transistor array.
使用聚萘二甲酸乙二酯(PEN)薄膜作為絕緣基板10，並以與實施例1同樣的方式形成閘極電極11、電容電極19、閘極絕緣膜12、源極電極13、源極配線13a、汲極電極14、半導體層15、保護層16。 A polyethylene naphthalate (PEN) film was used as the insulating substrate 10, and the gate electrode 11, the capacitor electrode 19, the gate insulating film 12, the source electrode 13, and the source wiring were formed in the same manner as in the first embodiment. 13a, a drain electrode 14, a semiconductor layer 15, and a protective layer 16.
對於層間絕緣膜17的形成係採用與實施例1同樣的材料及印刷方法。惟，用以將像素電極18與汲極電極14導通的50μm見方之通孔17a的中心位置A，係設計成在較通過保護層16之條帶間的中點且與條帶平行的直線C上更朝左側偏移50μm的位置。其結果，比起通孔17a的中心位於直線C上者，保護層16與層間絕緣膜17之通孔17a端部的空白部分縮小50μm。其結果，因保護層16之線寬偏差變動所致之線寬化、與保護層16及層間絕緣膜17之對準偏移，致使保護層16端部與層間絕緣膜17之通孔17a端部的間隔因一部分的保護層16露出至通孔部分而形成。 The same material and printing method as in Example 1 were used for the formation of the interlayer insulating film 17. However, the center position A of the 50 μm square through hole 17a for conducting the pixel electrode 18 and the drain electrode 14 is designed to be a straight line C parallel to the strip at a midpoint between the strips passing through the protective layer 16. The upper side is shifted to the left side by 50 μm. As a result, the blank portion of the end portion of the through hole 17a of the protective layer 16 and the interlayer insulating film 17 is reduced by 50 μm than the center of the through hole 17a on the straight line C. As a result, the line width due to the variation in the line width variation of the protective layer 16 and the alignment of the protective layer 16 and the interlayer insulating film 17 are shifted, so that the end of the protective layer 16 and the through hole 17a of the interlayer insulating film 17 are formed. The interval of the portions is formed by exposing a portion of the protective layer 16 to the via portion.
與實施例1同樣地形成像素電極18，並在其與對向電極之間夾持電泳媒體20來驅動比較例1之顯示器，結果，在保護層16露出至層間絕緣膜17之通孔部分而 不幸形成的部位，像素電極18與汲極電極14之導通受阻，且點缺陷增加，無法進行良好的顯示。 The pixel electrode 18 was formed in the same manner as in the first embodiment, and the electrophoretic medium 20 was sandwiched between the counter electrode and the counter electrode to drive the display of Comparative Example 1. As a result, the protective layer 16 was exposed to the via portion of the interlayer insulating film 17. In the unfortunately formed portion, the conduction between the pixel electrode 18 and the drain electrode 14 is blocked, and the dot defect is increased, and good display cannot be performed.
本發明之可撓性薄膜電晶體陣列非僅可利用於作為可撓性電子紙張、可撓性有機EL顯示器等的開關元件，尚可應用於可撓性顯示器或IC卡、IC標籤等廣範圍。 The flexible film transistor array of the present invention can be used not only as a switching element such as a flexible electronic paper or a flexible organic EL display, but also in a wide range such as a flexible display, an IC card, or an IC tag. .
1‧‧‧薄膜電晶體陣列 1‧‧‧Thin-film array
11‧‧‧閘極電極 11‧‧‧ gate electrode
13a‧‧‧源極配線 13a‧‧‧Source wiring
14‧‧‧汲極電極 14‧‧‧汲electrode
15‧‧‧半導體層 15‧‧‧Semiconductor layer
16‧‧‧保護層 16‧‧‧Protective layer
17‧‧‧層間絕緣膜 17‧‧‧Interlayer insulating film
17a‧‧‧通孔 17a‧‧‧through hole
19‧‧‧電容電極 19‧‧‧Capacitance electrode
A‧‧‧中心位置 A‧‧‧ central location
C‧‧‧直線 C‧‧‧ Straight line
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| US20020127857A1 (en) * | 2001-03-08 | 2002-09-12 | Hiroyuki Ohgami | Active matrix substrate and method for producing the same |
| TW200603408A (en) * | 2004-02-05 | 2006-01-16 | Samsung Electronics Co Ltd | TFT array substrate, method for manufacturing the same, and liquid crystal display having the same |
| US20100201932A1 (en) * | 2009-02-09 | 2010-08-12 | Hitachi Displays, Ltd. | Liquid crystal display device |
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| TW200603408A (en) * | 2004-02-05 | 2006-01-16 | Samsung Electronics Co Ltd | TFT array substrate, method for manufacturing the same, and liquid crystal display having the same |
| US20100201932A1 (en) * | 2009-02-09 | 2010-08-12 | Hitachi Displays, Ltd. | Liquid crystal display device |
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