JP6537960B2 - Method of forming insulating layer, method of producing electronic device and electronic device - Google Patents

Method of forming insulating layer, method of producing electronic device and electronic device Download PDF

Info

Publication number
JP6537960B2
JP6537960B2 JP2015234443A JP2015234443A JP6537960B2 JP 6537960 B2 JP6537960 B2 JP 6537960B2 JP 2015234443 A JP2015234443 A JP 2015234443A JP 2015234443 A JP2015234443 A JP 2015234443A JP 6537960 B2 JP6537960 B2 JP 6537960B2
Authority
JP
Japan
Prior art keywords
wiring
insulating layer
wiring pattern
pattern
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015234443A
Other languages
Japanese (ja)
Other versions
JP2017103318A (en
Inventor
裕太郎 古川
裕太郎 古川
佐藤 光範
光範 佐藤
豊 竹澤
豊 竹澤
彰利 坂上
彰利 坂上
充俊 内藤
充俊 内藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Aviation Electronics Industry Ltd
Original Assignee
Japan Aviation Electronics Industry Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Aviation Electronics Industry Ltd filed Critical Japan Aviation Electronics Industry Ltd
Priority to JP2015234443A priority Critical patent/JP6537960B2/en
Priority to US15/363,421 priority patent/US10064293B2/en
Publication of JP2017103318A publication Critical patent/JP2017103318A/en
Priority to US15/860,731 priority patent/US10492307B2/en
Priority to US15/991,294 priority patent/US10499513B2/en
Application granted granted Critical
Publication of JP6537960B2 publication Critical patent/JP6537960B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1241Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • H05K3/125Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing by ink-jet printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1275Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by other printing techniques, e.g. letterpress printing, intaglio printing, lithographic printing, offset printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04112Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0108Transparent
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09236Parallel layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09254Branched layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979Redundant conductors or connections, i.e. more than one current path between two points
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/013Inkjet printing, e.g. for printing insulating material or resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography
    • H05K2203/0534Offset printing, i.e. transfer of a pattern from a carrier onto the substrate by using an intermediate member
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base

Description

この発明はフレキソ印刷法やインクジェット印刷法によって絶縁層を形成する方法、その絶縁層の形成方法を用いる電子デバイスの生産方法に関し、さらに配線パターンと絶縁層とを含んで構成される電子デバイスに関する。   The present invention relates to a method of forming an insulating layer by flexographic printing or ink jet printing, a method of producing an electronic device using the method of forming the insulating layer, and further relates to an electronic device including a wiring pattern and an insulating layer.

電子デバイスにおける配線パターンや絶縁層等の形成に真空プロセスを用いず、印刷プロセスを用いれば、高価な成膜装置は不要となり、コストを削減することができ、生産性の向上を図ることができる。   If a vacuum process is not used to form a wiring pattern or an insulating layer in an electronic device and a printing process is used, an expensive film forming apparatus becomes unnecessary, cost can be reduced, and productivity can be improved. .

特許文献1には薄膜トランジスタアレイにおいて、半導体層、半導体層を覆う保護層、アレイ全体を覆う層間絶縁膜の形成に、それぞれフレキソ印刷法やインクジェット印刷法等を用いることが記載されている。   Patent Document 1 describes that in a thin film transistor array, a flexo printing method, an inkjet printing method, or the like is used to form a semiconductor layer, a protective layer covering the semiconductor layer, and an interlayer insulating film covering the entire array.

特許文献1における薄膜トランジスタアレイは層間絶縁膜の上に画素電極が形成された構成となっており、層間絶縁膜には画素電極とドレイン電極との導通を図るためにビアホールが設けられている。   The thin film transistor array in Patent Document 1 has a configuration in which a pixel electrode is formed on an interlayer insulating film, and a via hole is provided in the interlayer insulating film in order to electrically connect the pixel electrode and the drain electrode.

特開2014−191169号公報JP, 2014-191169, A

ところで、フレキソ印刷法やインクジェット印刷法では粘性の低いインキを用いるため、インキの流動が顕著であり、インキの流動による所望の印刷パターンからのインキのはみ出し等に注意を必要とする。   By the way, in the flexographic printing method and the ink jet printing method, since the ink having a low viscosity is used, the flow of the ink is remarkable, and it is necessary to pay attention to the protrusion of the ink from the desired printing pattern by the flow of the ink.

特許文献1では層間絶縁膜のビアホールによって、層間絶縁膜の上層に位置する画素電極と導通されるドレイン電極はビアホールの全底面を形成するべたの電極となっているため、例えば層間絶縁膜を形成する絶縁性インキがビアホールの底面に位置するドレイン電極上にはみ出したとしても、導通不良が生じる可能性は小さいと言える。   In Patent Document 1, the drain electrode electrically connected to the pixel electrode located in the upper layer of the interlayer insulating film by the via hole of the interlayer insulating film is a solid electrode which forms the entire bottom surface of the via hole. Even if the insulating ink to be formed is projected onto the drain electrode located on the bottom of the via hole, the possibility of the occurrence of the conduction failure can be said to be small.

しかしながら、例えばビアホールの底面に露出して位置する電気的接続をすべき導体が、例えばビアホールの周縁から延びている線状の配線である場合には、絶縁性インキが配線を伝わって流動して配線を覆ってしまうといったことが起こり得るため、導通不良が生じる可能性は大きくなる。   However, for example, when the conductor to be exposed and located on the bottom surface of the via hole is, for example, a linear wire extending from the periphery of the via hole, the insulating ink flows along the wire and flows. Since the wiring may be covered, the possibility of conduction failure increases.

この発明の目的はこのような問題に鑑み、他の導体との電気的接続に用いる接触領域を露出させつつ配線パターンを被覆する絶縁層をフレキソ印刷法もしくはインクジェット印刷法で形成するものとし、その場合に絶縁性インキが配線パターンの配線を伝わって流動し、接触領域に及んで導通不良が生じることがないようにした絶縁層の形成方法及びそのような絶縁層の形成方法を用いる電子デバイスの生産方法を提供することにあり、さらに配線パターンと、配線パターンの電気的接続に用いる接触領域が露出するように配線パターンを被覆する絶縁層とを含む電子デバイスにおいて、絶縁層をフレキソ印刷法やインクジェット印刷法等の粘性の低いインキを用いる印刷法で形成することができるようにした電子デバイスを提供することにある。   In view of such problems, an object of the present invention is to form an insulating layer covering a wiring pattern while exposing a contact area used for electrical connection with another conductor by flexographic printing method or inkjet printing method, In the case of an electronic device using a method of forming an insulating layer and a method of forming such an insulating layer, in which the insulating ink flows along the wiring of the wiring pattern to prevent the occurrence of conduction failure over the contact region. In an electronic device further comprising providing a wiring pattern and an insulating layer covering the wiring pattern so as to expose a contact region used for electrical connection of the wiring pattern, the insulating layer is formed by flexography or To provide an electronic device capable of being formed by a printing method using a low viscosity ink such as an inkjet printing method That.

請求項1の発明によれば、基体の上に形成された導体膜よりなる配線パターンを、配線パターンに属し、他の導体との電気的接続に用いる接触領域を露出させつつ被覆する絶縁層の形成方法において、絶縁層はフレキソ印刷法もしくはインクジェット印刷法のいずれかにより、定められた印刷パターンで絶縁性インキを配線パターンの上に塗布して硬化させることで形成され、前記印刷パターンは前記接触領域を内部に含む非印刷領域を形成する外郭線によって画定され、配線パターンは前記非印刷領域において前記外郭線から延びて前記接触領域に至る配線の経路のうちで最短のものを構成する幹配線と、幹配線の両側に少なくとも1本ずつ設けられ、幹配線の途中から枝分かれして前記外郭線に接することなく終端する枝配線とを有して形成され、絶縁性インキは塗布の後、幹配線の一部及び枝配線の少なくとも一部を伝わって濡らし、かつ前記接触領域には到達しない状態で硬化される。   According to the invention of claim 1, an insulating layer which belongs to the wiring pattern and covers the wiring area formed of the conductor film formed on the base while exposing the contact area used for the electrical connection with the other conductor. In the forming method, the insulating layer is formed by applying and curing the insulating ink on the wiring pattern with a defined printing pattern by either the flexographic printing method or the ink jet printing method, and the printing pattern is the above-mentioned contact A main wiring defined by an outline forming a non-printing area including an area inside, and a wiring pattern extending from the outline in the non-printing area to constitute the shortest one of the wiring paths leading to the contact area And at least one branch wiring provided on each side of the trunk wiring, the branch wiring branching off from the middle of the trunk wiring and terminating without contacting the outer wiring. Made, insulating ink after application, wet and transmitted at least a portion of the part and the branch wirings of main wirings, and the said contact area is cured in a state that does not reach.

請求項2の発明によれば、基体の上に形成された導体膜よりなる配線パターンを、配線パターンに属し、他の導体との電気的接続に用いる接触領域を露出させつつ被覆する絶縁層の形成方法において、絶縁層はフレキソ印刷法もしくはインクジェット印刷法のいずれかにより、定められた印刷パターンで絶縁性インキを配線パターンの上に塗布して硬化させることで形成され、前記印刷パターンは前記接触領域を内部に含む非印刷領域を形成する外郭線によって画定され、配線パターンは前記非印刷領域において前記外郭線から延びて前記接触領域に至る配線の経路のうちの最短の経路の途中に、3本以上の配線が集まる第1の結節点で分岐し、3本以上の配線が集まる第2の結節点で合流して2つの経路を構成し、2つの経路のいずれか一方が前記最短の経路に参与する分岐配線を少なくとも1つ含んで形成され、絶縁性インキは塗布の後、前記最短の経路の少なくとも一部を伝わって濡らし、かつ前記接触領域には到達しない状態で硬化される。   According to the second aspect of the present invention, there is provided an insulating layer which belongs to the wiring pattern and covers the wiring area formed of the conductor film formed on the base while exposing the contact area used for the electrical connection with another conductor. In the forming method, the insulating layer is formed by applying and curing the insulating ink on the wiring pattern with a defined printing pattern by either the flexographic printing method or the ink jet printing method, and the printing pattern is the above-mentioned contact And a wiring pattern is defined by an outline forming a non-printing area including the area in the middle, and a wiring pattern extends from the outline in the non-printing area to the middle of the shortest one of the wiring paths to the contact area. Bifurcated at a first node where more than this wiring gathers, and merges at a second nod where three or more wiring gathers to form two paths, one of two paths Is formed including at least one branch wiring that participates in the shortest path, the insulating ink wets along at least a portion of the shortest path after application, and does not reach the contact area Be cured.

請求項3の発明では請求項1又は2の発明において、配線パターンはグラビアオフセット印刷法で形成されているものとされる。   In the invention of claim 3, in the invention of claim 1 or 2, the wiring pattern is formed by the gravure offset printing method.

請求項4の発明によれば、電子デバイスの生産方法は請求項1記載の絶縁層の形成方法を用いる。   According to the invention of claim 4, the method for producing an electronic device uses the method for forming an insulating layer according to claim 1.

請求項5の発明によれば、電子デバイスの生産方法は請求項2記載の絶縁層の形成方法を用いる。   According to the invention of claim 5, the method for producing an electronic device uses the method for forming an insulating layer according to claim 2.

請求項6の発明では請求項4又は5の発明において、配線パターンはグラビアオフセット印刷法で形成されているものとされる。   In the invention of claim 6, in the invention of claim 4 or 5, the wiring pattern is formed by the gravure offset printing method.

請求項7の発明によれば、基体の上に形成された導体膜よりなる配線パターンと、配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように配線パターンを被覆する絶縁層とを含む電子デバイスにおいて、絶縁層は前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、配線パターンは前記非被覆領域において前記外郭線から延びて前記接触領域に至る配線の経路のうちで最短のものを構成する幹配線と、幹配線の両側に少なくとも1本ずつ設けられ、幹配線の途中から枝分かれして前記外郭線に接することなく終端する枝配線とを備え、絶縁層を構成する絶縁材料と同一の絶縁材料が幹配線の一部及び枝配線の少なくとも一部に前記外郭線から連続して付着しており、かつ前記接触領域には付着していないものとされる。   According to the invention of claim 7, the wiring pattern is covered such that the wiring pattern formed of the conductor film formed on the base body belongs to the wiring pattern and the contact area used for the electrical connection with the other conductor is exposed. An electronic device including an insulating layer, the insulating layer having a pattern defined by an outer line forming an uncovered area including the contact area therein, and a wiring pattern extending from the outer line in the uncovered area And at least one main wiring forming the shortest one of the wiring paths leading to the contact area, and at least one each on both sides of the main wiring, and branching off from the middle of the main wiring and ending without touching the outer outline And the same insulating material as the insulating material constituting the insulating layer is continuously attached to a part of the main wiring and at least a part of the branch wiring from the outer wiring, and The touch area is assumed not to adhere.

請求項8の発明によれば、基体の上に形成された導体膜よりなる配線パターンと、配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように配線パターンを被覆する絶縁層とを含む電子デバイスにおいて、絶縁層は前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、配線パターンは前記非被覆領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちの最短の経路の途中に、3本以上の配線が集まる第1の結節点で分岐し、3本以上の配線が集まる第2の結節点で合流して2つの経路を構成し、2つの経路のいずれか一方が前記最短の経路に参与する分岐配線を少なくとも1つ含んでおり、絶縁層を構成する絶縁材料と同一の絶縁材料が前記最短の経路の少なくとも一部に前記外郭線から連続して付着しており、かつ前記接触領域には付着していないものとされる。   According to the invention of claim 8, the wiring pattern is covered such that the wiring pattern formed of the conductor film formed on the base body belongs to the wiring pattern and the contact area used for the electrical connection with the other conductor is exposed. And an insulating layer having a pattern defined by an outline forming an uncovered area including the contact area therein, and a wiring pattern in the uncovered area from the outer line In the middle of the shortest route of the wires extending to the contact area, a branch is made at a first node where three or more wires gather, and a junction at a second node where three or more wires gather To form two paths, one of the two paths includes at least one branch wiring participating in the shortest path, and the same insulating material as the insulating material forming the insulating layer is the shortest. Path is small Ku and are attached continuously from the contour part also, and the said contact area being assumed not to adhere.

請求項9の発明によれば、基体の上に形成された導体膜よりなる配線パターンと、配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように配線パターンを被覆する絶縁層とを含む電子デバイスにおいて、絶縁層は前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、配線パターンは前記非被覆領域において前記外郭線から延びて前記接触領域に至る配線の経路のうちで最短のものを構成する幹配線と、幹配線の両側に少なくとも1本ずつ設けられ、幹配線の途中から枝分かれして前記外郭線に接することなく終端する枝配線とを備えているものとされる。   According to the invention of claim 9, the wiring pattern is covered such that the wiring pattern formed of the conductor film formed on the base body belongs to the wiring pattern and the contact area used for the electrical connection with the other conductor is exposed. An electronic device including an insulating layer, the insulating layer having a pattern defined by an outer line forming an uncovered area including the contact area therein, and a wiring pattern extending from the outer line in the uncovered area And at least one main wiring forming the shortest one of the wiring paths leading to the contact area, and at least one each on both sides of the main wiring, and branching off from the middle of the main wiring and ending without touching the outer outline And branch wiring.

請求項10の発明によれば、基体の上に形成された導体膜よりなる配線パターンと、配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように配線パターンを被覆する絶縁層とを含む電子デバイスにおいて、絶縁層は前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、配線パターンは前記非被覆領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちの最短の経路の途中に、3本以上の配線が集まる第1の結節点で分岐し、3本以上の配線が集まる第2の結節点で合流して2つの経路を構成し、2つの経路のいずれか一方が前記最短の経路に参与する分岐配線を少なくとも1つ含んでいるものとされる。   According to the invention of claim 10, the wiring pattern is covered such that the wiring pattern formed of the conductor film formed on the base body belongs to the wiring pattern and the contact region used for the electrical connection with the other conductor is exposed. And an insulating layer having a pattern defined by an outline forming an uncovered area including the contact area therein, and a wiring pattern in the uncovered area from the outer line In the middle of the shortest route of the wires extending to the contact area, a branch is made at a first node where three or more wires gather, and a junction at a second node where three or more wires gather Thus, two paths are configured, and one of the two paths includes at least one branch wiring participating in the shortest path.

請求項11の発明では請求項7乃至10のいずれかの発明において、導体膜は硬化した導電性インキよりなる。   In the invention of claim 11, in the invention of any of claims 7 to 10, the conductor film is made of a cured conductive ink.

この発明によれば、他の導体との電気的接続に用いる接触領域を露出させつつ配線パターンを被覆する絶縁層をフレキソ印刷法やインクジェット印刷法で形成しても、絶縁層を印刷形成する絶縁性インキが配線を伝わって流動して接触領域に到達することがないようにした絶縁層の形成方法及びそのような絶縁層の形成方法を用いる電子デバイスの生産方法を提供することができ、よって接触領域における導通不良の発生を防止することができる。   According to the present invention, the insulating layer is formed by printing the insulating layer even if the insulating layer covering the wiring pattern is formed by the flexo printing method or the ink jet printing method while exposing the contact region used for electrical connection with another conductor. It is possible to provide a method of forming an insulating layer that prevents the conductive ink from flowing along the wiring to reach the contact area, and a method of producing an electronic device using such a method of forming the insulating layer. The occurrence of conduction failure in the contact area can be prevented.

また、この発明による電子デバイスによれば、配線パターンの電気的接続に用いる接触領域が露出するように配線パターンを被覆する絶縁層の形成に、フレキソ印刷法やインクジェット印刷法等の粘性の低いインキを用いる印刷法を用いることができる。   Further, according to the electronic device according to the present invention, it is preferable to use a low viscosity ink such as flexo printing method or inkjet printing method to form the insulating layer covering the wiring pattern so as to expose the contact region used for electrical connection of the wiring pattern. Can be used.

この発明の第1の基本的な実施形態を説明するための図。The figure for demonstrating the 1st basic embodiment of this invention. Aはこの発明の第2の基本的な実施形態を説明するための図、BはAの拡張形を説明するための図。A is a figure for demonstrating the 2nd basic embodiment of this invention, B is a figure for demonstrating the extended form of A. FIG. この発明による電子デバイスの一実施例を示す平面図。The top view which shows one Example of the electronic device by this invention. Aは図3におけるジャンパ線の接続配置部分を仮に従来構成とした場合の構成を工程順に示した図、Bは図3におけるジャンパ線の接続配置部分の構成を工程順に示した図。FIG. 3A is a diagram showing the configuration in the case where the connection arrangement portion of the jumper wire in FIG. 3 is temporarily made conventional, and FIG. 3B is a diagram showing the configuration of the connection arrangement portion of the jumper wire in FIG. Aは図4Aにおける(c)の部分拡大図、Bは図4Bにおける(c)の部分拡大図。A is a partial enlarged view of (c) in FIG. 4A, and B is a partial enlarged view of (c) in FIG. 4B. この発明による電子デバイスの他の実施例を示す平面図。The top view which shows the other Example of the electronic device by this invention. 図6における検査端子が形成されている部分の部分拡大図。The elements on larger scale of the part in which the test terminal in FIG. 6 is formed. 図6における接続部が形成されている部分の構成を説明するための図。The figure for demonstrating the structure of the part in which the connection part in FIG. 6 is formed.

この発明は基体の上に形成された導体膜よりなる配線パターンを、配線パターンに属し、他の導体との電気的接続に用いる接触領域を露出させつつ絶縁層で被覆する場合において、接触領域を内部に含む非被覆領域を形成する絶縁層の外郭線から延びて接触領域に至る配線の途中に、電気抵抗を増大させることなく、インキの保液量を有効に増大させる構造を設けることで、絶縁層を印刷形成する絶縁性インキが流動してきても接触領域に到達することを防止するものであり、まず、初めにこの発明の基本的な実施形態を図1及び図2Aを参照して説明する。   According to the present invention, in the case where the wiring pattern made of the conductor film formed on the substrate belongs to the wiring pattern and is covered with the insulating layer while exposing the contact region used for electrical connection with other conductors, By providing a structure that effectively increases the amount of ink retention without increasing the electrical resistance, in the middle of the wiring extending from the outer line of the insulating layer forming the non-covering region contained inside to the contact region. This is to prevent the insulating ink for printing the insulating layer from reaching the contact area even if it flows, and first, a basic embodiment of the present invention will be described with reference to FIGS. 1 and 2A. Do.

絶縁層の印刷パターンは非印刷領域(非被覆領域)を形成する外郭線によって画定され、この印刷パターンで絶縁性インキを配線パターン上に塗布して硬化させることで絶縁層が形成される。図1における幹配線11は絶縁層20の外郭線20aから延びて接触領域12に至る配線の経路のうちで最短のものを示す。幹配線11の両側には幹配線11の途中から枝分かれして外郭線20aに接することなく終端する枝配線13が1本ずつ設けられている。   The printing pattern of the insulating layer is defined by the outline forming a non-printing area (non-covering area), and the insulating ink is formed on the wiring pattern by the printing pattern to form an insulating layer. The main wiring 11 in FIG. 1 shows the shortest one of the wiring paths extending from the outline 20 a of the insulating layer 20 to the contact area 12. One branch wiring 13 is provided on both sides of the main wiring 11 so as to branch off from the middle of the main wiring 11 and to terminate without contacting the outline 20 a.

配線パターンを、この図1に示したような構成を有するものとすれば、枝配線13は幹配線11との接続点以外にインキが流入する箇所はなく、よって幹配線11を伝わって流動してくる絶縁性インキは枝配線13に分散され、付着して保液されるため、接触領域12に到達しない。即ち、絶縁性インキは塗布の後、幹配線11の一部及び枝配線13の少なくとも一部を伝わって濡らすものの、接触領域12には到達しない状態で硬化される。   Assuming that the wiring pattern has a configuration as shown in FIG. 1, the branch wiring 13 has no place where the ink flows in except at the connection point with the main wiring 11, and therefore flows along the main wiring 11 and flows. Insulating ink that is dispersed is dispersed in the branch wiring 13 and adheres to the holding liquid, and therefore does not reach the contact area 12. That is, after the application, the insulating ink wets along a part of the main wiring 11 and at least a part of the branch wiring 13 but is cured without reaching the contact area 12.

図2Aは絶縁層20の外郭線20aから延びて接触領域12に至る配線の経路のうちの最短の経路の途中に、第1の結節点15aで分岐し、第2の結節点15bで合流して2つの経路を構成し、2つの経路のいずれか一方が最短の経路に参与する分岐配線15を設けたものである。第1及び第2の結節点15a,15bにはこの例では図2Aに示したように、それぞれ4本の配線が集まる構成としている。   FIG. 2A branches at a first node 15a and joins at a second node 15b in the middle of the shortest path of the wiring lines extending from the outer line 20a of the insulating layer 20 to the contact region 12. The two paths are configured, and one of the two paths is provided with the branch wiring 15 participating in the shortest path. As shown in FIG. 2A in this example, four wires are respectively gathered at the first and second nodes 15a and 15b.

配線パターンを、この図2Aに示したような構成を有するものとすれば、2つの結節点15a,15bを含んでなる分岐配線15は配線の分岐による長さの増加分が図1の枝配線13と同じ効果を奏することに加え、結節点15a,15bにはインキの表面張力によりインキ溜りが形成され、インキ溜りが固有の保液能力を持つため、配線14を伝わって流動してくる絶縁性インキは接触領域12に到達しない。即ち、絶縁性インキは塗布の後、最短の経路の少なくとも一部を伝わって濡らすものの、接触領域12には到達しない状態で硬化される。   Assuming that the wiring pattern has a configuration as shown in FIG. 2A, the branch wiring 15 including the two nodes 15a and 15b has an increase in length due to the branching of the wiring of the branch wiring of FIG. In addition to the same effect as in 13, ink reservoirs are formed at the nodes 15a and 15b due to the surface tension of the ink, and since the ink reservoir has an inherent liquid retaining ability, the insulation flowing through the wiring 14 flows Ink does not reach the contact area 12. That is, after being applied, the insulating ink is cured along at least a part of the shortest path but wet, but does not reach the contact area 12.

図1における枝配線13は幹配線11の電気抵抗に影響せず、また図2における分岐配線15は配線の並列接続による電気抵抗減の効果が長さの増加による電気抵抗増加分を上回り、電気的にはかえって有利になることが期待できる。   The branch wiring 13 in FIG. 1 does not affect the electrical resistance of the main wiring 11, and in the branch wiring 15 in FIG. 2, the electrical resistance reduction effect by parallel connection of the wirings exceeds the electrical resistance increase due to the increase in length, In fact, it can be expected to become more advantageous.

この発明では上述したような2つの配線パターンの構成をそれぞれ基本的な実施形態とする。   In the present invention, the configuration of the two wiring patterns as described above is a basic embodiment.

なお、図1における枝配線13は幹配線11の両側に1本ずつ設けられているが、幹配線11の片側につき2本以上設けてもよい。また、枝配線13にさらに配線の枝を複合的に増設してもよい。これらの要素の追加によって限られた面積の中で効果的にインキの保液量を増大させ、接触領域12への絶縁性インキの到達を防ぐことができる。   Although one branch wiring 13 is provided on each side of the trunk wiring 11 in FIG. 1, two or more may be provided on one side of the trunk wiring 11. Further, branches of the wiring may be added to the branch wiring 13 in a combined manner. The addition of these elements can effectively increase the ink holding capacity in a limited area and prevent the insulating ink from reaching the contact area 12.

一方、図2Aにおける分岐配線15も2つ以上累積して形成してもよい。その場合、1つの分岐配線15の第2の結節点15bが隣接する次の分岐配線15の第1の結節点15aを兼ねる集約的な形態が面積効率の点で有利であり、図2Bにその形態を示す。分岐配線15の数を増やせば、その分、接触領域12への絶縁性インキの到達を防ぐ防止効果は増大する。なお、図2Bに示した分岐配線15が累積した列の外側に、さらに配線の枝や結節点を増設してもよい。   On the other hand, two or more branch wirings 15 in FIG. 2A may be accumulated and formed. In that case, the intensive form in which the second node 15b of one branch wiring 15 doubles as the first node 15a of the next branch wiring 15 adjacent thereto is advantageous in terms of area efficiency, which is shown in FIG. 2B. Indicates the form. If the number of branch wires 15 is increased, the effect of preventing the insulating ink from reaching the contact area 12 is increased accordingly. Wiring branches and nodes may be additionally provided outside the column where the branch wirings 15 shown in FIG. 2B are accumulated.

また、図2Bに示した分岐配線15が累積した列を、複数列、隣接するものどうしを接続させて並設してもよい。このような形態において、絶縁層の印刷パターンから各列にそれぞれ流入してくる絶縁性インキの量が等しいと仮定すると、隣接する列どうしの間での絶縁性インキのやりとりは相殺されて隣接する列から実質的にインキが流入することはないのに加え、列どうしの接続点が新たな結節点を構成する分だけ、保液量が顕著に増大する。   Further, the columns in which the branch wirings 15 shown in FIG. 2B are accumulated may be juxtaposed by connecting a plurality of columns and adjacent ones. In such a configuration, assuming that the amounts of insulating ink flowing into the respective rows from the printed pattern of the insulating layer are equal, exchange of the insulating ink between adjacent rows is offset and adjacent to each other. In addition to substantially no inflow of ink from the rows, the amount of retained water is significantly increased by the amount that the connection points between the rows constitute new nodes.

結節点に集まる配線の数は図2A,Bでは4本となっているが、3本以上であればよい。なお、3本の配線が集合するY型よりも図2A,Bに示したような4本の配線が集合するX型の方が結節点の保液量は大きい。   The number of wires collected at the node is four in FIGS. 2A and 2B, but may be three or more. The Y-type in which four wires are gathered as shown in FIGS. 2A and 2B has a larger liquid retention amount at the node point than the Y-type in which three wires are gathered.

次に、上述したような配線パターンの構成及び配線パターンを被覆する絶縁層を有する電子デバイスの構成を具体的に説明する。   Next, the configuration of the wiring pattern as described above and the configuration of the electronic device having the insulating layer covering the wiring pattern will be specifically described.

図3はこのような電子デバイスの一例として静電容量式のタッチパネルの構成を示したものである。   FIG. 3 shows a configuration of a capacitive touch panel as an example of such an electronic device.

このタッチパネルは方形状の透明基板30上に第1の導体膜、絶縁層、第2の導体膜及び保護膜が順次、積層形成された構成を有している。センサ電極列は複数の第1のセンサ電極列40と複数の第2センサ電極列50とよりなる。   The touch panel has a configuration in which a first conductor film, an insulating layer, a second conductor film, and a protective film are sequentially laminated on a rectangular transparent substrate 30. The sensor electrode array comprises a plurality of first sensor electrode arrays 40 and a plurality of second sensor electrode arrays 50.

第1のセンサ電極列40は透明基板30の一辺と平行なX方向に配列された複数の島状電極41と、隣接する島状電極41を連結するジャンパ線42とよりなる。第1のセンサ電極列40は透明基板30の上記一辺と隣接する他辺と平行なY方向に複数、並列配置されて設けられている。第2のセンサ電極列50はY方向に配列された複数の島状電極51と、隣接する島状電極51を連結する連結部52とよりなる。第2のセンサ電極列50はX方向に複数、並列配置されて設けられている。   The first sensor electrode array 40 includes a plurality of island electrodes 41 arranged in the X direction parallel to one side of the transparent substrate 30, and a jumper wire 42 connecting adjacent island electrodes 41. A plurality of first sensor electrode arrays 40 are arranged in parallel in the Y direction parallel to the other side adjacent to the one side of the transparent substrate 30. The second sensor electrode array 50 includes a plurality of island electrodes 51 arranged in the Y direction, and a connection portion 52 connecting adjacent island electrodes 51. A plurality of second sensor electrode arrays 50 are arranged in parallel in the X direction.

各第1のセンサ電極列40のX方向両端には引出し配線61が接続されており、各第2のセンサ電極列50のY方向一端には引出し配線62が接続されている。透明基板30の一辺(下辺)の中央部分には端子63が配列形成されており、引出し配線61,62はそれぞれ端子63まで延びて端子63に接続されている。   A lead wire 61 is connected to both ends of each first sensor electrode row 40 in the X direction, and a lead wire 62 is connected to one end of each second sensor electrode row 50 in the Y direction. Terminals 63 are arranged in the center of one side (lower side) of the transparent substrate 30, and the lead wires 61, 62 extend to the terminals 63 and are connected to the terminals 63, respectively.

第2のセンサ電極列50、引出し配線61,62、端子63及び第1のセンサ電極列40の島状電極41は第1の導体膜によって形成され、第1のセンサ電極列40のジャンパ線42は絶縁層により第1の導体膜と絶縁された第2の導体膜によって形成されている。ジャンパ線42の両端はそれぞれ絶縁層に設けられた貫通穴71を介して島状電極41に接続されている。ジャンパ線42と連結部52は互いに重なる位置に位置されている。なお、図3では詳細図示を省略しているが、第2のセンサ電極列50、第1のセンサ電極列40の島状電極41及び端子63はそれぞれ導体細線のメッシュで形成されている。   The second sensor electrode row 50, the lead wires 61 and 62, the terminals 63, and the island-like electrodes 41 of the first sensor electrode row 40 are formed of the first conductor film, and the jumper wire 42 of the first sensor electrode row 40 is formed. Is formed by a second conductor film which is insulated from the first conductor film by an insulating layer. Both ends of the jumper wire 42 are connected to the island-like electrode 41 through through holes 71 provided in the insulating layer. The jumper wire 42 and the connecting portion 52 are positioned to overlap with each other. Although not shown in detail in FIG. 3, the second sensor electrode row 50 and the island-like electrodes 41 and the terminals 63 of the first sensor electrode row 40 are each formed of a mesh of a conductive thin line.

上記のような構成を有するタッチパネルにおいて、第1及び第2の導体膜よりなる配線パターンはそれぞれ銀粒子などの導電粒子を含んだ導電性インキを用い、この例ではグラビアオフセット印刷法によって形成される。また、絶縁層及び保護膜は絶縁性インキを用い、フレキソ印刷法やインクジェット印刷法によって形成される。   In the touch panel having the configuration as described above, the wiring pattern formed of the first and second conductor films is formed by gravure offset printing in this example using conductive ink containing conductive particles such as silver particles. . Further, the insulating layer and the protective film are formed by a flexographic printing method or an ink jet printing method using an insulating ink.

図4はジャンパ線42の接続配置部分の詳細を示したものであり、図4Bは図1に示した配線パターンを適用した構成を示す。なお、図4Aは比較として図1に示した配線パターンを適用していない構成を示したものである。   FIG. 4 shows details of the connection arrangement portion of the jumper wire 42, and FIG. 4B shows a configuration to which the wiring pattern shown in FIG. 1 is applied. 4A shows a configuration to which the wiring pattern shown in FIG. 1 is not applied for comparison.

図4A,Bにおける(a)〜(c)は工程順に構成を示したものであり、まず、図4Aを参照して説明する。図4A(a)に示したように、第2のセンサ電極列50の島状電極51、連結部52及び第1のセンサ電極40の島状電極41は導体細線のメッシュで形成されており、この配線パターンの上にジャンパ線42の接続部分が露出するように絶縁層70が図4A(b)に示したように形成される。第1のセンサ電極列40の隣接する島状電極41の各端部はそれぞれ絶縁層70の貫通穴71によって図4A(b)に示したように露出される。この例では貫通穴71によって露出している島状電極41のメッシュの一部はX字状をなす。図4A(c)はジャンパ線42が印刷形成され、隣接する島状電極41がジャンパ線42によって接続された状態を示したものである。   (A) to (c) in FIG. 4A and FIG. 4B show the configuration in the order of steps, and will be described first with reference to FIG. 4A. As shown in FIG. 4A (a), the insular electrodes 51 of the second sensor electrode array 50, the connection portion 52, and the insular electrodes 41 of the first sensor electrode 40 are formed of a mesh of a conductive thin wire, An insulating layer 70 is formed as shown in FIG. 4A (b) so that the connection portion of the jumper wire 42 is exposed on the wiring pattern. Each end of the adjacent island-like electrode 41 of the first sensor electrode array 40 is exposed by the through hole 71 of the insulating layer 70 as shown in FIG. 4A (b). In this example, a part of the mesh of the island-like electrode 41 exposed by the through hole 71 has an X shape. FIG. 4A (c) shows a state in which the jumper wire 42 is formed by printing and the adjacent island electrodes 41 are connected by the jumper wire 42.

このようなジャンパ線42による接続において、絶縁層70を印刷形成する絶縁性インキが配線を伝わって流動してくると、電気的接続がとれなくなるといった状況が生じうる。図5Aはこの様子を図4A(c)の一部を拡大して示したものであり、図5A中、破線で囲んだ領域は電気的接続に用いる島状電極41の接触領域41aを示す。矢印fは絶縁性インキの流動を示す。   In such connection by the jumper wire 42, when the insulating ink for printing and forming the insulating layer 70 flows along the wiring and flows, a situation may occur in which the electrical connection can not be made. FIG. 5A shows this state as an enlarged view of a part of FIG. 4A (c). In FIG. 5A, a region surrounded by a broken line shows a contact region 41a of the island-like electrode 41 used for electrical connection. Arrow f indicates the flow of insulating ink.

矢印fで示したように絶縁性インキが貫通穴71を囲む絶縁層70の外郭線72から配線を伝わって流動してくると接触領域41aが絶縁性インキによって覆われ、電気的接続がとれなくなるといった状況が生じる。   As shown by the arrow f, when the insulating ink flows along the wiring from the outer line 72 of the insulating layer 70 surrounding the through hole 71 and flows, the contact area 41a is covered with the insulating ink and the electrical connection can not be made Situations such as

これに対し、この例では図4B(a)に破線gで囲んで示したように図1に示した配線パターンの構成を適用する。図4B(b)、図4B(c)及び図5Bはそれぞれ図4A(b)、図4A(c)及び図5Aと対応する構成を示したものである。   On the other hand, in this example, the configuration of the wiring pattern shown in FIG. 1 is applied as shown by the dashed line g in FIG. 4B (a). FIGS. 4B (b), 4B (c) and 5B show configurations corresponding to FIGS. 4A (b), 4A (c) and 5A, respectively.

絶縁層70の貫通穴71によって露出している島状電極41のメッシュの一部はX字状をなしており、この例では接触領域41aに至る4つの配線41bをいずれも図1における幹配線11に対応するものとして、枝配線41cを各配線41bの両側に1本ずつ設けている。これにより、矢印fで示したように絶縁性インキが配線41bを伝わって流動してきても、絶縁性インキが接触領域41aに到達するのを防止できるものとなっており、よって導通不良が生じることなく、ジャンパ線42を良好に接続することができるものとなっている。   A part of the mesh of the island-like electrode 41 exposed by the through hole 71 of the insulating layer 70 has an X shape, and in this example, the four wires 41b leading to the contact region 41a are all main wires in FIG. As one corresponding to 11, one branch wiring 41c is provided on each side of each wiring 41b. As a result, even if the insulating ink flows along the wiring 41b as shown by the arrow f, the insulating ink can be prevented from reaching the contact region 41a, thereby causing a conduction failure. Instead, the jumper wire 42 can be connected well.

次に、図2に示した配線パターンを適用した電子デバイスの例を説明する。   Next, an example of an electronic device to which the wiring pattern shown in FIG. 2 is applied will be described.

図6は図2に示した配線パターンの構成を有する静電容量式のタッチパネルの構成を示したものである。   FIG. 6 shows the configuration of a capacitive touch panel having the configuration of the wiring pattern shown in FIG.

このタッチパネルは図3に示したタッチパネルと同様、方形状の透明基板30上に第1の導体膜、絶縁層、第2の導体膜及び保護膜が順次、積層形成された構成を有し、第1及び第2の導体膜よりなる配線パターンはそれぞれ導電性インキを用い、グラビアオフセット印刷法によって形成され、絶縁層及び保護膜は絶縁性インキを用い、フレキソ印刷法やインクジェット印刷法によって形成されるものとなっている。   Similar to the touch panel shown in FIG. 3, this touch panel has a configuration in which a first conductor film, an insulating layer, a second conductor film and a protective film are sequentially laminated on a rectangular transparent substrate 30, and The wiring pattern consisting of the first and second conductor films is formed by gravure offset printing using conductive ink, and the insulating layer and the protective film are formed by flexographic printing or ink jet printing using insulating ink. It has become a thing.

図3に示したタッチパネルとはセンサ電極列の形成の仕方に違いがあり、この例では第1の導体膜によってX方向に配列された複数の島状電極41と、隣接する島状電極41を連結する連結部43とよりなる第1のセンサ電極列40’がY方向に複数、並列配置されて形成され、絶縁層によって第1の導体膜と絶縁された第2の導体膜によってY方向に配列された複数の島状電極51と、隣接する島状電極51を連結する連結部52とよりなる第2のセンサ電極列50’がX方向に複数、並列配置されて形成されている。第1のセンサ電極列40’と第2のセンサ電極列50’は互いに絶縁された状態で交差され、連結部43と52は互いに重なる位置に位置されている。   The touch panel shown in FIG. 3 differs in the method of forming the sensor electrode array, and in this example, a plurality of island electrodes 41 arranged in the X direction by the first conductor film and the adjacent island electrodes 41 are used. A plurality of first sensor electrode arrays 40 'each including a connecting portion 43 to be connected are formed in parallel in the Y direction, and formed in the Y direction by the second conductor film insulated from the first conductor film by the insulating layer. A plurality of second sensor electrode arrays 50 ′ each including a plurality of arrayed island electrodes 51 and a connecting portion 52 connecting adjacent island electrodes 51 are formed in parallel in the X direction. The first sensor electrode array 40 'and the second sensor electrode array 50' are intersected in a mutually insulated state, and the connection portions 43 and 52 are positioned so as to overlap each other.

引出し配線61,62及び端子63は第1の導体層によって形成されており、引出し配線62の、端子63と接続されている一端と反対側の他端には第2のセンサ電極列50’と接続される接続部62aが形成されている。第2のセンサ電極列50’と接続部62aとは絶縁層に形成された貫通穴73を介して互いに接続される。   The lead wires 61 and 62 and the terminal 63 are formed by the first conductor layer, and the other end of the lead wire 62 opposite to the one end connected to the terminal 63 is a second sensor electrode row 50 ′ A connection portion 62a to be connected is formed. The second sensor electrode array 50 'and the connection portion 62a are connected to each other through a through hole 73 formed in the insulating layer.

一方、各第2のセンサ電極列50’の、接続部62aと接続される一端と反対側の他端には島状電極51に続いて検査端子53が島状電極51と一体に形成されており、保護膜には検査端子53を露出させる貫通穴81が形成されている。   On the other hand, an inspection terminal 53 is formed integrally with the island-like electrode 51 following the island-like electrode 51 at the other end of the second sensor electrode row 50 ′ opposite to one end connected to the connection portion 62a. A through hole 81 for exposing the inspection terminal 53 is formed in the protective film.

第1のセンサ電極列40’、第2のセンサ電極列50’、引出し配線62の接続部62a、端子63及び検査端子53は図3と同様、図6では詳細図示を省略しているが、それぞれ導体細線のメッシュで形成されている。   The first sensor electrode array 40 ', the second sensor electrode array 50', the connection portion 62a of the lead-out wiring 62, the terminal 63, and the inspection terminal 53 are not illustrated in detail in FIG. Each is formed of a mesh of a conductor thin line.

図7は検査端子53が形成されている部分の詳細を透視図で示したものである。検査端子53は第2のセンサ電極列50’を構成する第2の導体膜の上に保護膜を形成した後、各第2のセンサ電極列50’が所定の抵抗値になっているか電気検査を行うために使用されるもので、この検査端子53と端子63とを用いて電気検査が行われる。なお、第1のセンサ電極列40’の同様の検査は第1のセンサ電極列40’の両端から引出し配線61が引き出されているため、対応する2つの端子63を用いて電気検査を行うことができる。   FIG. 7 is a perspective view showing details of the portion where the inspection terminal 53 is formed. The inspection terminal 53 forms a protective film on the second conductive film constituting the second sensor electrode array 50 ', and then it is electrically inspected whether each second sensor electrode array 50' has a predetermined resistance value The electrical test is performed using the test terminal 53 and the terminal 63. In the same inspection of the first sensor electrode array 40 ', an electrical inspection is performed using the corresponding two terminals 63 because the lead wires 61 are drawn out from both ends of the first sensor electrode array 40'. Can.

この図7に示した島状電極51に続く、島状電極51のメッシュより狭ピッチの検査端子53のメッシュの態様は、図2Bに示した分岐配線15が累積した列の外側に、前述したように、さらに配線の枝や結節点を増設した構成に相当する。よって、貫通穴81を囲む保護膜の外郭線82から保護膜を形成する絶縁性インキが島状電極51の配線(メッシュ)を伝わって流動してきても検査端子53全体が絶縁性インキによって覆われてしまうといったことを防ぐことができる。   The mode of the mesh of the inspection terminal 53 whose pitch is narrower than the mesh of the island-like electrode 51 following the island-like electrode 51 shown in FIG. 7 is described above on the outside of the column where the branch wires 15 are accumulated. In other words, this corresponds to a configuration in which branches and nodes of wiring are further added. Therefore, even if the insulating ink for forming the protective film from the outline 82 of the protective film surrounding the through hole 81 flows along the wiring (mesh) of the island-like electrode 51 and flows, the entire inspection terminal 53 is covered with the insulating ink. It is possible to prevent such problems.

図8は第2のセンサ電極列50’と接続される引出し配線62の接続部62aが形成されている部分の詳細を透視図で示したものである。貫通穴73内に露出している接続部62aのメッシュの態様は、図2Bに示した分岐配線15が累積した列を、前述したように、複数列、隣接するものどうしを接続させて並設した構成に相当する。よって、貫通穴73を囲む絶縁層70の外郭線74から絶縁層70を形成する絶縁性インキが接続部62aの配線(メッシュ)を伝わって流動してきても接続部62a全体が絶縁性インキによって覆われてしまうといったことを防ぐことができる。   FIG. 8 is a perspective view showing details of the portion where the connection portion 62a of the lead-out wiring 62 connected to the second sensor electrode row 50 'is formed. As the mesh form of the connecting portion 62a exposed in the through hole 73, as described above, the rows accumulated by the branch wiring 15 shown in FIG. 2B are connected in parallel by connecting a plurality of rows and adjacent ones. This corresponds to the configuration described above. Therefore, even if the insulating ink forming the insulating layer 70 flows from the outer outline 74 of the insulating layer 70 surrounding the through hole 73 through the wiring (mesh) of the connecting portion 62a, the entire connecting portion 62a is covered with the insulating ink. It can prevent you from being broken.

このように他の導体との電気的接続に用いる接触領域をメッシュ配線とすることは、この発明の基本的な実施形態として図2を参照して説明した分岐配線15の構成、機能に基づくものであって、接触領域をメッシュ配線とすることによって導通不良を防止することができる。   As such, the mesh wiring is used as the contact area used for electrical connection with another conductor based on the configuration and function of the branch wiring 15 described with reference to FIG. 2 as the basic embodiment of the present invention. By making the contact area into mesh wiring, conduction failure can be prevented.

なお、メッシュ配線の利用の形態としては、図7や図8に示した形態の他、絶縁層の貫通穴内の全面積にメッシュ配線を形成し、貫通穴を囲む外郭線の全周から配線を伝わって流入する絶縁性インキが貫通穴の中央に構成される接触領域に到達しないものとされる形態も可能である。   As a form of utilization of mesh wiring, in addition to the form shown in FIG. 7 and FIG. 8, mesh wiring is formed over the entire area in the through hole of the insulating layer, and wiring is taken from the entire circumference of the outer line surrounding the through hole. It is also possible that the insulating ink flowing along does not reach the contact area configured at the center of the through hole.

また、メッシュは上記においては構成単位が四辺形のものを示したが、各結節点に3本の配線が集まる正六角形を構成単位とするものであってもよい。   In addition, although the mesh in the above description shows that the structural unit is a quadrilateral, it may be a structural unit that has a regular hexagon in which three wires are gathered at each node.

さらに、接触領域を内部に含む非印刷領域(非被覆領域)を形成する外郭線は絶縁層に設けた貫通穴の外郭線のように非印刷領域の全周を構成して囲む形態の他、外郭線が非印刷領域の外周の一部のみを構成する形態、例えば外郭線と基板の輪郭の一部とによって非印刷領域が囲まれるような形態も含む。   Furthermore, the outline forming the non-printing area (non-covering area) including the contact area in the inside forms and surrounds the entire circumference of the non-printing area like the outline of the through hole provided in the insulating layer, Also included is a form in which the outer outline constitutes only a part of the outer periphery of the non-printed area, for example a form in which the non-printed area is surrounded by the outer outline and a part of the outline of the substrate.

11 幹配線 12 接触領域
13 枝配線 14 配線
15 分岐配線 15a,15b 結節点
20 絶縁層 20a 外郭線
30 透明基板 40,40’ 第1のセンサ電極列
41 島状電極 41a 接触領域
41b 配線 41c 枝配線
42 ジャンパ線 43 連結部
50,50’ 第2のセンサ電極列 51 島状電極
52 連結部 53 検査端子
61,62 引出し配線 62a 接続部
63 端子 70 絶縁層
71 貫通穴 72 外郭線
73 貫通穴 74 外郭線
81 貫通穴 82 外郭線
11 trunk wiring 12 contact area 13 branch wiring 14 wiring 15 branch wiring 15a and 15b node 20 insulation layer 20a outer wiring 30 transparent substrate 40, 40 'first sensor electrode row 41 island-like electrode 41a contact area 41b wiring 41c branch wiring 42 jumper wire 43 connecting portion 50, 50 'second sensor electrode array 51 island-like electrode 52 connecting portion 53 inspection terminal 61, 62 lead wire 62a connecting portion 63 terminal 70 insulating layer 71 through hole 72 outer wire 73 through hole 74 outer frame Wire 81 Through hole 82 Outer wire

Claims (11)

基体の上に形成された導体膜よりなる配線パターンを、前記配線パターンに属し、他の導体との電気的接続に用いる接触領域を露出させつつ被覆する絶縁層の形成方法であって、
前記絶縁層は、フレキソ印刷法もしくはインクジェット印刷法のいずれかにより、定められた印刷パターンで絶縁性インキを前記配線パターンの上に塗布して硬化させることで形成され、
前記印刷パターンは、前記接触領域を内部に含む非印刷領域を形成する外郭線によって画定され、
前記配線パターンは、前記非印刷領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちで最短のものを構成する幹配線と、前記幹配線の両側に少なくとも1本ずつ設けられ、前記幹配線の途中から枝分かれして前記外郭線に接することなく終端する枝配線とを有して形成されており、
前記絶縁性インキは、前記塗布の後、前記幹配線の一部及び前記枝配線の少なくとも一部を伝わって濡らし、かつ前記接触領域には到達しない状態で硬化されることを特徴とする絶縁層の形成方法。
A method of forming an insulating layer which covers a wiring pattern made of a conductor film formed on a substrate, belonging to the wiring pattern and exposing a contact region used for electrical connection with another conductor,
The insulating layer is formed by applying and curing an insulating ink on the wiring pattern in a defined printing pattern by either a flexographic printing method or an inkjet printing method.
The printing pattern is defined by an outline forming a non-printing area including the contact area therein;
The wiring pattern is provided in the non-printing area, at least one main wiring forming the shortest one of the wiring paths extending from the outer contour line to the contact area, and at least one each on the both sides of the main wiring. A branch wiring which branches from the middle of the main wiring and terminates without coming into contact with the outer line;
The insulating layer is characterized in that after the application, the insulating ink wets along a part of the main wiring and at least a part of the branch wiring and is cured without reaching the contact area. How it is formed.
基体の上に形成された導体膜よりなる配線パターンを、前記配線パターンに属し、他の導体との電気的接続に用いる接触領域を露出させつつ被覆する絶縁層の形成方法であって、
前記絶縁層は、フレキソ印刷法もしくはインクジェット印刷法のいずれかにより、定められた印刷パターンで絶縁性インキを前記配線パターンの上に塗布して硬化させることで形成され、
前記印刷パターンは、前記接触領域を内部に含む非印刷領域を形成する外郭線によって画定され、
前記配線パターンは、前記非印刷領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちの最短の経路の途中に、3本以上の配線が集まる第1の結節点で分岐し、3本以上の配線が集まる第2の結節点で合流して2つの経路を構成し、前記2つの経路のいずれか一方が前記最短の経路に参与する分岐配線を少なくとも1つ含んで形成されており、
前記絶縁性インキは、前記塗布の後、前記最短の経路の少なくとも一部を伝わって濡らし、かつ前記接触領域には到達しない状態で硬化されることを特徴とする絶縁層の形成方法。
A method of forming an insulating layer which covers a wiring pattern made of a conductor film formed on a substrate, belonging to the wiring pattern and exposing a contact region used for electrical connection with another conductor,
The insulating layer is formed by applying and curing an insulating ink on the wiring pattern in a defined printing pattern by either a flexographic printing method or an inkjet printing method.
The printing pattern is defined by an outline forming a non-printing area including the contact area therein;
The wiring pattern is branched at a first node at which three or more wires gather in the middle of the shortest route among the routes of the wires extending from the outer line to the contact region in the non-printing region. , And a second node where three or more wires gather to form two paths, and one of the two paths is formed to include at least one branch wire participating in the shortest path. Yes,
The method of forming an insulating layer, wherein the insulating ink is cured after the application, wetted along at least a part of the shortest path, and does not reach the contact area.
請求項1又は2記載の絶縁層の形成方法において、
前記配線パターンはグラビアオフセット印刷法で形成されていることを特徴とする絶縁層の形成方法。
In the method of forming an insulating layer according to claim 1 or 2,
The method for forming an insulating layer, wherein the wiring pattern is formed by a gravure offset printing method.
請求項1記載の絶縁層の形成方法を用いる電子デバイスの生産方法。   A method of producing an electronic device using the method of forming an insulating layer according to claim 1. 請求項2記載の絶縁層の形成方法を用いる電子デバイスの生産方法。   A method of producing an electronic device using the method of forming an insulating layer according to claim 2. 請求項4又は5記載の電子デバイスの生産方法において、
前記配線パターンはグラビアオフセット印刷法で形成されていることを特徴とする電子デバイスの生産方法。
In the method of producing an electronic device according to claim 4 or 5,
The method for producing an electronic device, wherein the wiring pattern is formed by a gravure offset printing method.
基体の上に形成された導体膜よりなる配線パターンと、前記配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように前記配線パターンを被覆する絶縁層とを含む電子デバイスであって、
前記絶縁層は、前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、
前記配線パターンは、前記非被覆領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちで最短のものを構成する幹配線と、前記幹配線の両側に少なくとも1本ずつ設けられ、前記幹配線の途中から枝分かれして前記外郭線に接することなく終端する枝配線とを備え、
前記絶縁層を構成する絶縁材料と同一の絶縁材料が、前記幹配線の一部及び前記枝配線の少なくとも一部に前記外郭線から連続して付着しており、かつ前記接触領域には付着していないことを特徴とする電子デバイス。
An electron including: a wiring pattern formed of a conductor film formed on a substrate; and an insulating layer which belongs to the wiring pattern and covers the wiring pattern so as to expose a contact region used for electrical connection with another conductor. A device,
The insulating layer has a pattern defined by an outline forming an uncovered area including the contact area therein,
The wiring pattern is provided in the non-covering region, at least one main wiring forming the shortest one of the wiring routes extending from the outer contour line to the contact region, and at least one each on the both sides of the main wiring. And branch wiring which branches off in the middle of the main wiring and terminates without coming into contact with the outer line,
The same insulating material as the insulating material constituting the insulating layer is continuously attached to a part of the main wiring and at least a part of the branch wiring from the outer wire, and is attached to the contact area An electronic device characterized by not being.
基体の上に形成された導体膜よりなる配線パターンと、前記配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように前記配線パターンを被覆する絶縁層とを含む電子デバイスであって、
前記絶縁層は、前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、
前記配線パターンは、前記非被覆領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちの最短の経路の途中に、3本以上の配線が集まる第1の結節点で分岐し、3本以上の配線が集まる第2の結節点で合流して2つの経路を構成し、前記2つの経路のいずれか一方が前記最短の経路に参与する分岐配線を少なくとも1つ含んでおり、
前記絶縁層を構成する絶縁材料と同一の絶縁材料が、前記最短の経路の少なくとも一部に前記外郭線から連続して付着しており、かつ前記接触領域には付着していないことを特徴とする電子デバイス。
An electron including: a wiring pattern formed of a conductor film formed on a substrate; and an insulating layer which belongs to the wiring pattern and covers the wiring pattern so as to expose a contact region used for electrical connection with another conductor. A device,
The insulating layer has a pattern defined by an outline forming an uncovered area including the contact area therein,
The wiring pattern is branched at a first nodal point at which three or more wires gather in the middle of the shortest route among the routes of the wires extending from the outer line to the contact region in the non-covering region , And a second node where three or more wires gather to form two paths, and one of the two paths includes at least one branch wire participating in the shortest path,
An insulating material which is the same as the insulating material constituting the insulating layer is continuously attached from at least a part of the shortest path from the outer line, and is not attached to the contact area. Electronic devices.
基体の上に形成された導体膜よりなる配線パターンと、前記配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように前記配線パターンを被覆する絶縁層とを含む電子デバイスであって、
前記絶縁層は、前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、
前記配線パターンは、前記非被覆領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちで最短のものを構成する幹配線と、前記幹配線の両側に少なくとも1本ずつ設けられ、前記幹配線の途中から枝分かれして前記外郭線に接することなく終端する枝配線とを備えていることを特徴とする電子デバイス。
An electron including: a wiring pattern formed of a conductor film formed on a substrate; and an insulating layer which belongs to the wiring pattern and covers the wiring pattern so as to expose a contact region used for electrical connection with another conductor. A device,
The insulating layer has a pattern defined by an outline forming an uncovered area including the contact area therein,
The wiring pattern is provided in the non-covering region, at least one main wiring forming the shortest one of the wiring routes extending from the outer contour line to the contact region, and at least one each on the both sides of the main wiring. An electronic device comprising: a branch wiring branched from the middle of the main wiring and terminated without coming into contact with the outer contour line.
基体の上に形成された導体膜よりなる配線パターンと、前記配線パターンに属し、他の導体との電気的接続に用いる接触領域が露出するように前記配線パターンを被覆する絶縁層とを含む電子デバイスであって、
前記絶縁層は、前記接触領域を内部に含む非被覆領域を形成する外郭線によって画定されたパターンを有し、
前記配線パターンは、前記非被覆領域において、前記外郭線から延びて前記接触領域に至る配線の経路のうちの最短の経路の途中に、3本以上の配線が集まる第1の結節点で分岐し、3本以上の配線が集まる第2の結節点で合流して2つの経路を構成し、前記2つの経路のいずれか一方が前記最短の経路に参与する分岐配線を少なくとも1つ含んでいることを特徴とする電子デバイス。
An electron including: a wiring pattern formed of a conductor film formed on a substrate; and an insulating layer which belongs to the wiring pattern and covers the wiring pattern so as to expose a contact region used for electrical connection with another conductor. A device,
The insulating layer has a pattern defined by an outline forming an uncovered area including the contact area therein,
The wiring pattern is branched at a first nodal point at which three or more wires gather in the middle of the shortest route among the routes of the wires extending from the outer line to the contact region in the non-covering region A second node where three or more wires gather to form two paths, and one of the two paths includes at least one branch wire participating in the shortest path. Electronic devices characterized by
請求項7乃至10記載のいずれかの電子デバイスにおいて、
前記導体膜は硬化した導電性インキよりなることを特徴とする電子デバイス。
The electronic device according to any one of claims 7 to 10,
The said conductive film consists of hardened | cured conductive ink, The electronic device characterized by the above-mentioned.
JP2015234443A 2015-12-01 2015-12-01 Method of forming insulating layer, method of producing electronic device and electronic device Active JP6537960B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2015234443A JP6537960B2 (en) 2015-12-01 2015-12-01 Method of forming insulating layer, method of producing electronic device and electronic device
US15/363,421 US10064293B2 (en) 2015-12-01 2016-11-29 Method for forming insulating layer covering a wiring pattern
US15/860,731 US10492307B2 (en) 2015-12-01 2018-01-03 Method for forming insulating layer, method for producing electronic device, and electronic device
US15/991,294 US10499513B2 (en) 2015-12-01 2018-05-29 Method for forming insulating layer, method for producing electronic device, and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015234443A JP6537960B2 (en) 2015-12-01 2015-12-01 Method of forming insulating layer, method of producing electronic device and electronic device

Publications (2)

Publication Number Publication Date
JP2017103318A JP2017103318A (en) 2017-06-08
JP6537960B2 true JP6537960B2 (en) 2019-07-03

Family

ID=58777932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015234443A Active JP6537960B2 (en) 2015-12-01 2015-12-01 Method of forming insulating layer, method of producing electronic device and electronic device

Country Status (2)

Country Link
US (3) US10064293B2 (en)
JP (1) JP6537960B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102351618B1 (en) 2017-08-28 2022-01-17 삼성디스플레이 주식회사 Display device
CN109669586B (en) 2017-10-16 2022-01-04 日本航空电子工业株式会社 Touch panel
JP6886907B2 (en) 2017-10-31 2021-06-16 日本航空電子工業株式会社 Touch panel and touch panel production method
JP7093190B2 (en) * 2018-02-01 2022-06-29 日本航空電子工業株式会社 Touch panel
CN108803956B (en) * 2018-06-27 2021-08-24 东莞市显触光电科技有限公司 Pure plane special-shaped four-wire resistive touch screen with decorative panels in two-layer structure
JP7122577B2 (en) * 2018-07-31 2022-08-22 パナソニックIpマネジメント株式会社 touch sensor
JP6721667B2 (en) * 2018-12-19 2020-07-15 Nissha株式会社 Touch panel, touch panel module, and touch panel inspection method
JP7195917B2 (en) 2018-12-26 2022-12-26 日本航空電子工業株式会社 Touch panel production method, wiring pattern production method, touch panel and wiring pattern
EP4053686A4 (en) * 2020-06-30 2023-01-18 BOE Technology Group Co., Ltd. Touch structure and touch display panel

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259608B1 (en) * 1999-04-05 2001-07-10 Delphi Technologies, Inc. Conductor pattern for surface mount devices and method therefor
US9128038B2 (en) * 2012-06-21 2015-09-08 Lifescan Scotland Limited Analytical test strip with capillary sample-receiving chambers separated by a physical barrier island
US8947001B2 (en) * 2012-09-06 2015-02-03 Cooledge Lighting Inc. Wiring boards for array-based electronic devices
JP6123413B2 (en) 2013-03-27 2017-05-10 凸版印刷株式会社 Thin film transistor array and image display device
US20140307178A1 (en) * 2013-04-12 2014-10-16 Shenzhen O-Film Tech Co., Ltd Touch screen sensing module, manufacturing method thereof and display device
KR101614429B1 (en) * 2013-09-10 2016-04-21 주식회사 엘지화학 Touch screen using the new type of insulator and method for manufacturing the same
US20150268756A1 (en) * 2013-09-11 2015-09-24 Ronald Steven Cok Multi-area micro-wire structure
US9738807B2 (en) * 2014-10-08 2017-08-22 Kabushiki Kaisha Toshiba Method of forming pattern and pattern
US20170121548A1 (en) * 2015-11-03 2017-05-04 U.S.A. As Represented By The Administrator Of The National Aeronautics And Space Administration Inked Electrical Conductor

Also Published As

Publication number Publication date
US10499513B2 (en) 2019-12-03
JP2017103318A (en) 2017-06-08
US10492307B2 (en) 2019-11-26
US20180132363A1 (en) 2018-05-10
US20170156218A1 (en) 2017-06-01
US20180279488A1 (en) 2018-09-27
US10064293B2 (en) 2018-08-28

Similar Documents

Publication Publication Date Title
JP6537960B2 (en) Method of forming insulating layer, method of producing electronic device and electronic device
CN108389869B (en) Flexible display panel
US9696834B2 (en) Touch screen panel and fabricating method thereof
CN109669586B (en) Touch panel
US8466374B2 (en) Base for circuit board, circuit board, and method of fabricating thereof
JP2005531134A5 (en)
KR102189438B1 (en) Printed wiring
JP2019079133A (en) Touch panel
TWI517318B (en) Substrate having pillar group and semiconductor package having pillar group
JP2011129729A5 (en)
JP5019834B2 (en) Display device substrate and display device
JP2019075069A (en) Touch panel
JP4975398B2 (en) Semiconductor device and manufacturing method thereof
JP2002148654A5 (en)
JP2014149482A (en) Liquid crystal display device
JP6498816B2 (en) Manufacturing method of printed wiring
US11029791B2 (en) Touch panel including a layered structure with first and second mesh terminal layers directly overlaid on each other and touch panel production method
JP2007081042A (en) Semiconductor device
KR102528403B1 (en) A stretchable electronic device and fabrication method for the same
TWI520295B (en) Substrate having pillar group and via group and semiconductor package having pillar group and via group
JP6591508B2 (en) Method for forming insulating film by flexographic printing and flexographic printing plate
KR100290860B1 (en) display panel and method for packaging the same
JP2022091297A (en) Method for producing wiring board and wiring board
JP2017077677A (en) Method for forming insulation film by flexographic printing and flexographic printing plate
KR20110098447A (en) Semiconductor resistance element, semiconductor module comprising the semiconductor resistance element, and processor-based system comprising the semiconductor module

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180905

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190515

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190528

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190605

R150 Certificate of patent or registration of utility model

Ref document number: 6537960

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250