JP2014191169A - Thin film transistor array and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array preventing via holes from being filled with a protective layer material by providing a maximal distance between the via holes of a protective layer and of an interlayer dielectric film to thereby improve production yield.SOLUTION: There is provided a thin film transistor array at least including an insulation substrate, a gate electrode, a gate insulation layer, a source electrode, a drain electrode, a semiconductor layer, a protective layer covering the semiconductor layer, an interlayer dielectric film, and a pixel electrode. The protective layer has a stripe shape parallel to source wiring. The centre position of the via holes of the interlayer dielectric film provided for conduction between the drain electrode and the pixel electrode is positioned on a straight line parallel to a stripe passing through the midpoint of the stripe-shaped protective layers adjacent to each other.

Description

  The present invention relates to a thin film transistor array and an image display device.

  Due to the remarkable development of information technology, information is frequently sent and received at notebook computers and portable information terminals. It is a well-known fact that in the near future, a ubiquitous society that can exchange information regardless of location will come. In such a society, a lighter and thinner information terminal is desired.

  Among electronic members used for such information terminals, the mainstream of semiconductor materials currently used for thin film transistor elements is silicon-based. Since formation of a thin film transistor element using a silicon-based material includes a process at a high temperature, the substrate material of the thin film transistor element is required to withstand the process temperature. For this reason, glass is generally used as a substrate on which thin film transistor elements are formed.

  However, when glass is used in configuring the information terminal described above, the information terminal is heavy, inflexible, and can be broken by a drop impact. Therefore, it can be said that these characteristics resulting from the formation of thin film transistor elements on glass are undesirable as information terminals in the ubiquitous society.

  Therefore, in recent years, organic semiconductors have attracted attention as semiconductor materials for thin film transistors. Organic semiconductor materials do not require a heat treatment step at a high temperature unlike silicon-based materials, and thus have an advantage that they are provided on a flexible plastic substrate. Furthermore, since it can be produced by a printing process without using a vacuum process, there is an advantage that the cost can be reduced.

  In order to form a semiconductor layer from a solution, a spin coating method, a dip method, an ink jet method, or the like can be used. Especially, a semiconductor layer can be formed efficiently by applying a printing process. For example, in Patent Document 1, patterning of an organic semiconductor solution is performed by flexographic printing.

  Furthermore, in Patent Document 2, by making the semiconductor layer into a stripe shape, alignment accuracy can be improved and production efficiency can be further increased.

  Also in the formation of the protective layer, the protective layer can be formed easily and at low cost by applying a wet process. For example, in Patent Document 3, a protective layer is formed by flexographic printing, and a thin film transistor array is simply manufactured.

JP 2006-63334 A JP 2008-235861 A International Publication No. 2010/1007027

  However, when the thin film transistor array is formed by a printing method, the alignment accuracy is low and the variation in pattern shape is large as compared with the conventional patterning method using photolithography, so that a larger alignment margin is required. In particular, when the semiconductor layer and the protective layer are formed by a printing method, an alignment margin must be taken in consideration of variations in both the semiconductor layer and the protective layer. In particular, if the alignment margin of the protective layer is small and the insulating material of the protective layer protrudes over the drain electrode, the via hole in the interlayer insulating film is blocked, and the drain electrode and the pixel electrode cannot be conducted. End up. On the other hand, if the alignment margin is too large, the resolution of the thin film transistor array is lowered and the visibility is lowered.

  Therefore, in the present invention, by maximizing the distance between the protective layer and the via hole of the interlayer insulating film, the thin film transistor array capable of suppressing the protective layer material from blocking the via hole and improving the yield, and An image display device comprising:

  A first invention for solving the above problems includes at least an insulating substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, a semiconductor layer, a protective layer covering the semiconductor layer, and an interlayer. A thin film transistor array comprising an insulating film and a pixel electrode, wherein the protective layer has a stripe shape parallel to the source wiring, and the interlayer insulation provided for conducting the drain electrode and the pixel electrode The thin film transistor array is characterized in that the center position of the via hole of the film is located on a straight line parallel to the stripe passing through the midpoint of the adjacent protective layers in the stripe shape.

  According to a second aspect of the invention, there is provided the thin film transistor array according to the first aspect, wherein a deviation between a center position of the via hole and a position on a straight line parallel to the stripe passing through the midpoint is 40 μm or less. It is.

  A third invention is the thin film transistor array according to the first invention, wherein the semiconductor layer is an organic semiconductor or an oxide semiconductor.

  The fourth invention is the thin film transistor array according to the first invention, wherein the semiconductor layer is formed by one or more of a flexographic printing method, an ink jet printing method, and a screen printing method. .

  The fifth invention is the thin film transistor array according to the first invention, wherein the protective layer is formed of an organic insulating material.

  The sixth invention is the thin film transistor array according to the first invention, wherein the protective layer is formed by one or more of a flexographic printing method, an ink jet printing method, and a screen printing method. .

  According to a seventh aspect, in the first aspect, the interlayer insulating film is formed by any one or more of a flexographic printing method, an ink jet printing method, a screen printing method, and a gravure offset printing method. Is a thin film transistor array.

  The eighth invention is the thin film transistor array according to the first invention, wherein the insulating substrate is a plastic substrate.

  According to a ninth aspect of the present invention, there is provided an image display device comprising the thin film transistor array and an image display medium.

  The tenth invention is the image display device according to the ninth invention, wherein the image display medium is of an electrophoretic method.

  According to the thin film transistor array of the present invention, it is possible to provide a low-cost and high-quality flexible thin film transistor with a high yield. The center position of the via hole in the interlayer insulating film provided for the conduction between the drain electrode of the thin film transistor array and the pixel electrode is on a straight line parallel to the stripe passing through the midpoint of the adjacent stripe-shaped protective layer covering the semiconductor layer. Therefore, the alignment margin can be maximized, the reduction in yield due to line width variation and misalignment can be reduced, and the throughput of the flexible thin film transistor can be improved.

  A thin film transistor array including at least an insulating substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, a semiconductor layer, a protective layer covering the semiconductor layer, an interlayer insulating film, and an upper pixel electrode The protective layer has a stripe shape parallel to the source wiring, and the center position of the via hole of the interlayer insulating film provided for conducting the drain electrode and the pixel electrode is the stripe-shaped protective layer. In addition, the alignment margin of the protective layer can be maximized regardless of the resolution of the thin film transistor array by being positioned on a straight line parallel to the stripe passing through the midpoint between the adjacent protective layer having a stripe shape. Furthermore, the alignment accuracy with an interlayer insulation film or a semiconductor layer improves by making the shape of a protective layer into a stripe.

  By taking into consideration the maximum deviation of 40 μm from the straight line parallel to the stripe passing through the center point of the interlayer insulating film via hole and the middle point of the adjacent stripe-shaped protective layer, It is possible to design a pattern in consideration of alignment error and expansion / contraction of the plastic substrate due to heating during the process.

  By using an organic semiconductor as the semiconductor layer, a wet process can be applied, and a thin film transistor array can be formed in a large area with a short tact time.

  By forming the semiconductor layer by a flexographic printing method, an ink jet printing method, or a screen printing method, a thin film transistor array can be formed with a short tact time even in a large area.

  Since the protective layer is formed of an organic insulating material, a wet process can be applied, and a thin film transistor array can be formed in a large area with a short tact time.

  By forming the protective layer by a flexographic printing method, an ink jet printing method, or a screen printing method, a thin film transistor array can be formed with a short tact time even in a large area.

  Since the interlayer insulating film is formed of an organic insulating material, a wet process can be applied, and a thin film transistor array having a large area can be formed with a short tact time.

  When the insulating substrate is a plastic substrate, a lightweight and flexible thin film transistor array can be manufactured.

1, showing an embodiment of the present invention, is a pattern layout plan view showing a schematic configuration of an entire thin film transistor array. FIG. 2 is a cross-sectional structure of two adjacent elements of this transistor array (sliced between R-R ′ in FIG. 1). The embodiment of Comparative Example 1 is shown, and is a cross-sectional structure of two adjacent elements of this transistor array. 7 is a pattern layout plan view showing a schematic configuration of the entire thin film transistor array in Comparative Example 1. FIG. It is a cross-sectional structure in two adjacent elements in Comparative Example 1 (sliced between R-R 'in FIG. 4).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiments, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.

  1 and 2 show an example of the configuration of the thin film transistor array 1 of the present invention. FIG. 1 is a plan view of a pattern layout of the thin film transistor array 1. FIG. 2 shows a cross-sectional view of the thin film transistor array 1 of FIG. 1 cut along a line R-R ′ passing through the via hole 17 a and perpendicular to the stripe extending direction of the protective layer 16.

  A thin film transistor array including a gate electrode 11, a capacitor electrode 19, a gate insulating layer 12, a source electrode 13, a drain electrode 14, a semiconductor layer 15, a protective layer 16, an interlayer insulating film 17, and a pixel electrode 18 on a plastic substrate 10. The protective layer 16 is made of an organic insulating material and has a stripe shape. Further, as shown in FIG. 2, the center position A of the via hole 17a opened in the interlayer insulating film 17 for conducting the pixel electrode 18 and the drain electrode 14 is the midpoint between the stripe-shaped protective layers 16 adjacent to each other. Is located on a straight line C parallel to the stripe passing through the center hole A, and the deviation between the center position A of the via hole 17a and the straight line C is within 40 μm. A space between two protective layers 16 adjacent to each other is a space when each protective layer 16 is a line, and the midpoint is a bisector of the width of the space in the cross-sectional view of FIG. That is, the midpoint is a point on a line segment that is equidistant from the end of each protective layer 16 facing the space between the two protective layers 16 in the plan view of FIG. The center position A is the center of the alignment position of the via hole 17a and means the position of a point on a plane parallel to the substrate surface, and is a position represented by two-dimensional coordinates on the plane.

  The plastic substrate 10 of the present invention includes polymethylene methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone, polyolefin, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, polyethersulfone, triacetylcellulose, polyvinyl Fluoride film, ethylene-tetrafluoroethylene, copolymer resin, weather resistant polyethylene terephthalate, weather resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, transparent polyimide, fluorine resin, cyclic polyolefin resin, etc. are used. However, the present invention is not limited to these. These can be used alone or as a composite substrate in which two or more kinds are laminated. A substrate having a resin layer such as a color filter on a glass or plastic substrate can also be used.

For the gate electrode 11, source electrode 13, drain electrode 14, pixel electrode 18, and capacitor electrode 19 of the present invention, a low resistance metal material such as Au, Ag, Cu, Cr, Al, Mg, Li, or an oxide material is suitable. Used for. Specifically, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), cadmium oxide (CdO), indium cadmium oxide (CdIn ₂ O ₄ ), cadmium tin oxide (Cd ₂ SnO) ₄ ), zinc tin oxide (Zn ₂ SnO ₄ ), indium zinc oxide (InZnO), and the like. Further, an oxide material doped with impurities is also preferable. For example, indium oxide doped with molybdenum or titanium, tin oxide doped with antimony or fluorine, zinc oxide doped with indium, aluminum, or gallium. Among them, indium tin oxide (ITO) in which tin is doped in indium oxide exhibits a particularly low resistivity. An organic conductive material such as PEDOT (polyethylenedioxythiophene) is also suitable, and is preferably used in the case of a single substance or a plurality of laminated layers with a conductive oxide material. The gate electrode 11, the source electrode 13 and the drain electrode 14, the pixel electrode 18, and the capacitor electrode 19 may all be made of the same material or different materials. However, in order to reduce the number of steps, it is desirable to use the same material for the source electrode 13 and the drain electrode 14. These electrodes are formed by vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD, photo CVD, hot wire CVD, or the like. It can also be formed by applying the above conductive material in ink or paste form by screen printing, flexographic printing, ink jet method or the like and baking. The present invention is not limited to these.

The gate insulating film 12 of the present invention includes an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia oxide, titanium oxide, or PMMA (polyethylene oxide). Examples thereof include polyacrylates such as methyl methacrylate), PVA (polyvinyl alcohol), and PVP (polyvinylphenol), but the present invention is not limited thereto. In order to suppress gate leakage current, a preferable resistivity of the insulating material is 10 ¹¹ Ωcm or more, more preferably 10 ¹⁴ Ωcm or more.

  Examples of the semiconductor layer 15 used in the present invention include an oxide semiconductor and an organic semiconductor. As an oxide semiconductor material, an oxide containing one or more elements selected from zinc, indium, tin, tungsten, magnesium, gallium, that is, zinc oxide, indium oxide, indium zinc oxide, tin oxide, tungsten oxide, zinc oxide Known materials such as gallium indium can be used. Organic semiconductor materials include high molecular organic semiconductor materials such as polythiophene, polyallylamine, fluorenebithiophene copolymers, and derivatives thereof, and pentacene, tetracene, copper phthalocyanine, perylene, 6,13-bis (triisopropylsilyl) Low molecular organic semiconductor materials such as ethynyl) pentacene (TIPS-pentacene), and derivatives thereof, and precursors that are converted into organic semiconductors by heat treatment or the like can be used as the semiconductor material ink. Carbon compounds such as carbon nanotubes or fullerenes, semiconductor nanoparticle dispersions, and the like can also be used as the material for the semiconductor layer. When a semiconductor material ink is used, examples of the solvent include toluene, xylene, indane, tetralin, propylene glycol methyl ether acetate, and the like, but are not limited thereto. A method of applying the above conductive material in ink or paste form by screen printing, flexographic printing, ink jet method or the like and drying is preferably used.

  The material used as the protective layer 16 used in the present invention is preferably a polymer solution such as polyvinylphenol, polymethyl methacrylate, polyimide, polyvinyl alcohol, epoxy resin or fluororesin, or a solution in which particles such as alumina or silica gel are dispersed. Used for. As a method for forming the protective layer, a method of directly forming a pattern using a wet method such as screen printing, flexographic printing, or an ink jet method is preferably used.

The structure of the thin film transistor formed by using the pattern forming method of the present invention is not particularly limited, and may be either a top gate type or a bottom gate type structure.
As a difference in structure other than the arrangement of the gate electrode, there are a bottom contact type and a top contact type in which the positions of the semiconductor layers are different, but the present invention is not limited to these.

  FIG. 3 shows a cross-sectional structure of a thin film transistor array 1 including a bottom gate bottom contact type flexible thin film transistor array according to the first embodiment, and a manufacturing method will be described. The thin film transistor array 1 has an element size of 300 μm × 300 μm, and there are 240 × 320 elements.

  A polyethylene naphthalate (PEN) film was used as the plastic substrate 10. After depositing aluminum on the PEN film to a thickness of 100 nm by sputtering, photolithography and etching were performed using a positive resist, and then the resist was removed to form the gate electrode 11 and the capacitor electrode 19.

  Subsequently, polyimide was applied as a gate insulating material by a die coater and dried at 180 ° C. for 1 hour to obtain a gate insulating film 12. Next, gold was deposited to a thickness of 50 nm by an evaporation method, photolithography and etching were performed using a positive resist, and then the resist was removed to form the source electrode 13 and the drain electrode 14.

  As a semiconductor layer forming material, a mixed solution of tetralin and 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene) was used. The flexographic printing method was used for forming the semiconductor layer. For flexographic printing, a photosensitive resin flexographic plate and a 150-wire anilox roll were used to form a stripe-shaped semiconductor layer having a width of 100 μm. After printing, the semiconductor layer 15 was formed by drying at 100 ° C. for 60 minutes.

  Subsequently, the protective layer 16 was formed. A fluorine resin was used as a protective layer forming material. Flexographic printing was used for forming the protective layer. A photosensitive resin flexographic plate was used as the flexographic plate, and a 150-wire anilox roll was used. A stripe-shaped protective layer 16 having a line width of 150 μm was printed using a stripe-shaped flexographic plate so as to cover the semiconductor layer 15. The variation in the line width of the protective layer 16 was ± 10 μm. Thereafter, the protective layer 16 was formed by drying at 100 ° C. for 90 minutes.

  Subsequently, an interlayer insulating film 17 was formed. Epoxy resin was used as an interlayer insulating film forming material. It formed using screen printing, and it was made to dry at 90 degreeC for 1 hour, and was set as the interlayer insulation film 17. The interlayer insulating film 17 is formed so as to cover the entire array, and has a 50 μm square via hole 17 a for conducting the pixel electrode 18 and the drain electrode 14. Since the center position A of the via hole 17a is on the straight line C parallel to the stripe passing through the midpoint between the stripes of the protective layer 16, the via hole can be formed even in the portion where the stripe line width of the protective layer 16 is thicker than the design value. The conduction of the part was not hindered.

  Thereafter, the pixel electrode 18 was formed. Silver paste was used as the pixel electrode material. The pixel electrode 18 was formed by screen printing, and the silver paste was completely filled in the via hole 17a. After the pattern formation, the pixel electrode 18 was obtained by drying at 90 ° C. for 1 hour.

  Thereafter, the display according to this example was driven with the electrophoretic medium 20 sandwiched between the counter electrode. The line thickness (+10 μm) due to the line width variation of the protective layer 16, the misalignment of the protective layer 16 (10 μm to the left), and the misalignment of the interlayer insulating film 17 (10 μm to the left) occurred. Since 17a was at the center between the stripes of the protective layer 16, electrical conduction between the pixel electrode 18 and the drain electrode 14 could be achieved, and good image display could be performed without point defects.

Comparative Example 1

  The manufacturing method of the bottom gate bottom contact type flexible thin-film transistor array which takes the form shown in FIG. 4, FIG. 5 is shown. This transistor array has one element size of 300 μm × 300 μm, and there are 240 × 320 elements.

  Using a polyethylene naphthalate (PEN) film as the plastic substrate 10, the gate electrode 11, the capacitor electrode 19, the gate insulating film 12, the source electrode 13, the drain electrode 14, the semiconductor layer 15, and the protective layer 16 are formed as in the first embodiment. did.

  For the formation of the interlayer insulating film 17, the same material and printing method as in Example 1 were used. However, the center position A of the 50 μm square via hole 17a for conducting the pixel electrode 18 and the drain electrode 14 is shifted to the left by 50 μm from the straight line C parallel to the stripe passing through the midpoint between the stripes of the protective layer 16. It was designed to be. As a result, the margin of the protective layer 16 and the end portion of the via hole 17a of the interlayer insulating film 17 is 50 μm smaller than that of the via hole 17a centered on the straight line C. As a result, the distance between the end portion of the protective layer 16 and the end portion of the via hole 17a of the interlayer insulating film 17 is partially reduced due to line thickening due to line width variation of the protective layer 16 and misalignment of the protective layer 16 and the interlayer insulating film 17. The protective layer 16 has been formed to protrude to the via hole portion.

  As in the first embodiment, when the pixel electrode 18 is formed and the display according to the present embodiment is driven with the electrophoretic medium 20 sandwiched between the counter electrode and the counter electrode, the protective layer 16 protrudes to the via hole portion of the interlayer insulating film 17. In the portion formed in this manner, the conduction between the pixel electrode 18 and the drain electrode 14 is hindered, the number of point defects increases, and good display cannot be performed.

  The flexible thin film transistor of this invention can be utilized as switching elements, such as flexible electronic paper and a flexible organic EL display. In particular, by forming the center position of the via hole in the interlayer insulating film on a straight line passing through the midpoint of the stripe-shaped protective interlayer and parallel to the stripe, the yield and throughput in the manufacturing process can be improved. In consideration of misalignment and the like, if the deviation between the via hole center position and the position of the stripe middle point is within 40 μm, a protective layer can be formed without inhibiting conduction between the drain electrode and the interlayer insulating film, Throughput can be improved. This makes it possible to manufacture a flexible thin film transistor applicable to a wide range, such as a flexible display, an IC card, and an IC tag, at low cost and with high quality.

DESCRIPTION OF SYMBOLS 10 ... Plastic substrate 11 ... Gate electrode 12 ... Gate insulating film 13 ... Source electrode 14 ... Drain electrode 15 ... Semiconductor layer 16 ... Protective layer 17 ... Interlayer insulating film 17a ... via hole 18 ... pixel electrode 19 ... capacitor electrode 20 ... electrophoresis medium

Claims (10)

A thin film transistor array including at least an insulating substrate, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, a semiconductor layer, a protective layer covering the semiconductor layer, an interlayer insulating film, and a pixel electrode. There,
The protective layer has a stripe shape parallel to the source wiring, and the central positions of the via holes of the interlayer insulating film provided for conducting the drain electrode and the pixel electrode are adjacent to each other in the stripe shape. A thin film transistor array, wherein the thin film transistor array is located on a straight line parallel to a stripe passing through a middle point between layers.   2. The thin film transistor array according to claim 1, wherein a deviation between a center position of the via hole and a position on a straight line parallel to the stripe passing through the midpoint is 40 μm or less.   2. The thin film transistor array according to claim 1, wherein the semiconductor layer is an organic semiconductor or an oxide semiconductor.   2. The thin film transistor array according to claim 1, wherein the semiconductor layer is formed by one or more of a flexographic printing method, an ink jet printing method, and a screen printing method.   The thin film transistor array according to claim 1, wherein the protective layer is made of an organic insulating material.   The thin film transistor array according to claim 1, wherein the protective layer is formed by one or more of a flexographic printing method, an inkjet printing method, and a screen printing method.   2. The thin film transistor array according to claim 1, wherein the interlayer insulating film is formed by one or more of a flexographic printing method, an ink jet printing method, a screen printing method, and a gravure offset printing method.   2. The thin film transistor array according to claim 1, wherein the insulating substrate is a plastic substrate.   An image display device comprising the thin film transistor array according to claim 1 and an image display medium.   The image display device according to claim 9, wherein the image display medium is an electrophoretic type.

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