TWI593007B - Semiconductor device and method for fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to an electronic component and a method of fabricating the same, and more particularly to a semiconductor component and a method of fabricating the same.

With the rapid development of technology, in order to reduce the cost, simplify the process steps and save the wafer area, it has become a trend to integrate the elements of the memory cell array and the peripheral circuit area on the same wafer. However, there is a considerable step height in the Boundary region between the memory cell array region and the peripheral circuit region, which increases the complexity of subsequent processes.

1 is a schematic cross-sectional view of a conventional semiconductor device. Referring to FIG. 1, for example, in order to reduce the height of the stacked layer 12 on the surface of the substrate 10, a conventional semiconductor device employs a method of removing a portion of the substrate 10 of the memory cell array region 110 to embed the stacked layer 12. However, this approach results in a substantial step height for the boundary region 130 between the memory cell array region 110 and the peripheral circuit region 120. In order to solve the problem of the step height, it is necessary to reserve a considerable distance (about 3 μm) between the memory cell array region 110 and the peripheral circuit region 120 as the boundary region 130, and After a series of lithography such as lithography, etching, thin film deposition, and chemical mechanical polishing (CMP), a large and deep trench 18 is formed in the boundary region 130, and the tantalum nitride layer 14 is filled during the process. With the yttrium oxide layer 16. However, since the etching rate of the tantalum nitride layer 14 and the tantalum oxide layer 16 is different, after removing the excess tantalum nitride layer 14 and the tantalum oxide layer 16 by the wet etching process, the two layers of the tantalum nitride layer 14 are removed. The recess 20 is easily formed on the side and the top surface of the tantalum oxide layer 16 is also slightly higher than the top surface of the memory cell array region 110 and the peripheral circuit region 120. Due to the complicated cost of the boundary flattening process, the height difference of the conventional processing method increases the difficulty of subsequent processes and reduces the reliability of the product.

Therefore, how to simplify the boundary processing steps between the memory cell array region and the peripheral circuit region, and achieve the minimum step height difference between regions, reduce the complexity of subsequent processes, increase the wafer use area, and at the same time reduce the cost, will become quite important a subject.

The present invention provides a semiconductor device and a method of fabricating the same that can improve a step height of a boundary region between a memory cell array region and a peripheral circuit region.

The present invention provides a semiconductor device and a method of fabricating the same that can simplify the process and simultaneously increase the wafer use area.

The present invention provides a method of fabricating a semiconductor device, the method comprising providing a substrate. The substrate includes a first zone, a second zone, and a third zone. The top surface of the substrate of the first zone is lower than the top surface of the substrate of the second zone. The third zone is disposed in the first zone and the second zone between. The base of the third zone has a first step height. A stacked layer is conformally formed on the substrate. The stacked layers in the third zone have a second step height. A layer of flowing material is formed on the stacked layers. A first etching process is performed on the flowing material layer to remove a portion of the flowing material layer. The second etching process is performed on the stacked layers of the second region and the third region by using a layer of flowing material in the first region as a mask to expose the top surface of the substrate of the second region. Remove the layer of flowing material.

In an embodiment of the invention, the material of the flowing material layer comprises an organic material, an inorganic material or an organic-inorganic composite material.

In an embodiment of the invention, the material of the flowing material layer comprises an organic material. The above organic materials include photoresist (PR), organic underlayer (ODL), bottom anti-reflective coating (BARC), spin-on glass (SOG), or a combination thereof.

In an embodiment of the invention, the stacked layer includes a plurality of dielectric layers and a plurality of conductor layers. The dielectric layer and the conductor layer are stacked on each other. The etch rate of the dielectric layer to the second etch process is equal to the etch rate of the conductor layer.

In an embodiment of the invention, after the first etching process is performed on the flowing material layer, the stacked layers of the second region are exposed.

In an embodiment of the invention, after the first etching process is performed on the flowing material layer, the thickness of the flowing material layer remaining in the first region is greater than the thickness of the flowing material layer remaining in the second region, and is greater than the second Step height.

In an embodiment of the invention, after the flowing material layer is subjected to the first etching process, the thickness of the flowing material layer remaining in the first region is greater than the thickness of the flowing material layer remaining in the second region, and is smaller than the second Step height.

The present invention provides a semiconductor device including a substrate and a stacked layer. The substrate includes a first zone, a second zone, and a third zone. The third zone is disposed between the first zone and the second zone. Since the top surface of the substrate of the first region is lower than the top surface of the substrate of the second region, the substrate of the third region has a first step height. The stacked layers are disposed on the substrates of the first and third regions. The top surface of the stacked layers in the first and third regions is substantially coplanar with the top surface of the substrate in the second region.

In an embodiment of the invention, the top surface of the stacked layer in the third zone is substantially equal to or lower than the top surface of the substrate in the second zone.

In an embodiment of the invention, the third region has a width of 40 nm to 140 nm.

Based on the above, the embodiment of the present invention covers the stacked layer in the first region and partially covers the stacked layer in the third region by using the flowing material layer such that the top surface of the flowing material layer in the first region and the third region is approximately equal to the second layer. The top surface of the stacked layers in the zone. Then, the stacked material layers of the second region and the third region are etched by using the flowing material layer in the first region as a mask to expose the top surface of the substrate of the second region. It causes the top surface of the stacked layers of the first and third regions to be approximately equal to the top surface of the substrate of the second region. In this way, the step height of the boundary region (for example, the third region) between the memory cell array region (for example, the first region) and the peripheral circuit region (for example, the second region) can be improved, thereby simplifying the subsequent process. The complexity, which in turn reduces process costs.

The above described features and advantages of the invention will be apparent from the following description.

10, 100‧‧‧ base

101a‧‧‧ dielectric layer

101b‧‧‧ conductor layer

12, 102, 102a, 102b‧‧‧ stacked layers

14‧‧‧矽 nitride layer

16‧‧‧Oxide layer

18‧‧‧ditch

20, 105‧‧‧ dent

103a, 103b, 103c, 103d, 103e, 103f‧‧‧ material layers

104, 104a, 104b, 104c, 104d‧‧‧ flowing material layer

106‧‧‧Charge storage layer

108‧‧‧Conductor column

110‧‧‧First Zone, Memory Cell Array Area

120‧‧‧Second area, peripheral circuit area

130‧‧‧ Third District, Border Area

140‧‧‧ditches, holes

Section 200‧‧‧

H1, H2, H3‧‧‧ step height

T, T1~T7, t1, t2‧‧‧ thickness

1 is a schematic cross-sectional view of a conventional semiconductor device.

2A-2G are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

Figure 3 is an enlarged schematic view of a portion of the stacked layers of Figure 2A.

4 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

Figure 5 is a cross-sectional view showing a semiconductor device in accordance with a second embodiment of the present invention.

Figure 6 is a cross-sectional view showing a semiconductor device in accordance with a third embodiment of the present invention.

Figure 7 is a cross-sectional view showing a semiconductor device in accordance with a fourth embodiment of the present invention.

Figure 8 is a cross-sectional view showing a semiconductor device in which a flow material layer is subjected to a first etching process in another embodiment of the present invention.

Figure 9 is a cross-sectional view showing a semiconductor device in which a flow material layer is subjected to a first etching process in still another embodiment of the present invention.

2A-2G are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

Referring to FIG. 2A, first, a substrate 100 is provided. The substrate 100 includes a first region 110, a second region 120, and a third region 130. The third zone 130 is located between the first zone 110 and the second zone 120. The top surface of the substrate 100 of the first region 110 is lower than the top surface of the substrate 100 of the second region 120, and the substrate 100 of the third region 130 has a first step height H1. In an embodiment, the height of the first step height H1 is 40 nm to 140 nm. In one embodiment, the first region 110 is a memory cell array region; the second region 120 is a peripheral circuit region; and the third region 130 is a boundary region between the memory cell array region and the peripheral circuit region. In one embodiment, the third region 130 has a width of 40 nm to 140 nm and a width that is much smaller than a distance of 3 μm reserved in the prior art.

In an embodiment, the substrate 100 may be subjected to a first patterning process on the substrate material by using a lithography and etching process to remove portions of the substrate material corresponding to the first region 110 and the third region 130. In another embodiment, the substrate 100 may be formed with a layer of germanium-containing material (not shown) on the substrate material corresponding to the second region 120 such that the top surface of the germanium-containing material layer of the second region 120 is higher than the first layer. The top surface of the base material of zone 110. The substrate material is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

Thereafter, a stacked layer 102 is conformally formed on the substrate 100 such that the top surface of the stacked layer 102 in the first region 110 is substantially coplanar with the top surface of the substrate 100 of the second region 120. In other words, the thickness of the stacked layer 102 is approximately equal to the first step height H1. Since the stacked layer 102 conformally covers the substrate 100, the top surface of the stacked layer 102 in the first region 110 is lower than the top surface of the stacked layer 102 in the second region 120, and in the third region 130 The stacked layer 102 has a second step height H2. In an embodiment The stacked layer 102 may be, for example, a single layer or a multilayer composite layer. When the stacked layer 102 is, for example, a multi-layered composite layer, an enlarged schematic view of the partially stacked layer 200 is shown in FIG. The stacked layer 102 includes a plurality of dielectric layers 101a and a plurality of conductor layers 101b. The dielectric layer 101a and the conductor layer 101b are stacked on each other. In an embodiment, the number of conductor layers 101b may include 8 layers, 16 layers, 32 layers, or more. Similarly, the dielectric layer 101a is disposed between the adjacent two conductor layers 101b. Therefore, the dielectric layer 101a also includes 8 layers, 16 layers, 32 layers or more. In an embodiment, the material of the dielectric layer 101a may include ruthenium oxide, tantalum nitride, or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. The material of the conductor layer 101b may include doped polysilicon, undoped polysilicon, or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. In an embodiment, the height of the second step height H2 is 40 nm to 140 nm.

Referring to FIG. 2B, a flow material layer 104 is formed on the stacked layer 102 of the first region 110, the second region 120, and the third region 130. In an embodiment, the material of the flowing material layer 104 includes an organic material, an inorganic material, or an organic-inorganic composite material. When the material of the flowing material layer 104 is, for example, an organic material, the organic material includes Photoresist (PR), Organic UnDer Layer (ODL), and Bottom Anti-Reflection Coating (BARC). ), Spin-On Glass (SOG) or a combination thereof. The method of forming the flowing material layer 104 is, for example, a spin coating method, a high density plasma method (HDPCVD), or an enhanced high aspect ratio process (eHARP). The flow material layer 104 can be a single layer structure, a two layer structure, or a multilayer structure.

As shown in FIG. 4, in the first embodiment of the present invention, the flowing material layer 104 For example, it is a single layer structure. The material of the flowing material layer 104 may include: photoresist (PR), organic underlayer (ODL), bottom anti-reflective coating (BARC) or spin-on glass (SOG). The material of the flowing material layer 104 of the embodiment of the present invention is not limited thereto as long as the flowing material layer 104 can cover the top surface of the stacked layer 102 and the thickness T1 of the flowing material layer 104 is greater than the second step height H2.

Referring to Figures 5 through 7, the flowing material layer 104 can be, for example, a two-layer structure. Referring to FIG. 5, in the second embodiment of the present invention, the top surface of the flowing material layer 104 is a flat surface, and the flowing material layer 104 sequentially includes a material layer 103a and a material layer 103b. The material layer 103a and the material layer 103b may be, for example, the same material. The material layer 103b has a flat surface. For example, both the material layer 103a and the material layer 103b are, for example, organic underlayer materials (ODL). However, the thickness T2 of the sum of the material layer 103a and the material layer 103b may be larger than the second step height H2, and the material of the material layer 103a and the material layer 103b of the embodiment of the present invention is not limited thereto.

On the other hand, referring to FIG. 6, in the third embodiment of the present invention, the top surface of the flowing material layer 104 is a flat surface, and the flowing material layer 104 sequentially includes a material layer 103c and a material layer 103d. The material layer 103c and the material layer 103d are, for example, different materials. For example, material layer 103c can be, for example, an organic underlayer material (ODL), while material layer 103d can be, for example, a photoresist (PR). The material layer 103d has a flat surface. However, the thickness T3 of the sum of the material layer 103c and the material layer 103d may be larger than the second step height H2, and the materials of the material layers 103c and 103d of the embodiment of the present invention are not limited thereto.

Further, as shown in FIG. 7, in the fourth embodiment of the present invention, the flowing material Layer 104 may be, for example, a two-layer or multi-layer structure, but the top surface of flowing material layer 104 is not flat, but its step height H3 is less than step height H2. For example, a single or multiple layer of material layer 103e is conformally formed on the stacked layer 102. Next, a material layer 103f is formed on the single or multiple layer of material layer 103e. The surface of the material layer 103f is not flat and has a step height H3. The material layer 103e may be, for example, tantalum nitride (SiN), ruthenium oxide, ruthenium oxynitride, a carbon layer or tantalum carbide, and the formation method thereof may be formed by chemical vapor deposition. The material layer 103f may be, for example, an organic underlayer material (ODL), and the formation method thereof may be formed by a spin coating method. The material layer 103e and the material layer of the embodiment of the present invention may be used as long as the material layer 103e and the material layer 103f can cover the top surface of the stacked layer 102, and the thickness T4 of the sum of the material layer 103e and the material layer 103f is greater than the second step height H2. The material of 103f is not limited to this.

2C, 8 and 9, with the top surface of the stacked layer 102 as an etch stop layer, a first etching process is performed to remove a portion of the flowing material layer 104, leaving the flowing material layers 104a, 104b or 104c. The first etch process can be, for example, an Etch Back process. In an embodiment, referring to FIG. 2C, after the first etching process is performed, the remaining flowing material layer 104a covers the first region 110 and partially covers the stacked layer 102 in the third region 130, and exposes the second region 120. The top surface of the stacked layer 102 with the third region 130. Further, the thickness T5 of the flowing material layer 104a on the first region 110 is substantially equal to the second step height H2. That is, the top surface of the flowing material layer 104a is substantially equal to the top surface of the stacked layer 102 of the second region 120 and the third region 130.

In still another embodiment, referring to FIG. 8, after the first etching process is performed, the remaining flowing material layer 104b covers the first region 110, the second region 120, and the first Stacked layers 102 in three zones 130. The thickness T6 of the flowing material layer 104b on the first zone 110 is greater than the thickness t1 of the flowing material layer 104b on the second zone 120, but the thickness T6 is substantially greater than the second step height H2.

In another embodiment, referring to FIG. 9, after the first etching process is performed, the remaining flowing material layer 104c covers the stacked layer 102 in the first region 110, the second region 120, and the third region 130. The thickness T7 of the flowing material layer 104c on the first region 110 is greater than the thickness t2 of the flowing material layer 104c on the second region 120, but the thickness T7 is smaller than the second step height H2.

Referring to FIG. 2D, a second etching process is performed to expose the top surface of the substrate 100 of the second region 120. In an embodiment, the second etch process can be, for example, an anisotropic etch process. By the choice of etchant, an etchant having a low etch rate or a very low etch rate for the flowing material layer 104a/104b/104c, but having a high etch rate for the stacked layer 102a, may be directly used as the flowing material layer 104a/104b/ 104c is a mask, self-aligning (Self Align) does not cover the second region 120 of the flowing material layer 104a or the flowing material layer 104b/104c and the stacked layer 102 of the third region 130 is partially removed, without The shadow process defines the area of the etch. Therefore, the problem of misalignment caused by the lithography process can be avoided.

After the second etching process is performed, the top surface of the stacked layer 102a of the third region 130 is exposed, and the top surface of the stacked layer 102a of the third region 130 is approximately equal to the top surface of the substrate 100 of the second region 120. In one embodiment, a portion of the flowing material layer 104d remains on the substrate 100 of the first region 110 after the second etching process. In another embodiment, after performing the second etching process, the substrate in the first region 110 The flow material layer 104a on 100 is completely removed.

In addition, referring back to FIG. 2C and FIG. 3, in one embodiment, the etching rate of the second etching process to the dielectric layer 101a is approximately equal to the etching rate of the conductor layer 101b. As such, after the second etching process is performed, the top surface of the stacked layer 102a of the third region 130 may be a substantially smooth surface rather than an uneven surface. However, it is also possible to cause partial depression in the stacked layer 102a of the third region 130 during the second etching process, but it is acceptable.

In addition, the etching condition (Etch Recipe) of the second etching process may be adjusted according to the thickness T of the flowing material layer 104 and the second step height H2. For example, after forming the flowing material layer 104a on the stacked layer 102, as shown in FIG. 2C, when the thickness T5 of the flowing material layer 104a on the first region 110 is equal to the second step height H2, or as shown in FIG. When the thickness T6 of the flowing material layer 104b on the first region 110 is greater than the second step height H2, the etching rate of the second etching process to the flowing material layer 104a or 104b may be lower than or equal to the etching rate of the stacked layer 102. However, as shown in FIG. 9, when the thickness T7 of the flowing material layer 104c on the first region 110 is smaller than the second step height H2, the minimum etching rate ratio of the second etching process to the flowing material layer 104c and the stacked layer 102 is (T7-t2): H2. In other words, the etch rate of the selected etchant to the flowing material layer 104c must be much lower than the etch rate to the stacked layer 102 during the second etch process. As such, the thickness of the flowing material layer 104c on the first region 110 is sufficient to protect the stacked layer 102 underneath from damage during the second etching process.

Please refer to Figures 2D and 2E, using the Dry Strip process or The Wet Strip process removes the flow material layer 104d to expose the top surface of the stacked layer 102a in the first region 110. After removing the flowing material layer 104d, the top surface of the stacked layer 102a of the first region 110 and the third region 130 is substantially equal to the top surface of the substrate 100 of the second region 120. In the third region 130 having the second step height H2, the top surface of the stacked layer 102a is also a smooth surface, which does not cause the unevenness of the top surface in the prior art. In this way, the manufacturing method of the semiconductor device of the embodiment of the invention can simplify the complexity of the subsequent process, thereby improving the reliability of the product.

Referring to FIG. 2F, after removing the flowing material layer 104d of the first region 110, a second patterning process is performed on the stacked layer 102a of the first region 110, and the stacked layer 102a of the portion of the first region 110 is removed. A plurality of trenches or holes 140 are formed in the stacked layer 102b of a zone 110. Since the second patterning process may partially remove the stacked layer 102b of the third region 130, the top surface of the stacked layer 102b in the third region 130 is substantially equal to or lower than the top surface of the substrate 100 in the second region 120. . However, for product reliability of the final component, a portion of the recess 105 of the stacked layer 102b of the third region 130 is acceptable. In an embodiment, the depth of the recess 105 is less than 10 nm. In another embodiment, the depth of the recess 105 is between 1 nm and 10 nm.

Referring to FIG. 2G, the charge storage layer 106 and the corresponding conductor post 108 are sequentially formed in each trench or hole 140. The charge storage layer 106 is disposed between the conductor post 108 and the stacked layer 102b. Specifically, the charge storage layer 106 is conformally formed in each of the trenches 140. Next, a conductive material layer (not shown) is formed on the stacked layer 102b, wherein the conductive material layer is filled in the trench 140. Then, a planarization process is performed to remove a portion of the conductor material layer to expose the top surface of the stacked layer 102b. In an embodiment, The charge storage layer 106 may be, for example, a composite layer composed of an Oxide-Nitride-Oxide (ONO) layer. The composite layer may be three or more layers, and the present invention is not limited thereto. The formation method may be a chemical vapor deposition method, a thermal oxidation method, or the like. The material of the conductor post 108 may be, for example, doped polysilicon, non-doped polysilicon or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition.

Referring back to FIG. 2E, the semiconductor device of the embodiment of the present invention includes a substrate 100 and a stacked layer 102a. The substrate 100 includes a first region 110, a second region 120, and a third region 130. The third zone 130 is located between the first zone 110 and the second zone 120. The top surface of the substrate 100 of the first region 110 is lower than the top surface of the substrate 100 of the second region 120, and the substrate 100 of the third region 130 has a first step height H1. The stacked layer 102a is disposed on the substrate 100 of the first region 110 and the third region 130. The stacked layer 102a includes a plurality of dielectric layers 101a and a plurality of conductor layers 101b. The dielectric layer 101a and the conductor layer 101b are stacked on each other. The top surface of the stacked layer 102a in the first region 110 and the third region 130 is substantially coplanar with the top surface of the substrate 100 of the second region 120.

In summary, the embodiment of the present invention uses a stacked layer of flowing material layer in a stacked layer covering a memory cell array region (for example, the first region) as a mask to etch a peripheral circuit region (for example, a second region). And a stacked layer with a boundary area (for example, the third area). Thereby, the top surface of the stacked layer in the memory cell array region (for example, the first region) and the boundary region (for example, the third region) can be made approximately equal to the top surface of the substrate in the second region. In this way, the boundary area between the memory cell array region (for example, the first region) and the peripheral circuit region (for example, the second region) can be reduced (for example, the third region). The height of the ladder, thereby simplifying the complexity of subsequent processes.

In addition, the embodiment of the present invention may further adjust the etching condition by using the thickness of the flowing material layer and the second step height, so that after performing the second etching process, the memory cell array region (for example, the first region) and the boundary region (for example, The top surface of the stacked layer in the third region) is equal to the top surface of the substrate of the peripheral circuit region (for example, the second region), and the stacked layers in the memory cell array region (for example, the first region) are not damaged. The top surface of the stacked layer in the memory cell array region (eg, the first region) and the boundary region (eg, the third region) is substantially coplanar with the top surface of the substrate in the peripheral circuit region (eg, the second region) Therefore, the embodiment of the present invention can omit many subsequent process steps, and achieve the effect of reducing the process cost (about 3% of the process cost). Moreover, the embodiment of the present invention can also reduce the boundary area between the memory cell array region and the peripheral circuit region to increase the wafer use area and further reduce the process cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102a‧‧‧Stacking

110‧‧‧First District

120‧‧‧Second District

130‧‧‧ Third District

Claims (10)

A method of fabricating a semiconductor device, comprising: providing a substrate, the substrate comprising a first region, a second region, and a third region, wherein a top surface of the substrate of the first region is lower than the second region a top surface of the substrate, the third region being located between the first region and the second region, the substrate of the third region having a first step height; forming a stacked layer conformally on the substrate The stacked layer in the third region has a second step height; forming a flowing material layer on the stacked layer; performing a first etching process on the flowing material layer to remove a portion of the flowing material layer; The layer of flowing material in the first region is a mask, and a second etching process is performed on the stacked layer of the second region and the third region to expose a top surface of the substrate of the second region; and completely The layer of flowing material is removed. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the flowing material layer comprises an organic material, an inorganic material or an organic-inorganic composite material. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the flowing material layer comprises an organic material including a photoresist (PR), an organic underlayer (ODL), and a bottom anti-reflective coating. (BARC), spin on glass (SOG) or a combination thereof. The method of fabricating a semiconductor device according to claim 1, wherein the stacked layer comprises a plurality of dielectric layers and a plurality of conductor layers, and the dielectric layers and the conductor layers are stacked on each other, wherein the second etching The etch rate of the dielectric layers is equal to the etch rate of the conductor layers. The method of manufacturing a semiconductor device according to claim 1, wherein the stacked layer of the second region is exposed after the first etching process is performed on the flowing material layer. The method of manufacturing a semiconductor device according to claim 1, wherein after the first etching process is performed on the flowing material layer, a thickness of the flowing material layer remaining in the first region is greater than remaining in the second region. The thickness of the layer of flowing material is greater than the second step height. The method of manufacturing a semiconductor device according to claim 1, wherein after the first etching process is performed on the flowing material layer, a thickness of the flowing material layer in the first region is greater than a thickness remaining in the second region. The thickness of the layer of flowing material is less than the second step height. A semiconductor device comprising: a substrate comprising a first region, a second region, and a third region, wherein the third region is disposed between the first region and the second region, the first region The top surface of the substrate is lower than the top surface of the substrate of the second region, the substrate of the third region has a first step height, wherein the first region is a memory cell array region, and the second region is a peripheral circuit region And a stacked layer disposed on the substrate of the first region and the third region, wherein The top surface of the stacked layer in the first zone and the third zone is substantially coplanar with the top surface of the substrate in the second zone. The semiconductor device of claim 8, wherein a top surface of the stacked layer in the third region is substantially equal to or lower than a top surface of the substrate in the second region. The semiconductor device according to claim 8, wherein the third region has a width of 40 nm to 140 nm.