TWI590732B - Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies - Google Patents
Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies Download PDFInfo
- Publication number
- TWI590732B TWI590732B TW100141850A TW100141850A TWI590732B TW I590732 B TWI590732 B TW I590732B TW 100141850 A TW100141850 A TW 100141850A TW 100141850 A TW100141850 A TW 100141850A TW I590732 B TWI590732 B TW I590732B
- Authority
- TW
- Taiwan
- Prior art keywords
- assembly
- perforation
- sub
- conductive
- pad
- Prior art date
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明係概括有關印刷電路板及其製造方法,且更特別有關包含疊設有封閉及內部微穿孔的電路層之印刷電路板及其製造方法。SUMMARY OF THE INVENTION The present invention is generally directed to printed circuit boards and methods of fabricating the same, and more particularly to printed circuit boards including circuit layers stacked with closed and internal microperforations, and methods of fabricating the same.
大部份電子系統係包括具有高密度電子互連件之印刷電路板。一印刷電路板(PCB)可包括一或多個電路核心、基材、或載體。在用於具有一或多個電路載體的印刷電路板之一製作方案中,電子電路(譬如墊、電子互連件等)係被製作於一個別電路載體的相對側上以形成一對的電路層。電路板的這些電路層對可隨後被物理或電子性接合以形成印刷電路板,其中係藉由製作一黏劑(或一預浸物(prepreg)或一結合層(bond ply))、在一壓機中堆積電路層對及黏劑、固化所產生的電路板結構、鑽製通洞、然後以一銅材料鍍覆通洞以互連電路層對。Most electronic systems include printed circuit boards with high density electronic interconnects. A printed circuit board (PCB) can include one or more circuit cores, substrates, or carriers. In a fabrication of a printed circuit board having one or more circuit carriers, electronic circuits (such as pads, electronic interconnects, etc.) are fabricated on opposite sides of a separate circuit carrier to form a pair of circuits Floor. These pairs of circuit layers of the board can then be physically or electronically bonded to form a printed circuit board by making an adhesive (or a prepreg or a bond ply) in one In the press, the circuit layer is stacked with the adhesive, the circuit board structure produced by the curing, the through hole is drilled, and then the through hole is plated with a copper material to interconnect the circuit layer pairs.
利用固化製程以固化黏劑提供電路板結構的永久物理性結合。然而,黏劑一般在固化製程期間顯著地收縮。收縮且連同稍後的通洞鑽製及鍍覆製程係會造成結構內顯著的應力,導致電路層之間不可靠的互連或結合或是損害。因此,需要具有可補償此收縮並可提供電路層對之間的一較無應力且可靠的電子性互連之材料及相關聯製程。A curing process is used to cure the adhesive to provide a permanent physical bond to the board structure. However, the adhesive generally shrinks significantly during the curing process. Shrinkage, together with later through hole drilling and plating processes, can cause significant stresses within the structure, resulting in unreliable interconnections or bonds or damage between circuit layers. Accordingly, there is a need for materials and associated processes that can compensate for this shrinkage and that provide a less stress-free and reliable electronic interconnection between pairs of circuit layers.
此外,以銅材料鍍覆通洞(或穿孔)係需要難以快速迴轉實行之一額外、昂貴且耗時的製程順序。第1圖是一用於製造一具有經堆積穿孔的印刷電路板之順序性疊合製程的流程圖,其包括昂貴且耗時的順序性疊合及鍍覆步驟。因此,需要提供一可藉由降低關鍵製程的反覆因此降低製造時間與成本而被快速且容易地製作及/或確保互連件(或通洞或微穿孔)對準於印刷電路板上之印刷電路板及其製造方法。In addition, plating a via (or perforation) with a copper material requires an additional, expensive, and time consuming process sequence that is difficult to spin quickly. 1 is a flow diagram of a sequential stacking process for fabricating a printed circuit board having stacked vias that includes an expensive and time consuming sequential stacking and plating step. Accordingly, there is a need to provide a printed circuit that can be quickly and easily fabricated and/or ensure that interconnects (or vias or microvias) are aligned on a printed circuit board by reducing the reversal of critical processes, thereby reducing manufacturing time and cost. Board and its manufacturing method.
本發明的態樣係有關且針對使用封閉及內部微穿孔耦接次總成之系統及方法。本發明的一實施例係提供一製造一印刷電路之方法,其包括附接複數個金屬層載體以形成一在一第一表面上包括至少一銅箔墊之第一次總成,施加一包封材料至第一次總成的第一表面上,固化包封材料及第一次總成;施加一疊合黏劑至經固化的包封材料之一表面,形成至少一穿孔於疊合黏劑及經固化的包封材料中以曝露至少一銅箔墊,附接複數個金屬層載體以形成一第二次總成,及附接第一次總成與第二次總成。Aspects of the present invention are related to and directed to systems and methods for coupling sub-assemblies using closed and internal micro-perforations. An embodiment of the invention provides a method of fabricating a printed circuit comprising attaching a plurality of metal layer carriers to form a first assembly comprising at least one copper foil pad on a first surface, applying a package Sealing the material onto the first surface of the first assembly, curing the encapsulating material and the first assembly; applying a stack of adhesive to one surface of the cured encapsulant to form at least one perforation And curing the encapsulating material to expose at least one copper foil pad, attaching a plurality of metal layer carriers to form a second sub-assembly, and attaching the first sub-assembly to the second sub-assembly.
本發明的另一實施例係提供一製造一多層印刷電路板之方法,包括形成一第一次總成,其包括(a)附接至少一金屬層載體以形成一在一第一表面上包括至少一銅箔墊之第一次總成,(b)施加一包封材料至第一次總成的第一表面上,(c)固化包封材料及第一次總成,(d)形成至少一第一穿孔於經固化的包封材料中以曝露至少一銅箔墊,(e)形成一傳導圖案於經固化的包封材料之一表面上,該傳導圖案包括一被耦接到至少一第一穿孔之傳導墊,(f)施加一疊合黏劑到經固化的包封材料之表面,(g)形成至少一洞在鄰近於至少一第一穿孔之疊合黏劑中,(h)以一傳導材料充填至少一洞以形成至少一第二穿孔,重覆(a)至(e)以形成一第二次總成,附接第一次總成與第二次總成使得第一次總成的至少一第二穿孔大約對準於第二次總成的傳導墊。Another embodiment of the present invention provides a method of fabricating a multilayer printed circuit board comprising forming a first subassembly comprising (a) attaching at least one metal layer carrier to form a first surface a first assembly comprising at least one copper foil pad, (b) applying an encapsulating material to the first surface of the first assembly, (c) curing the encapsulating material and the first assembly, (d) Forming at least a first through hole in the cured encapsulant to expose at least one copper foil pad, (e) forming a conductive pattern on a surface of the cured encapsulant, the conductive pattern including a coupled At least one first perforated conductive pad, (f) applying a stack of adhesive to the surface of the cured encapsulating material, (g) forming at least one hole in the superimposed adhesive adjacent to the at least one first perforation, (h) filling at least one hole with a conductive material to form at least one second perforation, repeating (a) to (e) to form a second sub-assembly, attaching the first assembly and the second assembly The at least one second perforation of the first assembly is aligned approximately to the conductive pad of the second assembly.
本發明的又另一實施例係提供一用於耦接一多層印刷電路板的次總成之附接結構,該結構係包括一第一總成,該第一總成包括一第一金屬層載體,其包括一包括一第一擷取墊之第一封閉穿孔,其被定位於第一金屬層載體的一頂表面中,一第一疊合黏劑層,其被定位為沿著頂表面及第一擷取墊,及一第一穿孔,其大約充填有一傳導材料而被定位於第一疊合黏劑中,第一穿孔接觸於第一擷取墊,及一第二總成,該第二總成包括一第二金屬層載體,其包括一包括一第二擷取墊之第二封閉穿孔,其被定位於第二金屬層載體的一頂表面中,其中第一總成利用第一疊合黏劑層被附接到第二總成使得第一黏劑中的第一穿孔大約對準於第二封閉穿孔的第二擷取墊。Yet another embodiment of the present invention provides an attachment structure for coupling a sub-assembly of a multilayer printed circuit board, the structure including a first assembly, the first assembly including a first metal a layer carrier comprising a first closed via comprising a first pick-up pad positioned in a top surface of the first metal layer carrier, a first stack of adhesive layers positioned along the top a surface and a first pick-up pad, and a first through hole, which is filled with a conductive material and positioned in the first laminated adhesive, the first through hole is in contact with the first pick-up pad, and a second assembly is The second assembly includes a second metal layer carrier including a second closed via including a second pick-up pad positioned in a top surface of the second metal layer carrier, wherein the first assembly utilizes The first superposed adhesive layer is attached to the second assembly such that the first perforation in the first adhesive is approximately aligned with the second dip pad of the second closed perforation.
第1圖是一用於製造一具有經堆積穿孔的印刷電路板之順序性疊合製程的流程圖,其包括順序性疊合及鍍覆步驟;第2a至2f圖顯示根據本發明的一實施例之一利用被定位於包封及黏劑層中的內部穿孔附接次總成以形成一多層印刷電路板之製程;第2g圖是根據本發明的一實施例之第2a至2f圖的最終多層印刷電路板之橫剖視圖;第3圖是根據本發明的一實施例之一具有利用第2a至2f圖的製程所附接之三個次總成之多層印刷電路板的橫剖視圖;第4a至4j圖顯示根據本發明的一實施例之一利用被定位於一黏劑層中的內部微穿孔附接次總成以形成一多層印刷電路板之替代性製程;第5圖是根據第4a至4j圖製程之一包括由黏劑及傳導膏耦接形成一細穿孔的兩封閉穿孔之次總成至次總成附接的橫剖視分解圖;第6圖是根據本發明的一實施例之包括由黏劑及傳導膏耦接形成一穿孔之各次總成上的經堆積穿孔之另一次總成至次總成附接之橫剖視分解圖;第7圖是根據本發明的一實施例使用一位居具有放大表面積的兩經機械鑽製穿孔之間的傳導膏微穿孔之另一次總成至次總成附接之橫剖視分解圖。1 is a flow chart of a sequential stacking process for fabricating a printed circuit board having stacked vias, including sequential stacking and plating steps; and FIGS. 2a through 2f showing an embodiment in accordance with the present invention. One of the examples utilizes an internal perforation positioned in the encapsulation and adhesive layer to attach the sub-assembly to form a multilayer printed circuit board; Figure 2g is a second to second embodiment of the present invention in accordance with an embodiment of the present invention. a cross-sectional view of the final multilayer printed circuit board; FIG. 3 is a cross-sectional view of a multilayer printed circuit board having three sub-assemblies attached by the processes of FIGS. 2a through 2f, in accordance with an embodiment of the present invention; Figures 4a through 4j illustrate an alternative process for forming a multilayer printed circuit board using an internal microperforated attachment sub-assembly positioned in an adhesive layer in accordance with one embodiment of the present invention; One of the processes according to FIGS. 4a to 4j includes a cross-sectional exploded view of the sub-assembly of the two closed perforations that are coupled by the adhesive and the conductive paste to form a thin perforation to the sub-assembly; FIG. 6 is a perspective view according to the present invention. An embodiment of the method includes coupling an adhesive and a conductive paste to form a wearer A cross-sectional exploded view of another assembly of the stacked perforations on each of the sub-assemblies to the sub-assembly; FIG. 7 is a schematic illustration of the use of a two-machine having an enlarged surface area in accordance with an embodiment of the present invention; A cross-sectional exploded view of another assembly of the conductive paste microperforations between the drilled perforations and the sub-assembly.
下文詳細描述中,利用示範方式顯示及描述本發明的特定示範性實施例。如同熟習該技術者將瞭解:所描述的示範性實施例可以不同方式作修改,皆不脫離本發明的精神與範圍。為此,圖式及描述係被視為示範性質而非限制性質。可能具有圖中顯示的部份、或圖中未顯示的部份,因為其對於完整瞭解本發明而言並不重要故未在說明書中討論。類似代號係代表類似的元件。In the following detailed description, specific exemplary embodiments of the invention are shown and described. As will be appreciated by those skilled in the art, the described exemplary embodiments may be modified in various ways without departing from the spirit and scope of the invention. To this end, the drawings and description are to be regarded as exemplary rather than limiting. There may be portions shown in the figures, or portions not shown in the figures, as they are not essential to a complete understanding of the invention and are not discussed in the specification. Similar code numbers represent similar components.
第1圖是一用於製造一具有經堆積穿孔之印刷電路板的順序性疊合製程之流程圖,其包括順序性疊合及鍍覆步驟。1 is a flow diagram of a sequential stack process for fabricating a printed circuit board having stacked vias, including sequential stacking and plating steps.
第2a至2f圖顯示根據本發明的一實施例之一用於製造印刷電路板之製程,其包括利用被定位於包封及黏劑層中的內部微穿孔附接經疊合次總成。2a through 2f illustrate a process for fabricating a printed circuit board in accordance with an embodiment of the present invention comprising attaching a laminated sub-assembly using internal microperforations positioned in an encapsulation and adhesive layer.
第2a圖中,該製程開始時係提供一在兩側上皆具有四層及銅墊(譬如箔)102之經疊合次總成100。經疊合次總成100進一步包括兩個經鍍覆或經充填通洞穿孔104。次總成的層可由金屬、陶瓷、或絕緣材料(譬如,FR4,LCP,熱蒙特聚芳醯胺(Thermount),BT,GPY,諸如鐵氟龍(Teflon),熱傳導碳(史塔柏柯(stablecor)),無鹵素等,其中GPY是一種不納入FR4類別之疊層,諸如聚醯亞胺,環乙亞胺經固化環氧樹脂,雙馬來醯亞胺(bismalimide),及其他電性等級的疊層)製成。然而,本發明不在此限。其他實施例中,可使用其他適當的基材及傳導層材料。第2a圖所示的實施例中,次總成層係具有介於從約3至4密耳的一厚度。然而,其他實施例中,次總成層及其他組件可具有其他適當的維度。In Fig. 2a, the process begins with a superimposed subassembly 100 having four layers and copper pads (e.g., foil) 102 on both sides. The superimposed subassembly 100 further includes two plated or filled through holes 104. The sub-assembly layer can be made of metal, ceramic, or insulating materials (eg, FR4, LCP, Thermomount, Thermount, BT, GPY, such as Teflon, heat transfer carbon (Staboco ( Stablecor)), halogen-free, etc., where GPY is a laminate that is not included in the FR4 category, such as polyimine, ethylene-ethylimine cured epoxy, bismalimide, and other electrical properties. Made of a laminate of grades. However, the invention is not limited thereto. In other embodiments, other suitable substrates and conductive layer materials can be used. In the embodiment illustrated in Figure 2a, the sub-assembly layer has a thickness of from about 3 to 4 mils. However, in other embodiments, the sub-assembly layer and other components may have other suitable dimensions.
數項實施例中,經疊合次總成100可使用第1圖所描述的製程予以製造。其他實施例中,次總成可為一具有多個單一金屬層載體及經堆積微穿孔之單一疊合次總成。用於製造電路板之單一疊合製程的態樣係進一步描述於美國專利案No. 7,523,543、美國臨時專利申請案No. 61/189171及美國專利申請案No. 12/772,086中,各案的整體內容合併於本文中以供參考。In several embodiments, the superposed subassembly 100 can be fabricated using the process described in FIG. In other embodiments, the secondary assembly can be a single stacked secondary assembly having a plurality of single metal layer supports and stacked microperforations. The singularity of a single splicing process for the manufacture of a circuit board is further described in U.S. Patent No. 7, 523, 543, U.S. Provisional Patent Application No. 61/189, 171, and U.S. Patent Application Serial No. 12/772,086. The content is incorporated herein by reference.
第2a圖所示的實施例中,經疊合次總成100係包括四個金屬層。其他實施例中,經疊合次總成可包括多於或少於三個金屬層載體。第2a圖所示的實施例中,經疊合次總成係包括兩個通洞穿孔。其他實施例中,經疊合次總成可具有多於或少於兩個穿孔。其他實施例中,通洞穿孔可以經堆積微穿孔、經埋設穿孔及/或封閉穿孔所取代。In the embodiment illustrated in Figure 2a, the superimposed subassembly 100 comprises four metal layers. In other embodiments, the superposed sub-assembly may include more or less than three metal layer supports. In the embodiment illustrated in Figure 2a, the superimposed sub-assembly comprises two through-hole perforations. In other embodiments, the superposed sub-assembly may have more or less than two perforations. In other embodiments, the through hole perforations may be replaced by stacked microperforations, embedded perforations, and/or closed perforations.
第2b圖中,該製程施加一包封材料106至經疊合次總成100的一頂表面並予以固化。數項實施例中,包封材料係為一介電材料。數項實施例中,利用一預選定溫度以一預選定時程加熱次總成及其上的包封材料,藉以達成固化。In Figure 2b, the process applies an encapsulating material 106 to a top surface of the laminated subassembly 100 and cures. In several embodiments, the encapsulating material is a dielectric material. In several embodiments, the secondary assembly and the encapsulating material thereon are heated in a preselected temperature range for a preselected temperature to achieve cure.
包封材料可為任何適當的未經固化絕緣材料,包括但不限於:FR4,LCP,熱蒙特聚芳醯胺(Thermount),BT,GPY,諸如鐵氟龍(Teflon),熱傳導碳(史塔柏柯(stablecor)),無鹵素等,其中GPY是一種不納入FR4類別之疊層,諸如聚醯亞胺,環乙亞胺經固化環氧樹脂,雙馬來醯亞胺(bismalimide),及其他電性等級的疊層。The encapsulating material can be any suitable uncured insulating material including, but not limited to: FR4, LCP, Thermomount Polyamide, BT, GPY, such as Teflon, heat transfer carbon (Stita Stablecor), halogen-free, etc., wherein GPY is a laminate that is not included in the FR4 category, such as polyimine, ethylene-ethylimine cured epoxy, bismalimide, and A stack of other electrical grades.
第2c圖中,該製程施加一疊合黏劑108至經固化的包封材料106之一頂表面。In Figure 2c, the process applies a stack of adhesive 108 to the top surface of one of the cured encapsulants 106.
第2d圖中,該製程係鑽過疊合黏劑108及包封材料106直到銅墊102的一頂表面藉以形成用於微穿孔之洞110。各微穿孔可由介於約4至10密耳直徑之雷射鑽製(及/或機械鑽製)洞所形成。其他實施例中,可使用用於形成穿孔洞之其他適當的技術。此外,可使用其他穿孔尺寸。In Fig. 2d, the process drills the overlay adhesive 108 and encapsulation material 106 until a top surface of the copper pad 102 forms a hole 110 for microperforation. Each microperforation may be formed by a laser drilled (and/or mechanically drilled) hole having a diameter of between about 4 and 10 mils. In other embodiments, other suitable techniques for forming a perforated hole can be used. In addition, other perforation sizes can be used.
第2e圖中,洞110係充填有傳導膏,藉此形成微穿孔112。部分實施例中,微穿孔係充填有銅而非傳導膏。一實施例中,穿孔洞被雷射鑽製時使用傳導膏,且洞被機械鑽製時則使用銅。In Fig. 2e, the hole 110 is filled with a conductive paste, thereby forming microperforations 112. In some embodiments, the microperforation is filled with copper rather than a conductive paste. In one embodiment, the perforated hole is made of a conductive paste when laser is drilled, and copper is used when the hole is mechanically drilled.
第2f圖中,提供一兩側上皆具有銅墊202之第二經疊合次總成200,並帶領其鄰近於第一經疊合次總成100。In Fig. 2f, a second superposed subassembly 200 having a copper pad 202 on both sides is provided and leads adjacent to the first superimposed subassembly 100.
第2g圖是根據本發明的一實施例之第2a至2f圖的最終多層印刷電路板之橫剖視圖。第2g圖中,第一及第二次總成(100,200)被帶領合併且附接。部分應用中,會難以連接及製造具有高尺寸比(aspect ratio)穿孔之板。利用上述製程附接經疊合次總成,將大幅使得附接及製造方法更容易。第2g圖所示的實施例中,在第一經疊合次總成100的頂表面上進行第2b至2e圖的製程。其他實施例中,在經疊合次總成100的頂與底表面上皆進行第2b至2e圖的製程,以容許不只一個第二次總成200附接到第一次總成100。Figure 2g is a cross-sectional view of the final multilayer printed circuit board of Figures 2a through 2f in accordance with an embodiment of the present invention. In the 2g figure, the first and second sub-assemblies (100, 200) are led and attached. In some applications, it may be difficult to join and fabricate panels with high aspect ratio perforations. Attaching the superimposed sub-assembly using the above process will greatly make the attachment and manufacturing process easier. In the embodiment shown in Fig. 2g, the processes of Figs. 2b to 2e are performed on the top surface of the first superposed subassembly 100. In other embodiments, the processes of Figures 2b through 2e are performed on the top and bottom surfaces of the superposed sub-assembly 100 to allow more than one second sub-assembly 200 to be attached to the first sub-assembly 100.
第3圖是根據本發明的一實施例之一包括使用第2a至2f圖製程所附接的三個次總成之多層印刷電路板300的橫剖視圖。其他實施例中,可使用第2a至2f圖的製程附接不只三個次總成。PCB 300係包括三個具有多重銅墊302及通洞穿孔304之次總成。次總成係藉由嵌入包封層(306-1,306-2)及黏劑層(308-1,308-2)中之內部微穿孔312予以附接。第3圖所示的實施例中,使用一充填有一傳導膏的微穿孔來實行次總成至次總成附接。其他實施例中,可使用一實心銅鍍覆微穿孔或實心銅通洞穿孔來實行次總成至次總成附接。Figure 3 is a cross-sectional view of a multilayer printed circuit board 300 including three sub-assemblies attached using the processes of Figures 2a through 2f, in accordance with one embodiment of the present invention. In other embodiments, more than three sub-assemblies may be attached using the processes of Figures 2a through 2f. The PCB 300 series includes three sub-assemblies having multiple copper pads 302 and through-holes 304. The secondary assembly is attached by internal micro-perforations 312 embedded in the encapsulation layers (306-1, 306-2) and the adhesive layers (308-1, 308-2). In the embodiment illustrated in Figure 3, the sub-assembly to sub-assembly attachment is performed using a microperforation filled with a conductive paste. In other embodiments, a sub-assembly to sub-assembly attachment may be performed using a solid copper plated microperforated or solid copper via hole perforation.
第4a至4j圖顯示根據本發明的一實施例之一使用內部微穿孔附接次總成以形成一多層印刷電路板之替代性製程。Figures 4a through 4j illustrate an alternative process for attaching a sub-assembly to form a multilayer printed circuit board using an internal micro-perforation in accordance with an embodiment of the present invention.
第4a圖中,該製程開始時係提供一在兩側上皆具有四層及銅墊(譬如箔)402之經疊合次總成400。經疊合次總成400進一步包括兩個經鍍覆或經充填封閉穿孔404,其耦接到另兩個經鍍覆或經充填封閉穿孔405。次總成的層可由金屬、陶瓷、或絕緣材料(譬如,FR4,LCP,熱蒙特聚芳醯胺(Thermount),BT,GPY,諸如鐵氟龍(Teflon),熱傳導碳(史塔柏柯(stablecor)),無鹵素等,其中GPY是一種不納入FR4類別之疊層,諸如聚醯亞胺,環乙亞胺經固化環氧樹脂,雙馬來醯亞胺(bismalimide),及其他電性等級的疊層)製成。然而,本發明不在此限。其他實施例中,可使用其他適當的基材及傳導層材料。第4a圖所示的實施例中,次總成層係具有介於從約3至4密耳的一厚度。然而,其他實施例中,次總成及其他組件可具有其他適當的維度。In Fig. 4a, the process begins with a superimposed subassembly 400 having four layers and copper pads (e.g., foil) 402 on both sides. The superimposed subassembly 400 further includes two plated or filled closed perforations 404 coupled to the other two plated or filled closed perforations 405. The sub-assembly layer can be made of metal, ceramic, or insulating materials (eg, FR4, LCP, Thermomount, Thermount, BT, GPY, such as Teflon, heat transfer carbon (Staboco ( Stablecor)), halogen-free, etc., where GPY is a laminate that is not included in the FR4 category, such as polyimine, ethylene-ethylimine cured epoxy, bismalimide, and other electrical properties. Made of a laminate of grades. However, the invention is not limited thereto. In other embodiments, other suitable substrates and conductive layer materials can be used. In the embodiment illustrated in Figure 4a, the secondary assembly layer has a thickness of from about 3 to 4 mils. However, in other embodiments, the secondary assembly and other components may have other suitable dimensions.
數項實施例中,經疊合次總成400可使用第1圖所描述的製程予以製造。其他實施例中,次總成可為一具有多個單一金屬層載體及經堆積微穿孔之單一疊合次總成。用於製造電路板之單一疊合製程的態樣係進一步描述於上文參考的專利案與專利申請案中。In several embodiments, the superposed subassembly 400 can be fabricated using the process described in FIG. In other embodiments, the secondary assembly can be a single stacked secondary assembly having a plurality of single metal layer supports and stacked microperforations. A single superposition process for fabricating a circuit board is further described in the patents and patent applications referenced above.
第4a圖所示的實施例中,經疊合次總成400係包括四個金屬層。其他實施例中,經疊合次總成可包括多於或少於三個金屬層載體。第4a圖所示的實施例中,經疊合次總成係包括四個封閉穿孔。其他實施例中,經疊合次總成可具有多於或少於四個穿孔。其他實施例中,封閉穿孔可以通洞、經埋設穿孔及/或經堆積穿孔所取代。 In the embodiment illustrated in Figure 4a, the superimposed subassembly 400 comprises four metal layers. In other embodiments, the superposed sub-assembly may include more or less than three metal layer supports. In the embodiment illustrated in Figure 4a, the superimposed sub-assembly comprises four closed perforations. In other embodiments, the superposed sub-assembly may have more or less than four perforations. In other embodiments, the closed perforations may be replaced by holes, buried perforations, and/or stacked perforations.
第4b圖中,該製程施加一包封材料406至經疊合次總成400的一頂表面並予以固化。數項實施例中,包封材料係為一介電材料。數項實施例中,利用一預選定溫度以一預選定時程加熱次總成及其上的包封材料,藉以達成固化。 In Figure 4b, the process applies an encapsulating material 406 to a top surface of the superposed subassembly 400 and is cured. In several embodiments, the encapsulating material is a dielectric material. In several embodiments, the secondary assembly and the encapsulating material thereon are heated in a preselected temperature range for a preselected temperature to achieve cure.
包封材料可為任何適當的未經固化絕緣材料,包括但不限於:FR4,LCP,熱蒙特聚芳醯胺(Thermount),BT,GPY,諸如鐵氟龍(Teflon),熱傳導碳(史塔柏柯(stablecor)),無鹵素等,其中GPY是一種不納入FR4類別之疊層,諸如聚醯亞胺,環乙亞胺經固化環氧樹脂,雙馬來醯亞胺(bismalimide),及其他電性等級的疊層。 The encapsulating material can be any suitable uncured insulating material including, but not limited to: FR4, LCP, Thermomount Polyamide, BT, GPY, such as Teflon, heat transfer carbon (Stita Stablecor), halogen-free, etc., wherein GPY is a laminate that is not included in the FR4 category, such as polyimine, ethylene-ethylimine cured epoxy, bismalimide, and A stack of other electrical grades.
第4c圖中,該製程係鑽過包封材料406直到銅墊402的一頂表面藉以形成用於微穿孔(或穿孔)之洞410。各微穿孔可由介於約4至10密耳直徑之雷射鑽製(及/或機械鑽製)洞所形成。其他實施例中,可使用用於形成穿孔洞之其他適當的技術。此外,可使用其他穿孔尺寸。 In Fig. 4c, the process drills the encapsulation material 406 until a top surface of the copper pad 402 forms a hole 410 for microperforation (or perforation). Each microperforation may be formed by a laser drilled (and/or mechanically drilled) hole having a diameter of between about 4 and 10 mils. In other embodiments, other suitable techniques for forming a perforated hole can be used. In addition, other perforation sizes can be used.
第4d圖中,洞410係充填有傳導膏,藉此形成封閉穿孔,例如,實心銅微穿孔412。部分實施例中,微穿孔412係充填有傳導膏而非銅。一實施例中,穿孔洞被雷射鑽製時使用傳導膏,且洞被機械鑽製時則使用銅。 In Fig. 4d, the hole 410 is filled with a conductive paste, thereby forming a closed perforation, for example, a solid copper microperforation 412. In some embodiments, the microperforations 412 are filled with a conductive paste instead of copper. In one embodiment, the perforated hole is made of a conductive paste when laser is drilled, and copper is used when the hole is mechanically drilled.
第4e圖中,該製程係成像、顯影、鍍覆銅、添加阻劑 及剝除阻劑以形成一傳導圖案於包封層406上及穿孔412上。傳導圖案係包括被定位於穿孔412頂上之擷取墊414。 In Figure 4e, the process is imaging, developing, plating copper, adding a resist. The resist is stripped to form a conductive pattern on the encapsulation layer 406 and on the vias 412. The conductive pattern includes a pick-up pad 414 that is positioned atop the aperture 412.
第4f圖中,該製程係施加一層之疊合黏劑416至經固化的包封材料406及擷取墊414的一頂表面。 In Figure 4f, the process applies a layer of superposed adhesive 416 to the cured encapsulant 406 and a top surface of the extraction pad 414.
第4g圖中,該製程係鑽過疊合黏劑416直到擷取墊414的一頂表面藉以形成用於細微穿孔之洞418。各細微穿孔可由介於約1至3密耳直徑之雷射鑽製(及/或機械鑽製)洞所形成。其他實施例中,可使用用於形成穿孔洞之其他適當的技術。此外,可使用其他穿孔尺寸。 In Fig. 4g, the process drills the laminated adhesive 416 until a top surface of the extraction pad 414 is formed to form a hole 418 for fine perforation. Each of the fine perforations may be formed by a laser drilled (and/or mechanically drilled) hole having a diameter of between about 1 and 3 mils. In other embodiments, other suitable techniques for forming a perforated hole can be used. In addition, other perforation sizes can be used.
第4h圖中,洞418係充填有傳導膏,藉此形成微穿孔420。 In Figure 4h, the hole 418 is filled with a conductive paste, thereby forming microperforations 420.
第4i圖中,係形成且對準在其一表面上具有實質與第4e圖的第一次總成400類似的形貌體之一第二經疊合次總成400-2-包括兩封閉實心銅微穿孔及位於其上的傳導墊,故使得第一經疊合總成400之充填有細傳導膏的微穿孔以及第二經疊合總成400-2的對應傳導墊在其被帶領合併附接時將受到物理性及電性耦接、並由疊合黏劑416所固接。 In Fig. 4i, a second superposed subassembly 400-2- comprising two closures is formed and aligned on a surface thereof having substantially similar to the first assembly 400 of Fig. 4e. The solid copper microperforation and the conductive pad thereon are such that the micro-perforation of the first superimposed assembly 400 filled with fine conductive paste and the corresponding conductive pad of the second superposed assembly 400-2 are led The combined attachment will be physically and electrically coupled and secured by the laminated adhesive 416.
第4j圖是根據本發明的一實施例之第4a至4i圖的最終多層印刷電路板之橫剖視圖。第4j圖中,第一及第二次總成(400,400-2)係被帶領合併且附接。部分應用中,會難以連接及製造具有高尺寸比(aspect ratio)穿孔之板。部分應用中,利用傳統製造方法會太難以製造複雜的穿孔結構。利用上述製程附接經疊合次總成,將大幅使得附接及製造方法更容易。此外,經疊合次總成之間的傳導膏或傳導墨水微穿孔係很細薄(譬如3至5密耳)。在不受限於任何特定理論 下,細微穿孔或接合部可提供良好的高頻傳導性。數項實施例中,接合部的電連導性不像諸如銅等高傳導金屬般良好,然而,因為接合部為細薄,其可對於具有高頻特徵的信號(譬如射頻型信號及類似物)提供傳導性。此外,細銅膏接合部可對於流過的電流提供極小擾亂。 Figure 4j is a cross-sectional view of the final multilayer printed circuit board of Figures 4a through 4i in accordance with an embodiment of the present invention. In Figure 4j, the first and second sub-assemblies (400, 400-2) are led and attached. In some applications, it may be difficult to join and fabricate panels with high aspect ratio perforations. In some applications, it is too difficult to make complex perforated structures using conventional manufacturing methods. Attaching the superimposed sub-assembly using the above process will greatly make the attachment and manufacturing process easier. In addition, the conductive paste or conductive ink microperforation between the superposed sub-assemblies is very thin (e.g., 3 to 5 mils). Not limited to any particular theory Underneath, fine perforations or joints provide good high frequency conductivity. In several embodiments, the electrical conductivity of the joint is not as good as that of a highly conductive metal such as copper, however, because the joint is thin, it can be used for signals having high frequency characteristics (such as radio frequency signals and the like). Provide conductivity. In addition, the fine copper paste joint can provide minimal disturbance to the current flowing through.
第4a至4j圖所示的實施例中,在第一經疊合次總成400的頂表面上進行該製程。其他實施例中,在經疊合次總成400的頂與底表面上皆進行該製程,以容許不只一個第二次總成400-2附接到第一次總成400。 In the embodiment illustrated in Figures 4a through 4j, the process is performed on the top surface of the first superposed subassembly 400. In other embodiments, the process is performed on the top and bottom surfaces of the superposed subassembly 400 to allow more than one second subassembly 400-2 to be attached to the first subassembly 400.
數項實施例中,傳導膏或傳導墨水可包括銅與錫的一混合物。其他實施例中,可對於傳導膏使用其他適當的傳導材料。 In several embodiments, the conductive paste or conductive ink can comprise a mixture of copper and tin. In other embodiments, other suitable conductive materials can be used for the conductive paste.
第5圖是次總成至次總成附接500之橫剖視分解圖,該附接包括兩封閉穿孔(512-1,512-2),其由黏劑(未圖示)及傳導膏520耦接以形成符合第4a至4j圖之製程的一細微穿孔420。封閉穿孔(512-1,512-2)各者係包括位於其外表面上之傳導墊(502-1,502-2)及位於其內表面上之傳導墊(514-1,514-2)。傳導膏結構520係形成黏劑內之一細微穿孔(請見第4j圖),其可具有上文討論的理想性質。 Figure 5 is a cross-sectional exploded view of the sub-assembly to sub-assembly attachment 500, the attachment comprising two closed perforations (512-1, 512-2) consisting of an adhesive (not shown) and a conductive paste 520 is coupled to form a fine perforation 420 that conforms to the process of Figures 4a through 4j. The closed perforations (512-1, 512-2) each include a conductive pad (502-1, 502-2) on its outer surface and a conductive pad (514-1, 514-2) on its inner surface. . The conductive paste structure 520 forms a fine perforation in the adhesive (see Figure 4j) which may have the desirable properties discussed above.
第6圖是根據本發明的一實施例之包括藉由黏劑(未圖示)及一傳導膏穿孔606耦接之各次總成上的經堆積穿孔(602,604)之另一次總成至次總成附接600的橫剖視分解圖。相較於第5圖的次總成,傳導膏穿孔606係實質地較高(譬如z軸長度)。此較高形式的傳導膏穿孔係較容易製造並 提供板層之間阻抗的良好控制。 6 is another assembly of stacked vias (602, 604) on each of the subassemblies coupled by an adhesive (not shown) and a conductive paste via 606, in accordance with an embodiment of the present invention. A cross-sectional exploded view of the secondary assembly attachment 600. The conductive paste perforations 606 are substantially higher (e.g., z-axis length) compared to the secondary assembly of Figure 5. This higher form of conductive paste perforation is easier to manufacture and Provides good control of the impedance between the layers.
第7圖是根據本發明的一實施例之使用一位居具有放大表面積(708,710)的兩機械鑽製穿孔(704,706)之間的傳導膏微穿孔702之另一次總成至次總成附接700的橫剖視分解圖。 Figure 7 is a diagram showing another assembly of conductive paste microperforations 702 between two mechanically drilled perforations (704, 706) having one enlarged surface area (708, 710) in accordance with an embodiment of the present invention. A cross-sectional exploded view of the assembly attachment 700.
雖然上文描述含有本發明許多特定實施例,這些實施例不應被詮釋為對於本發明的範圍之限制,而是成為其特定實施例的範例。為此,本發明的範圍不應由所顯示的實施例決定,而是由申請專利範圍及其均等物決定。譬如,雖已表明特定組件由銅形成,可使用銅以外的其他適當傳導材料。 While the above description contains many specific embodiments of the present invention, these embodiments are not to be construed as limiting the scope of the invention For that reason, the scope of the invention should not be determined by the embodiments shown, but by the scope of the claims and their equivalents. For example, although specific components have been shown to be formed of copper, other suitable conductive materials other than copper may be used.
100‧‧‧經疊合次總成 100‧‧‧ superimposed sub-assembly
102,202,302,402‧‧‧銅墊 102,202,302,402‧‧‧ copper pad
104‧‧‧經充填通洞穿孔 104‧‧‧Perforated through hole
106,406‧‧‧包封材料 106,406‧‧‧Encapsulation material
108,416‧‧‧疊合黏劑 108,416‧‧‧Overlay adhesive
110,410,418‧‧‧洞 110,410,418‧‧ holes
112,412,420‧‧‧微穿孔 112,412,420‧‧‧Microperforation
200,400-2‧‧‧第二經疊合次總成 200,400-2‧‧‧Second superimposed sub-assembly
300‧‧‧多層印刷電路板 300‧‧‧Multilayer printed circuit boards
304‧‧‧通洞穿孔 304‧‧‧ hole piercing
306-1,306-2‧‧‧包封層 306-1, 306-2‧‧‧Encapsulation layer
308-1,308-2‧‧‧黏劑層 308-1, 308-2‧‧‧ adhesive layer
312‧‧‧內部微穿孔 312‧‧‧Internal microperforation
400‧‧‧第一經疊合次總成 400‧‧‧First superimposed sub-assembly
404,405‧‧‧經鍍覆或經充填封閉穿孔 404,405‧‧‧Cleaved or filled closed perforations
414‧‧‧擷取墊 414‧‧‧Capture pad
500,600,700‧‧‧次總成至次總成附接 500,600,700‧‧‧ sub-assembly to sub-assembly
502-1,502-2,514-1,514-2‧‧‧傳導墊 502-1, 502-2, 514-1, 514-2‧‧‧ Conductive mat
512-1,512-2‧‧‧封閉穿孔 512-1,512-2‧‧‧closed perforation
520‧‧‧傳導膏結構 520‧‧‧Transfer paste structure
602,604‧‧‧經堆積穿孔 602,604‧‧‧Stacked perforations
606‧‧‧傳導膏穿孔 606‧‧‧Transfer paste perforation
702‧‧‧傳導膏微穿孔 702‧‧‧Transfer paste microperforation
704,706‧‧‧機械鑽製穿孔 704,706‧‧‧Mechanical drilling perforation
708,710‧‧‧放大表面積 708,710‧‧‧Amplified surface area
第1圖是一用於製造一具有經堆積穿孔的印刷電路板之順序性疊合製程的流程圖,其包括順序性疊合及鍍覆步驟;第2a至2f圖顯示根據本發明的一實施例之一利用被定位於包封及黏劑層中的內部穿孔附接次總成以形成一多層印刷電路板之製程;第2g圖是根據本發明的一實施例之第2a至2f圖的最終多層印刷電路板之橫剖視圖;第3圖是根據本發明的一實施例之一具有利用第2a至2f圖的製程所附接之三個次總成之多層印刷電路板的橫剖視圖;第4a至4j圖顯示根據本發明的一實施例之一利用被定位於一黏劑層中的內部微穿孔附接次總成以形成一多層印刷電路板之替代性製程; 第5圖是根據第4a至4j圖製程之一包括由黏劑及傳導膏耦接形成一細穿孔的兩封閉穿孔之次總成至次總成附接的橫剖視分解圖;第6圖是根據本發明的一實施例之包括由黏劑及傳導膏耦接形成一穿孔之各次總成上的經堆積穿孔之另一次總成至次總成附接之橫剖視分解圖;第7圖是根據本發明的一實施例使用一位居具有放大表面積的兩經機械鑽製穿孔之間的傳導膏微穿孔之另一次總成至次總成附接之橫剖視分解圖。 1 is a flow chart of a sequential stacking process for fabricating a printed circuit board having stacked vias, including sequential stacking and plating steps; and FIGS. 2a through 2f showing an embodiment in accordance with the present invention. One of the examples utilizes an internal perforation positioned in the encapsulation and adhesive layer to attach the sub-assembly to form a multilayer printed circuit board; Figure 2g is a second to second embodiment of the present invention in accordance with an embodiment of the present invention. a cross-sectional view of the final multilayer printed circuit board; FIG. 3 is a cross-sectional view of a multilayer printed circuit board having three sub-assemblies attached by the processes of FIGS. 2a through 2f, in accordance with an embodiment of the present invention; Figures 4a through 4j illustrate an alternative process for forming a multilayer printed circuit board using an internal microperforated attachment sub-assembly positioned in an adhesive layer in accordance with one embodiment of the present invention; Figure 5 is a cross-sectional exploded view of the sub-assembly to the sub-assembly of one of the two closed perforations formed by bonding the adhesive and the conductive paste according to the processes of Figures 4a to 4j; Figure 6 Is a cross-sectional exploded view of another assembly to sub-assembly of a stacked perforation on each of the sub-assemblies formed by the adhesive and the conductive paste coupled to the adhesive and the conductive paste, in accordance with an embodiment of the present invention; 7 is a cross-sectional, exploded view of another assembly to subassembly attachment of a conductive paste microperforation between two mechanically drilled perforations having an enlarged surface area, in accordance with an embodiment of the present invention.
100...經疊合次總成100. . . Superimposed subassembly
102...銅墊102. . . Copper pad
104...經充填通洞穿孔104. . . Perforation through the filling hole
106...包封材料106. . . Encapsulation material
108...疊合黏劑108. . . Superimposed adhesive
110...洞110. . . hole
112...微穿孔112. . . Microperforation
Claims (23)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100141850A TWI590732B (en) | 2011-11-16 | 2011-11-16 | Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100141850A TWI590732B (en) | 2011-11-16 | 2011-11-16 | Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201322856A TW201322856A (en) | 2013-06-01 |
TWI590732B true TWI590732B (en) | 2017-07-01 |
Family
ID=49032603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100141850A TWI590732B (en) | 2011-11-16 | 2011-11-16 | Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI590732B (en) |
-
2011
- 2011-11-16 TW TW100141850A patent/TWI590732B/en active
Also Published As
Publication number | Publication date |
---|---|
TW201322856A (en) | 2013-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9736948B2 (en) | Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies | |
JP6200178B2 (en) | Electronic component built-in substrate and manufacturing method thereof | |
US9247646B2 (en) | Electronic component built-in substrate and method of manufacturing the same | |
JP6795137B2 (en) | Manufacturing method of printed circuit board with built-in electronic elements | |
US20120033394A1 (en) | Method of fabricating embedded component package structure and the package structure thereof | |
US8453322B2 (en) | Manufacturing methods of multilayer printed circuit board having stacked via | |
TW201501600A (en) | Printed circuit board and method for manufacturing same | |
JP2004319962A (en) | Flex rigid printed wiring board and its manufacturing method | |
JP2010157664A (en) | Circuit substrate with electric and electronic component incorporated therein, and method of manufacturing the same | |
KR101282965B1 (en) | Novel printed circuit board and method of producing the same | |
TW201406222A (en) | Multilayer printed circuit board and method for manufacturing same | |
KR101205464B1 (en) | Method for manufacturing a printed circuit board | |
TWI590732B (en) | Systems and methods of manufacturing printed circuit boards using blind and internal micro vias to couple subassemblies | |
JP4899409B2 (en) | Multilayer printed wiring board and manufacturing method thereof | |
KR101887754B1 (en) | Rigid flexible circuit board manufacturing method | |
JP2005302991A (en) | Manufacturing method of multi-layered wiring substrate | |
JP2005123332A (en) | Circuit board and method of manufacturing thereof | |
JP2008258358A (en) | Rigid flexible board and manufacturing method thereof | |
JP3645780B2 (en) | Build-up multilayer printed wiring board and manufacturing method thereof | |
JP4803918B2 (en) | Manufacturing method of multilayer wiring board | |
JP4803919B2 (en) | Manufacturing method of multilayer wiring board | |
JP2007027504A (en) | Multilevel wiring board, and method and apparatus for manufacturing the same | |
JP6001475B2 (en) | Wiring board | |
JPH0750487A (en) | Multilayer printed wiring board | |
JP2006013172A (en) | Method for manufacturing multilayer wiring board |