JPH0750487A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JPH0750487A
JPH0750487A JP3286094A JP3286094A JPH0750487A JP H0750487 A JPH0750487 A JP H0750487A JP 3286094 A JP3286094 A JP 3286094A JP 3286094 A JP3286094 A JP 3286094A JP H0750487 A JPH0750487 A JP H0750487A
Authority
JP
Japan
Prior art keywords
hole
layer
printed wiring
blind via
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3286094A
Other languages
Japanese (ja)
Inventor
Kunio Setsuda
国男 説田
Katsumi Kosaka
克己 匂坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP3286094A priority Critical patent/JPH0750487A/en
Publication of JPH0750487A publication Critical patent/JPH0750487A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Abstract

PURPOSE:To prevent the deterioration of electric characteristics of blind via holes by constituting the sidewall of each via hole of a through hole formed through outer-layer substrates and adhesive layers and constituting the adhesive layers of non-flow type prepregs. CONSTITUTION:A multilayer printed wiring board is constituted of inner-layer substrates 7 provided with inner-layer conductor patterns 12 on their surface sides and outer-layer substrates 5 which are integrally joined to the surfaces of the substrates 7 with adhesive layers (adhesive sheets 4 composed of non-flow type prepregs). The substrates 5 have blind via holes 14 opened to the patterns 12. Each hole 14 has a chemically plated copper film 10 which integrally and electrically connects one pattern 12 and an outer-layer conductor pattern 11 to the internal surface of the hole 14 and its sidewall is constituted of a through hole 6 formed through the substrates 5 and layers 4. The adhesive layers 4 are formed of non-flow type prepregs.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,各種電子機器の電子部
品を実装するために使用される多層プリント配線板に関
し,特に非貫通孔(以下,ブラインド・バイアホールと
称す)を有する多層プリント配線板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board used for mounting electronic parts of various electronic devices, and particularly to a multilayer printed wiring having a non-through hole (hereinafter referred to as a blind via hole). Regarding the board.

【0002】[0002]

【従来技術】従来のプリント配線板は,部品挿入用の孔
やバイアホールを貫通させて,めっき等によって孔内壁
に導体層を形成するのが一般的である。しかし,近年,
電子機器の性能上及び経済上のニーズから実装の高密度
化が進んでおり,プリント配線板においてもより一層高
密度化への要求が高まってきている。
2. Description of the Related Art In a conventional printed wiring board, it is general that a conductor layer is formed on the inner wall of the hole by passing through a hole for inserting a component or a via hole and plating. However, in recent years
Due to the performance and economic needs of electronic equipment, higher density packaging is being made, and there is an increasing demand for even higher density in printed wiring boards.

【0003】ところが,バイアホールを貫通孔で設ける
従来の多層プリント配線板にあっては,このバイアホー
ルによって,高密度化のための配線密度が著しく阻害さ
れるという問題が生じる。また,高多層化を招来して,
アスペクト比(外層基材の厚さと当該外層基材に穴明け
する穴径の比)が増加し,スルーホールの信頼性ならび
経済性も必ずしも満足するものではなかった。
However, in the conventional multilayer printed wiring board in which the via holes are provided as through holes, there is a problem in that the via holes significantly impede the wiring density for high density. In addition, as a result of increasing the number of layers,
The aspect ratio (ratio between the thickness of the outer layer base material and the diameter of the hole drilled in the outer layer base material) increased, and the reliability and economical efficiency of the through hole were not always satisfactory.

【0004】これに対して,ブラインド・バイアホール
によって配線密度を向上させる設計が提案されており,
これをブラインド・バイアホールの製造上から考慮する
と,次の2つの試みがなされている。
On the other hand, a design for improving the wiring density by using blind via holes has been proposed.
Considering this from the viewpoint of manufacturing blind via holes, the following two attempts have been made.

【0005】即ち,その第1の試みは,ドリルによって
ブラインド・バイアホールを形成する方法であり,この
方法は,多層基板を形成後,ドリルによって必要なブラ
インド・バイアホールを形成するものである。この場合
には,多層基板の厚み方向に対してドリルの深さを制御
する必要がある。しかし,多層基板の製造時にはロット
間の板の厚みの変動は避けられず,ブラインド・バイア
ホールの底部と次の層の導体回路との距離が変動し,電
気的特性の変動が大きくなるという欠点がある。また,
片面ずつ穴明けし,さらに貫通孔を穴明けせざるを得な
いという制約があり,量産するには不向きであった。
That is, the first attempt is a method of forming blind via holes by a drill, and this method is to form a necessary blind via hole by a drill after forming a multilayer substrate. In this case, it is necessary to control the depth of the drill in the thickness direction of the multilayer board. However, when manufacturing a multi-layered board, it is inevitable that the thickness of the board varies from lot to lot, and the distance between the bottom of the blind via hole and the conductor circuit of the next layer varies, resulting in a large variation in electrical characteristics. There is. Also,
It was not suitable for mass production because it had to be drilled on each side and then through holes.

【0006】第2の試みは,あらかじめバイアホールを
設けたプリント配線板を,プリプレグを介して積層する
方法である。しかし,この方法は,最外層にバイアホー
ルを設けたプリント配線板を使用するため,最外層の銅
めっき厚みが大きくなって,ファインパターンには不適
当であり,また,経済的にもニーズを満足するものでは
なかった。
The second attempt is a method of laminating printed wiring boards, which are provided with via holes in advance, through prepregs. However, this method uses a printed wiring board having a via hole in the outermost layer, which increases the thickness of the copper plating in the outermost layer, making it unsuitable for fine patterns. I was not satisfied.

【0007】また,上記プリプレグの接着層を用いる場
合においても,基板を積層し,加熱圧着したとき,この
接着層がブラインド・バイアホール用の貫通孔内に流出
し,貫通孔の直下の導体パターンが接着層で汚れて(覆
われる)しまうことがあった。
Also, when the adhesive layer of the prepreg is used, when the substrates are laminated and thermocompression bonded, the adhesive layer flows out into the through hole for the blind via hole, and the conductor pattern immediately below the through hole is formed. Sometimes became dirty (covered) with the adhesive layer.

【0008】上記の導体パターンが,流出した接着層で
汚れると,貫通孔及びその直下の導体パターン上にブラ
インド・バイアホール用の化学銅めっきを施したとき,
この化学銅めっきが形成されない部分を生ずる。そのた
め内層基板の導体パターンとブラインド・バイアホール
との間の電気的接続性が低下し,ブラインド・バイアホ
ールの電気的特性が悪化してしまう。
When the above-mentioned conductor pattern is contaminated with the adhesive layer that has flowed out, when chemical copper plating for blind via holes is applied to the through hole and the conductor pattern immediately below it,
This causes a portion where the chemical copper plating is not formed. As a result, the electrical connectivity between the conductor pattern on the inner layer substrate and the blind via hole is degraded, and the electrical characteristics of the blind via hole are deteriorated.

【0009】[0009]

【解決しようとする課題】本発明は,かかる従来の問題
点に鑑み,電気的特性に優れたブラインド・バイアホー
ルを有する多層プリント配線板を提供しようとするもの
である。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and it is an object of the present invention to provide a multilayer printed wiring board having a blind via hole excellent in electrical characteristics.

【0010】[0010]

【課題の解決手段】本発明は,表面側に内層導体パター
ンを設けた内層基板と,該内層基板の表面側に接着層を
介して一体的に接合した外層基板とよりなると共に,該
外層基板には上記内層導体パターンに開口したブライン
ド・バイアホールを有し,かつ該ブラインド・バイアホ
ールにはその内面と上記内層導体パターンと外層基板上
の外層導体パターンとの三者を一体的かつ電気的に接続
する化学銅めっきを有する多層プリント配線板におい
て,上記ブラインド・バイアホールは,その側壁が上記
外層基板と上記接着層を貫通して形成された貫通孔によ
り構成され,また,上記接着層はノンフロータイプのプ
リプレグを用いてなることを特徴とする多層プリント配
線板にある。
The present invention comprises an inner layer substrate having an inner layer conductor pattern provided on the front surface side and an outer layer substrate integrally bonded to the front surface side of the inner layer substrate via an adhesive layer. Has a blind via hole opened in the inner layer conductor pattern, and the blind via hole integrally and electrically has its inner surface, the inner layer conductor pattern, and the outer layer conductor pattern on the outer layer substrate. In the multilayer printed wiring board having the chemical copper plating connected to, the blind via hole has a sidewall formed by a through hole formed through the outer layer substrate and the adhesive layer, and the adhesive layer is The multilayer printed wiring board is characterized by using a non-flow type prepreg.

【0011】次に,本発明の多層プリント配線板につい
て,その製造方法と共に,図面を用いて詳細に説明す
る。図1は,片面銅張積層板3の樹脂基材2側に,前記
ノンフロータイプの接着シート4からなる接着層を仮接
着した後に,ドリルによって穴明けした外層基材5を示
した部分拡大断面図である。ここに重要なことは,上記
接着層として,ノンフロータイプのプリプレグを用いた
ことである。また,上記貫通孔6がブラインド・バイア
ホールを形成する穴であり,最外層の外層導体パターン
11と次の層の内層導体パターン12とを電気的に接続
する孔である。
Next, the multilayer printed wiring board of the present invention will be described in detail with reference to the drawings together with its manufacturing method. FIG. 1 is a partially enlarged view showing an outer layer base material 5 in which a non-flow type adhesive sheet 4 is temporarily adhered to a resin base material 2 side of a single-sided copper clad laminate 3 and then a hole is drilled. FIG. What is important here is that a non-flow type prepreg was used as the adhesive layer. The through holes 6 are holes that form blind via holes, and are holes that electrically connect the outermost conductor pattern 11 of the outermost layer and the inner conductor pattern 12 of the next layer.

【0012】図2は,前記外層基材5を,公知の方法に
より形成された内層基板7上の所望の導体パターンに位
置合わせして積み重ねた後加熱加圧して接着し,目的の
層数の積層基板8を形成する工程を示した部分拡大断面
図である。図3は,公知の方法により,前記積層基板8
にスルーホール9を穴明けし,銅めっき10を行なって
外層導体パターンを形成した,目的とする多層プリント
配線板の部分拡大断面図である。なお,本発明に示す内
層基板7は,少なくとも一層の導体回路を有する基板を
意味するものである。
FIG. 2 shows that the outer layer base material 5 is aligned and stacked on a desired conductor pattern on the inner layer substrate 7 formed by a known method, and then heated and pressed to bond the layers. FIG. 6 is a partially enlarged cross-sectional view showing a step of forming a laminated substrate 8. FIG. 3 shows the laminated substrate 8 according to a known method.
FIG. 3 is a partially enlarged cross-sectional view of a target multilayer printed wiring board in which through holes 9 are drilled and copper plating 10 is performed to form outer layer conductor patterns. The inner layer substrate 7 shown in the present invention means a substrate having at least one conductor circuit.

【0013】[0013]

【作用及び効果】本発明にあっては,外層基材と内層基
板との接合に当たって,接着層としてノンフロータイプ
のプリプレグを用いている。そのため,内層基板と外層
基材とを加熱圧着する場合においては,従来の接着剤の
ごとく流出することがない。そのため,接着層が内層基
板の導体パターンに開口している上記貫通孔の内部,つ
まり該貫通孔の直下にある内層基板の導体パターン上に
は,接着層が流出して来ていない。
In the present invention, a non-flow type prepreg is used as the adhesive layer when joining the outer layer base material and the inner layer substrate. Therefore, when the inner layer substrate and the outer layer base material are heat-pressed, they do not flow out unlike the conventional adhesive. Therefore, the adhesive layer does not flow out into the inside of the through hole where the adhesive layer opens to the conductor pattern of the inner layer substrate, that is, onto the conductor pattern of the inner layer substrate immediately below the through hole.

【0014】それ故,貫通孔内の上記化学銅めっきは貫
通孔の側壁面は勿論のこと,該貫通孔の直下の導体パタ
ーン上にも連続して形成されている。したがって,ブラ
インド・バイアホールは電気的特性に優れている。した
がって,本発明によれば,電気的特性に優れたブライン
ド・バイアホールを有する多層プリント配線板を提供す
ることができる。
Therefore, the chemical copper plating in the through hole is continuously formed not only on the side wall surface of the through hole but also on the conductor pattern immediately below the through hole. Therefore, blind via holes have excellent electrical characteristics. Therefore, according to the present invention, it is possible to provide a multilayer printed wiring board having a blind via hole having excellent electrical characteristics.

【0015】[0015]

【実施例】次に本発明の実施例につき,図1〜図3を用
いて説明する。本例の多層プリント配線板は図2,図3
に示すごとく,表面側に内層導体パターン12を設けた
内層基板7と,該内層基板7の表面側に接着層(ノンフ
ロータイプのプリプレグの接着シート4)を介して一体
的に接合した外層基板5とよりなると共に,該外層基板
5には上記内層導体パターン12に開口したブラインド
・バイアホール14を有する。
Embodiments of the present invention will be described below with reference to FIGS. The multilayer printed wiring board of this example is shown in FIGS.
As shown in FIG. 5, an inner layer substrate 7 having an inner layer conductor pattern 12 provided on the surface side, and an outer layer substrate integrally bonded to the surface side of the inner layer substrate 7 via an adhesive layer (adhesive sheet 4 of a non-flow type prepreg). 5, the outer layer substrate 5 has a blind via hole 14 opened to the inner layer conductor pattern 12.

【0016】該ブラインド・バイアホール14にはその
内面と内層導体パターン12と外層基板5上の外層導体
パターン11との三者を一体的かつ電気的に接続する化
学銅めっき10を有する。そして,ここに注目すべきこ
とは,上記ブラインド・バイアホール14は,その側壁
が上記外層基板5と上記接着層とを貫通して形成された
貫通孔6により構成され,また上記接着層はノンフロー
タイプのプリプレグからなる接着シート4を用いている
ことである。
The blind via hole 14 has a chemical copper plating 10 for integrally and electrically connecting the inner surface thereof, the inner layer conductor pattern 12 and the outer layer conductor pattern 11 on the outer layer substrate 5. It should be noted that the blind via hole 14 has a side wall formed by a through hole 6 formed by penetrating the outer layer substrate 5 and the adhesive layer, and the adhesive layer is not formed. That is, the adhesive sheet 4 made of a flow type prepreg is used.

【0017】上記多層プリント配線板についてその製法
を示せば,まず,ガラスエポキシ片面銅張積層板(0.
1mm厚,銅箔厚さ18μm)3を用い,その樹脂基材
2側に,ノンフロータイプのプリプレグであって厚さ4
0μmの接着シート4(ニッカン工業製,商品名:SA
F)を一枚,50℃の温度で,10kg/cm2 の圧力
を約20分間かけて仮接着させた。これにより,片面銅
張積層板3の樹脂基材2側に接着シート4からなる接着
層を仮接着した。
The manufacturing method of the above multilayer printed wiring board will be described. First, a glass epoxy single-sided copper clad laminate (0.
1 mm thick, copper foil thickness 18 μm) 3, and on the resin base material 2 side, a non-flow type prepreg with a thickness of 4
0 μm adhesive sheet 4 (manufactured by Nikkan Kogyo, trade name: SA
One piece of F) was temporarily bonded at a temperature of 50 ° C. and a pressure of 10 kg / cm 2 for about 20 minutes. As a result, the adhesive layer made of the adhesive sheet 4 was temporarily adhered to the resin base material 2 side of the single-sided copper-clad laminate 3.

【0018】その後,外層基材5における所定の位置
に,直径0.4mmの貫通孔6をドリルによって穴明け
し,図1に示す外層基材5を得た。なお,図1におい
て,符号1は銅箔である。一方,厚さ0.4mm(銅箔
厚さ18μm)のガラスエポキシ銅張積層板に,テンテ
ィング法で内層導体パターン12(図3)を形成した2
枚の基板7aを,ガラスエポキシプリプレグ7bを介し
て積層し,加熱圧着して厚さ1.2mmの内層基板7を
得た。
Then, a through hole 6 having a diameter of 0.4 mm was drilled at a predetermined position in the outer layer base material 5 by a drill to obtain the outer layer base material 5 shown in FIG. In FIG. 1, reference numeral 1 is a copper foil. On the other hand, the inner layer conductor pattern 12 (FIG. 3) was formed on the glass epoxy copper clad laminate having a thickness of 0.4 mm (copper foil thickness of 18 μm) by the tenting method.
The substrates 7a were laminated on each other with the glass epoxy prepreg 7b interposed therebetween and thermocompression bonded to obtain an inner layer substrate 7 having a thickness of 1.2 mm.

【0019】次に,基準穴にピンを立てて外層基材5の
上記貫通孔6と,内層基板7の所望の内層導体パターン
12とを位置合わせして積層した後,150℃の温度
で,20kg/cm2 の圧力をかけて,20分間加熱圧
着して積層基板8とした(図2)。その後,図3に示す
ごとく,上記積層基板8における所定の位置にスルーホ
ール9をドリルによって穴明けした。次いで,公知の化
学銅めっき10及び電気銅めっき10を施し,エッチン
グ処理によって,積層基板8の最外層の外層導体パター
ン11を形成した。
Next, a pin is erected in the reference hole, the through hole 6 of the outer layer base material 5 and the desired inner layer conductor pattern 12 of the inner layer substrate 7 are aligned and laminated, and then at a temperature of 150 ° C. A pressure of 20 kg / cm 2 was applied and thermocompression bonding was performed for 20 minutes to obtain a laminated substrate 8 (FIG. 2). After that, as shown in FIG. 3, through holes 9 were drilled at predetermined positions in the laminated substrate 8. Then, known chemical copper plating 10 and electrolytic copper plating 10 were applied, and an outermost conductor pattern 11 of the outermost layer of the laminated substrate 8 was formed by etching.

【0020】これにより,前記したごとき,本発明に係
る6層の多層プリント配線板(図3)を得た。上記のご
とく,本例においては,接着層としてノンフロータイプ
のプリプレグからなる接着シート4を用いている。その
ため,上記加熱圧着時に接着層がブラインド・バイアホ
ール及びその直下の内層基板の導体パターン上に流出し
ていない。そのため,ブラインド・バイアホール用の化
学銅めっきは,連続して均一に形成できる。それ故,電
気的特性に優れたブラインド・バイアホールを有する多
層プリント配線板を提供することができる。
As a result, a 6-layer multilayer printed wiring board (FIG. 3) according to the present invention was obtained as described above. As described above, in this example, the adhesive sheet 4 made of a non-flow type prepreg is used as the adhesive layer. Therefore, the adhesive layer does not flow onto the blind via hole and the conductor pattern of the inner layer substrate immediately below the blind via hole during the above-mentioned thermocompression bonding. Therefore, chemical copper plating for blind via holes can be formed continuously and uniformly. Therefore, it is possible to provide a multilayer printed wiring board having a blind via hole having excellent electrical characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例における多層プリント配線板の製造工程
を示す説明図。
FIG. 1 is an explanatory view showing a manufacturing process of a multilayer printed wiring board in an example.

【図2】図1に続く工程の説明図。FIG. 2 is an explanatory view of a process following FIG.

【図3】実施例において得られた多層プリント配線板の
断面図。
FIG. 3 is a cross-sectional view of a multilayer printed wiring board obtained in an example.

【符号の説明】[Explanation of symbols]

3・・・片面銅張積層板, 4・・・接着シート, 5・・・外層基材, 6・・・ブラインド・バイアホール, 7・・・内層基板, 8・・・積層基板, 10・・・銅めっき, 11・・・外層導体パターン, 12・・・内層導体パターン, 3 ... Single-sided copper clad laminate, 4 ... Adhesive sheet, 5 ... Outer layer base material, 6 ... Blind via hole, 7 ... Inner layer substrate, 8 ... Laminated substrate, 10. ..Copper plating, 11 ... Outer layer conductor pattern, 12 ... Inner layer conductor pattern,

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 表面側に内層導体パターンを設けた内層
基板と,該内層基板の表面側に接着層を介して一体的に
接合した外層基板とよりなると共に,該外層基板には上
記内層導体パターンに開口したブラインド・バイアホー
ルを有し,かつ該ブラインド・バイアホールにはその内
面と上記内層導体パターンと外層基板上の外層導体パタ
ーンとの三者を一体的かつ電気的に接続する化学銅めっ
きを有する多層プリント配線板において,上記ブライン
ド・バイアホールは,その側壁が上記外層基板と上記接
着層を貫通して形成された貫通孔により構成され,ま
た,上記接着層はノンフロータイプのプリプレグを用い
てなることを特徴とする多層プリント配線板。
1. An inner layer substrate having an inner layer conductor pattern provided on the front surface side, and an outer layer substrate integrally joined to the front surface side of the inner layer substrate via an adhesive layer, wherein the outer layer substrate has the inner layer conductor. Chemical copper having a blind via hole opened in the pattern and integrally and electrically connecting the inner surface of the blind via hole with the inner conductor pattern and the outer conductor pattern on the outer substrate. In a multilayer printed wiring board having a plating, the blind via hole has a sidewall formed by a through hole formed through the outer substrate and the adhesive layer, and the adhesive layer is a non-flow type prepreg. A multilayer printed wiring board, characterized by comprising:
JP3286094A 1994-02-03 1994-02-03 Multilayer printed wiring board Pending JPH0750487A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3286094A JPH0750487A (en) 1994-02-03 1994-02-03 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3286094A JPH0750487A (en) 1994-02-03 1994-02-03 Multilayer printed wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP62193360A Division JPH0671143B2 (en) 1987-07-31 1987-07-31 Method for manufacturing multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH0750487A true JPH0750487A (en) 1995-02-21

Family

ID=12370608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3286094A Pending JPH0750487A (en) 1994-02-03 1994-02-03 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH0750487A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8093506B2 (en) 2006-12-21 2012-01-10 Ngk Spark Plug Co., Ltd. Multilayer wiring board and power supply structure to be embedded in multilayer wiring board

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181761A (en) * 1983-03-31 1984-10-16 Toshiba Electric Equip Corp Interphone device
JPS6084899A (en) * 1983-10-15 1985-05-14 松下電工株式会社 Method of producing multilayer circuit board
JPS60133033A (en) * 1983-12-20 1985-07-16 Mitsubishi Gas Chem Co Inc Manufacture of low-fluidity prepreg
JPS60133032A (en) * 1983-12-20 1985-07-16 Mitsubishi Gas Chem Co Inc Manufacture of low-fluidity prepreg
JPS60240741A (en) * 1984-05-14 1985-11-29 Mitsubishi Gas Chem Co Inc Preparation of low-flow prepreg

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181761A (en) * 1983-03-31 1984-10-16 Toshiba Electric Equip Corp Interphone device
JPS6084899A (en) * 1983-10-15 1985-05-14 松下電工株式会社 Method of producing multilayer circuit board
JPS60133033A (en) * 1983-12-20 1985-07-16 Mitsubishi Gas Chem Co Inc Manufacture of low-fluidity prepreg
JPS60133032A (en) * 1983-12-20 1985-07-16 Mitsubishi Gas Chem Co Inc Manufacture of low-fluidity prepreg
JPS60240741A (en) * 1984-05-14 1985-11-29 Mitsubishi Gas Chem Co Inc Preparation of low-flow prepreg

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8093506B2 (en) 2006-12-21 2012-01-10 Ngk Spark Plug Co., Ltd. Multilayer wiring board and power supply structure to be embedded in multilayer wiring board

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