TWI581367B - Method for manufacturing semiconductor structure - Google Patents

Description

Semiconductor structure manufacturing method

The present invention relates to a method of fabricating a semiconductor structure, and more particularly to a method of fabricating a semiconductor structure that forms a layer of selectively grown material on the surface of the recess.

In current semiconductor processes, localized oxidation isolation (LOCOS) or shallow trench isolation (STI) methods are generally used to isolate components to avoid short-circuit phenomena caused by mutual interference between components. However, as the design and manufacturing line width of semiconductor wafers become finer, the pits, crystal defects, and bird's beak lengths generated in the LOCOS process are too long. The characteristics of the semiconductor wafer will be greatly affected. Moreover, since the field oxide layer produced by the LOCOS method occupies a large volume, it affects the integration of the entire semiconductor wafer. Therefore, in a submicron semiconductor process, a small size and improved semiconductor wafer shallow trench isolation process has become a widely used isolation technique.

In general, current methods of fabricating STIs include first making a trench between MOS components on the surface of the wafer. The dielectric material is then filled into the trench to create an electrically isolated structure. However, as the size of semiconductor components is increasingly shrinking to near physical limits, the size of the trenches is getting smaller and smaller, and the difficulty in filling dielectric materials is gradually increasing. Therefore, how to make a good appearance and performance of STI has become an urgent need for the industry to solve. important question.

In view of the above, it is an object of the present invention to provide a method for fabricating a semiconductor structure using a precursor material having a better hole filling capability and forming a layer of selectively grown material on the surface of the trench, particularly for forming shallow trench isolation. The structure of the ditch surface to solve the above problems.

In order to achieve the above object, in accordance with a preferred embodiment of the present invention, a method of fabricating a semiconductor structure is provided, comprising the following steps. First, a semiconductor substrate is provided and a patterned pad is formed over the semiconductor substrate to expose a portion of the semiconductor substrate. Next, the exposed semiconductor substrate is etched to form a trench. A layer of selectively growing material is selectively formed on the surface of the trench, and a dielectric material precursor is filled in the trench. Finally, a conversion process is performed to convert the dielectric material precursor into a dielectric material and simultaneously convert the layer of selectively grown material into an oxygen-containing amorphous material layer.

In summary, the present invention provides a method of fabricating a semiconductor structure that forms a layer of selectively grown material on the surface of the trench. A layer of selectively grown material has been formed on the surface of the trench prior to filling the precursor of the dielectric material into the trench. Therefore, in the subsequent conversion process, the oxygen atoms originating from the precursor of the dielectric material or the external environment can be completely consumed by the selective growth material layer without directly diffusing into the semiconductor substrate beside the trench, so that the active region The size does not change. In addition, since the oxygen-containing amorphous material layer has a function of buffering the stress between the dielectric material and the semiconductor substrate, it can also avoid the semiconductor. The substrate is subjected to unnecessary compressive stress.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

1 to 10 are schematic cross-sectional views showing a method of fabricating a semiconductor structure according to a preferred embodiment of the present invention. As shown in Figure 1. First, a semiconductor substrate 110 is provided having at least one active region 10 and at least one insulating region 20 defined therein as regions for providing electrical components and electrically insulating materials, respectively. Next, at least one pad layer 120 (or hard mask layer) is stacked in the active region 10 and the insulating region 20 on the semiconductor substrate 110 by a deposition process. In a subsequent process, the underlayer 120 can be patterned to define a pattern of trenches in the insulating region 20. According to a preferred embodiment of the present invention, the pad layer 120 may include an oxide pad layer 122 and a nitride pad layer 124 from bottom to top, but is not limited thereto. The semiconductor substrate 110 includes a germanium substrate, a germanium-containing substrate, a three-five-layer germanium substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on insulator. -insulator, SOI) A semiconductor substrate such as a substrate, but is not limited thereto.

Next, the pad layer 120 is patterned by a patterning process to form a patterned pad layer 120' as shown in FIG. 2 on the semiconductor substrate 110. For the sake of clarity, a method of fabricating the patterned pad layer 120' of this embodiment will be generally described below. As shown in Figure 1 and 2 As shown in the figure, first, a patterned photoresist (not shown) is formed on the underlayer 120 by means of photolithography to define the position at which the trench is to be formed below. Next, a patterned photoresist (not shown) is used as an etch mask, and the underlayer 120 in FIG. 1 is subjected to an etching process to form a patterned pad layer 120' as shown in FIG. Finally, the patterned photoresist (not shown) is removed to form a structure as shown in FIG. The patterned pad layer 120' may include a patterned oxide pad layer 122' and a patterned nitride pad layer 124' that may expose a portion of the semiconductor substrate 110 to define a location in the subsequent process where the trench is to be formed.

As shown in Figure 3. Next, at least one etching process, such as a dry etching process, is performed to transfer the pattern of the patterned pad layer 120' into the semiconductor substrate 110 to form a corresponding trench R pattern in the insulating region 20. It should be noted here that since the trench R is formed in the semiconductor substrate 110, it is preferable to expose an inner region of the semiconductor substrate 110, such as a single crystal region. Next, a patterned back layer 120' can be selectively subjected to a pull back to expose the semiconductor substrate 110 adjacent the opening of the trench R. By this retracting process, the interstitial ability of the precursor of the subsequent process dielectric material and the buffering effect when the subsequent dielectric material is over-etched can be assisted.

4 and 5 are schematic cross-sectional views showing a surface of a trench having a selective growth material layer or a deposition material layer, respectively, according to an embodiment of the present invention. As shown in FIG. 4, a selective growth process P1 is performed under the coverage of the patterned pad layer 120', and at least one selective growth material layer 130 is formed on the surface S of the trench R, for example, as a An amorphous material is preferably an amorphous material. More precisely, according to a preferred embodiment of the present invention, the selective growth material layer 130 can be regarded as a stress buffer layer and/or a sacrificial layer at the same time, which can be used as a buffer for subsequent process dielectric materials (Fig. In addition to the stress between the semi-substrate substrate 110, it may also consume active atoms, such as oxygen atoms, that diffuse from the dielectric material to the semiconductor substrate 110 during subsequent conversion processes, as will be described in more detail below. In addition, the selective growth process P1 described above preferably employs a co-flow deposition process or a cyclic deposition process to form the selective growth material layer 130. For a cyclic deposition process, for example, when the selective growth material layer 130 is made of amorphous germanium, the germanium source gas and the etching gas may be alternately introduced in an environment where the process temperature is lower than 500 degrees Celsius. In combination with the carrier gas, the cycle of multiple deposition and etching is repeated to have a thickness of preferably between 5 angstroms and 100 angstroms. Since the deposition rate of the amorphous germanium material on the surface S of the trench R (that is, the exposed surface of the semiconductor substrate 110) is greater than the deposition rate of the patterned pad layer 120', an amorphous germanium can be ensured by a periodic etching process. The material is selectively formed only in the trench R. The above-mentioned gas source gas includes silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ) or a halide thereof, and the etching gas contains chlorine gas (Cl ₂ ), hydrogen chloride (HCl) or other etching gas, carrier gas. Contains hydrogen (H ₂ ), argon (Ar) or other suitable inert gas. According to different process requirements, the surface of the selective growth material layer 130 and the semiconductor substrate 110 or the selective growth material layer 130 may further include a liner layer (not shown), such as an oxide layer and/or a nitrogen. The layer or the like can be used to buffer the difference or increase in adhesion between the selective growth material layer 130 and the semiconductor substrate 110, but is not limited thereto.

According to another embodiment of the present invention, as shown in FIG. 5, it is also possible to pass through a sink. The deposition process P1' forms a deposition material layer 132 which covers the surface S of the trench R and the surface of the patterned pad layer 120. However, it is worth noting that if the deposition material layer 132 covers both the surface S of the trench R and the surface of the patterned pad layer 120', it will be disadvantageous for the flatness of the dielectric material (not shown) in the subsequent trench R. Process. For example, a two-stage planarization process is required to remove the dielectric material and the deposited material layer 132, respectively. Therefore, it is preferable to form only the selective growth material layer 130 on the surface S of the trench R to have a structure as shown in FIG.

As shown in FIG. 6, a filling process is then performed to fill a dielectric material precursor 150 in the trench R. Due to the continued shrinkage of the semiconductor components, the aspect ratio of the trench R is continuously increased (for example, a trench having a depth of 3000 angstroms and an opening diameter of only 500 angstroms). Therefore, preferably, the dielectric material precursor 150 is preferably in a liquid state to have a better interstitial capacity. For example, a liquid dielectric material precursor 150 can be filled into the trench R by a fluid chemical vapor deposition (FCVD) process or a spin-on dielectric (SOD) process. According to the preferred embodiment, the dielectric material precursor 150 is preferably a liquid decylamine, such as trisilylamine (TSA), but is not limited thereto.

Next, a conversion process is performed to convert the dielectric material precursor into a dielectric material and simultaneously convert the layer of selectively grown material into an oxygen-containing amorphous material layer, the detailed steps of which are as follows. As shown in Figure 7, and with reference to Figure 6. A conversion process P2 is performed to convert the selective growth material layer 130 of FIG. 6 into the oxygen-containing amorphous material layer 140. The conversion process P2 may be a sub-step or a subsequent step of the fluid chemical vapor deposition process or a spin-coating dielectric layer process, which includes at least an oxidation process and a densification process. For example, for a fluid chemical vapor deposition process, after the liquid niobium nitride is filled into the trench R, an oxidation process can be successively performed to cause a liquid tantalum nitride to undergo a curing reaction. The bond of -Si-O-Si- is produced. Finally, a uniform densification process is performed to cause the cross-linked niobium nitride to react further and become a dense tantalum oxide structure. Wherein, the oxidation process and the densification process both include oxygen (O ₂ ), ozone (O ₃ ) or water vapor (H ₂ O), and the process temperatures thereof are between 500 ° C and 700 ° C and greater than 1000 ° C respectively. .

For the current technology, if the above conversion process is carried out, the oxygen atoms will continue to diffuse from the inside of the trench to the semiconductor substrate around the trench, which will reduce the range of the active region. In addition, when the dielectric material precursor is converted into a dielectric material by a conversion process, a compressive stress is generated on the semiconductor substrate around the trench due to a slight increase in volume. However, in accordance with a preferred embodiment of the present invention, a selective growth material layer 130 is present between the semiconductor substrate 110 and the dielectric material precursor 150, which can react with oxygen atoms to prevent further diffusion of oxygen atoms. Still as shown in FIGS. 6 and 7, for example, when the selective growth material layer 130 is a polycrystalline germanium material, it can react with oxygen atoms to form cerium oxide, so that the converted oxygen-containing amorphous material layer 140 The composition comprises amorphous germanium and/or germanium oxide. The oxygen content in the oxygen-containing amorphous material layer 140 has a gradient distribution. Further, the gradient distribution is reduced from the contact surface S1 of the dielectric material 160 and the oxygen-containing amorphous material layer 140 to the contact surface S2 of the oxygen-containing amorphous material layer 140 and the trench R. This feature is illustrated in Figure 8, and is detailed below.

Fig. 8 is a graph showing the oxygen content as a function of position along the line I-I' in Fig. 7. In Fig. 8, D1 corresponds to C ₀ and D2 corresponds to C ₁ , wherein D1 represents a position in the oxygen-containing amorphous material layer at the contact surface S1 or adjacent to the contact surface S1, and D2 represents oxygen. In the amorphous material layer, at the contact surface S2 or adjacent to the contact surface S2; C ₁ and C ₀ respectively represent an oxygen content in the oxygen-containing amorphous material layer, preferably, C ₁ ≧C ₀ ≧0 And t ₁ , t ₂ , and t ₃ respectively represent curve distributions at different conversion times, preferably 0 < t ₁ < t ₂ < t ₃ . As shown in Figure 8, the reference is shown in Figure 7. After a certain conversion time t ₁ , part of the polysilicon material reacts with active atoms, such as oxygen atoms, to form cerium oxide, so that the oxygen content in the oxygen-containing amorphous material layer 140 exhibits a gradient distribution, and The gradient distribution decreases from the contact surface S1 of the dielectric material 160 to the oxygen-containing amorphous material layer 140 to the contact surface S2 of the oxygen-containing amorphous material layer 140 and the trench R. More specifically, the ratio of cerium oxide/polycrystalline germanium near the contact surface S1 will be greater than the ratio of cerium oxide/polycrystalline germanium near the contact surface S2. And as the conversion time continues to increase, for example, from t ₂ to t ₃ , the oxygen content between D1 and D2 in the oxygen-containing amorphous material layer 140 gradually increases, that is, there are more amorphous germanium. The material reacts to yttrium oxide. In accordance with a preferred embodiment of the present invention, preferably, the oxygen atoms are fully reacted prior to diffusion to the contact surface S2 and thus do not diffuse into the semiconductor substrate 110 adjacent the contact surface S2. If a conversion time is sufficiently long, the oxygen content corresponding to the relationship between D1 and D2 in the oxygen-containing amorphous material layer 140 may also reach the concentration of C1, that is, in the oxygen-containing amorphous material layer 140. All selective growth enthalpy is reacted to cerium oxide, but is not limited thereto. Through this reaction mechanism, the semiconductor substrate 110 located in the active region is not degraded by the implementation of the conversion process P2. It should also be noted that since the selective growth material layer 130 is a loose structure, even if the oxygen-containing amorphous material layer 140 is formed, it does not cause unnecessary stress on the active region.

Subsequently, the dielectric material 160 is planarized until the patterned pad layer 120' is exposed to form a planarized dielectric material 160a and a planarized patterned pad layer 120' as shown in FIG. It should be noted that, according to a preferred embodiment of the present invention, since the surface of the patterned pad layer 120' is not covered by the selective growth material layer (not shown), the planarization process can be continued. Until the surface of the patterned pad layer 120' is exposed. That is, through the preferred embodiment of the present invention, a one-time polishing process can be employed on the dielectric material 160 without the need to remove the dielectric material 160 and the selectively grown material layer in sections.

Thereafter, the patterned pad layer 120' is removed, and a shallow trench isolation structure G as shown in Fig. 10 can be formed in the insulating region 20. The shallow trench isolation structure G includes a dielectric material 160a and an oxygen-containing amorphous material layer 140. Then, a semiconductor process such as a transistor in the active region 10 can be performed. This semiconductor process is well known to those of ordinary skill in the art and will not be described again.

In summary, the present invention provides a method of fabricating a semiconductor structure that forms a layer of selective growth material 130 on the surface of the trench R. Since the surface R of the trench R has formed a layer of selective growth material 130 before the dielectric material precursor 150 is filled into the trench R, in the subsequent conversion process P2, it is derived from the dielectric material precursor 150 or the outside. An active atom of the environment, such as an oxygen atom, can be selectively grown 130 is completely consumed and converted into an oxygen-containing amorphous material layer 140 without directly diffusing into the semiconductor substrate 110 beside the trench R, so that the extent of the active region does not change. In addition, since the oxygen-containing amorphous material layer 140 has the function of buffering the stress between the dielectric material 160 and the semiconductor substrate 110, the semiconductor substrate 110 can be prevented from withstanding unnecessary compressive stress, thereby enhancing the carrier migration of the corresponding transistor element. rate.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Active area

20‧‧‧Insulated area

110‧‧‧Semiconductor substrate

120‧‧‧ cushion

122‧‧‧Oxide cushion

124‧‧‧Nitrided mat

120’‧‧‧ patterned cushion

122'‧‧‧ patterned oxidized cushion

124'‧‧‧ patterned nitride pad

130‧‧‧Selective growth material layer

132‧‧‧layer of deposited material

140‧‧‧Oxygen-containing amorphous material layer

150‧‧‧ dielectric material precursor

160‧‧‧ dielectric materials

160a‧‧‧ dielectric materials

G‧‧‧Shallow trench isolation structure

P1'‧‧‧ deposition process

P2‧‧‧ conversion process

R‧‧‧ Ditch

S‧‧‧ surface

S1, S2‧‧‧ contact surface

P1‧‧‧Selective Growth Process

1 to 10 are schematic cross-sectional views showing a method of fabricating a semiconductor structure according to an embodiment of the invention.

110‧‧‧Semiconductor substrate

120’‧‧‧ patterned cushion

122'‧‧‧ patterned oxidized cushion

124'‧‧‧ patterned nitride pad

130‧‧‧Selective growth material layer

150‧‧‧ dielectric material precursor

R‧‧‧ Ditch

S‧‧‧ surface

Claims (17)

A method of fabricating a semiconductor structure, comprising: providing a semiconductor substrate; forming a patterned pad on the semiconductor substrate to expose a portion of the semiconductor substrate; etching the exposed semiconductor substrate to form a trench; Forming a selective growth material layer on the surface of the trench; filling a dielectric material precursor into the trench; and performing a conversion process to convert the dielectric material precursor into a dielectric material and simultaneously selecting the selectivity Converting the growth material layer into an oxygen-containing amorphous material layer, wherein after the conversion process, the oxygen content in the oxygen-containing amorphous material layer is in a gradient distribution, and the oxygen content is from the dielectric material and the The contact of the oxygen-containing amorphous material layer decreases toward the contact surface of the trench and the oxygen-containing amorphous material layer. The method of fabricating a semiconductor structure according to claim 1, wherein the selective growth material layer is located only on the surface of the trench. The method of fabricating a semiconductor structure according to claim 1, wherein the process of forming the selective growth material layer comprises a selective growth process. The method of fabricating a semiconductor structure according to claim 1, wherein the process of forming the selective growth material layer comprises a co-flow deposition process or a cyclic deposition process. The method of fabricating the semiconductor process of claim 1, wherein the process temperature for forming the selective growth material layer is less than 500 degrees Celsius (° C.). The method of fabricating a semiconductor structure according to claim 1, wherein the selective growth material layer is an amorphous germanium material layer. The method of fabricating a semiconductor structure according to claim 1, wherein the selective growth material layer has a thickness of from 5 angstroms to 100 angstroms. The method for fabricating a semiconductor structure according to claim 1, wherein before the forming the selective growth material layer, a pull back process is performed on the patterned pad layer. The method of fabricating a semiconductor structure according to claim 1, wherein before forming the selective growth material layer, forming a liner layer on the surface of the trench. The method of fabricating a semiconductor structure according to claim 1, wherein the dielectric material precursor comprises trisilylamine (TSA). The method for fabricating a semiconductor process according to claim 1, wherein the process of filling the precursor of the dielectric material is a flow chemical vapor deposition (FCVD) process or a spin coating process. Electric layer (spin-on Dielectric, SOD) process. The method of fabricating a semiconductor structure according to claim 1, wherein the conversion process comprises an oxidation process. The method of fabricating a semiconductor structure according to claim 12, wherein the oxidizing process comprises introducing oxygen, ozone or water vapor. The method of fabricating a semiconductor structure according to claim 1, wherein the conversion process comprises a uniform densification process for densifying the dielectric material and the oxygen-containing amorphous material layer. The method for fabricating a semiconductor structure according to claim 1, wherein the conversion process has a process temperature of 500 ° C to 700 ° C. The method for fabricating a semiconductor structure according to claim 1, after performing the conversion process, further comprising: performing a planarization process to remove the dielectric material outside the trench. The method for fabricating a semiconductor structure according to claim 1, wherein the composition of the oxygen-containing amorphous material layer comprises amorphous germanium and germanium oxide.