CN103515285B - Semiconductor structure and its manufacture craft - Google Patents
Semiconductor structure and its manufacture craft Download PDFInfo
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- CN103515285B CN103515285B CN201210223143.XA CN201210223143A CN103515285B CN 103515285 B CN103515285 B CN 103515285B CN 201210223143 A CN201210223143 A CN 201210223143A CN 103515285 B CN103515285 B CN 103515285B
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- silicon
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- manufacture craft
- rich layer
- fabrication process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The present invention discloses a kind of semiconductor structure and its manufacture craft, and the semiconductor structure is located in a groove of a substrate.Semiconductor structure includes a laying, a silicon-rich layer and a packing material.Laying is located at the surface of groove.Silicon-rich layer is located on laying.Packing material is located in silicon-rich layer and fills up groove.In addition, the present invention it is also proposed that a kind of semiconductor fabrication process forming foregoing semiconductor structure.
Description
Technical field
A silicon-rich layer is formed in recessed the present invention relates to a kind of semiconductor structure and its manufacture craft, and more particularly to one kind
The semiconductor structure and its manufacture craft of rooved face.
Background technology
In current semiconductor fabrication process, typically zone oxidation method (localized oxidation are used
Isolation, LOCOS) or shallow isolating trough (shallow trench isolation, STI) method enter between units
Isolation, produce short circuit phenomenon to avoid interelement from interfering.However as the design and manufacture line width of semiconductor chip
When becoming more and more thinner, caused pit (pits) in LOCOS manufacture crafts, crystal defect (crystal defect) and
The shortcomings of beak (bird ' s beak) length is long, it just will significantly influence the characteristic of semiconductor chip, and LOCOS methods institute
Caused field oxide occupies larger volume and can influence the integrated level (integration) of whole semiconductor chip.Therefore
In secondary micron (submicron) semiconductor fabrication process, size is smaller, the product of semiconductor chip can be improved into degree shallow ridges every
Turn into the isolation technology being widely used recently then from (shallow trench isolation, abbreviation STI) manufacture craft.
Typical STI preparation method is each MOS interelements one groove of making in chip surface, and inserts dielectric material
To produce the effect electrically isolated.Dielectric material is generally silica.When forming silica, the step of to form silica
Or the high temperature of subsequent manufacturing processes can be such that oxygen diffuses to by groove in the silicon base of the active region of transistor to be formed, and by part
Silicon base aoxidize to form silica.In this way, the size of each shallow trench isolation structure not only can not be accurately controlled, and equivalent to
The volume increase of the shallow trench isolation structure formed, and reduce the silicon base of active region.However, the size with semiconductor element
For increasingly micro to close to physics limit, different size of shallow trench isolation structure and active region have had a strong impact on the electrical of element thereon
Performance and manufacture craft quality.
The content of the invention
It is an object of the invention to provide a kind of semiconductor structure and its manufacture craft, and it forms a silicon-rich layer in groove table
Face, particularly to form the groove surfaces of shallow trench isolation structure, to solve the above problems.
For the above-mentioned purpose, the present invention provides a kind of semiconductor structure and is located in a groove of a substrate.Semiconductor structure
Include a laying, a silicon-rich layer and a packing material.Laying is located at the surface of groove.Silicon-rich layer is located at laying
On.Packing material is located in silicon-rich layer and fills up groove.
The present invention also provides a kind of semiconductor fabrication process, includes following step.First, a groove is formed in a substrate
In.Then, the surface of laying covering groove is formed.Continue, form a silicon-rich layer on laying.Followed by, a silicon is inserted
Nitride is in groove.Then, a conversion manufacture craft is carried out, silicon nitride is changed into silicon monoxide, and at least oxidation section
Divide silicon-rich layer.
Based on above-mentioned, a kind of semiconductor structure of present invention proposition and its manufacture craft, it forms a silicon-rich layer in groove table
Face, particularly to form the groove surfaces of shallow trench isolation structure, silicon nitride is then filled with groove, then this silicon is nitrogenized
Thing is converted into packing material to be used as the insulation between active region.In this way, due to the present invention before silicon nitride is inserted
Silicon-rich layer is initially formed in groove surfaces, is to be diffused to the composition such as oxygen atom that can prevent from being passed through in conversion process by groove
Substrate in, its volume for occupying the substrate of part active region and expanding formed shallow trench isolation structure.
Brief description of the drawings
Fig. 1-Figure 10 is the diagrammatic cross-section of the semiconductor fabrication process of one embodiment of the invention.
Main element symbol description
110：Substrate
120：Hard mask layer
122：Pad oxide
124：Pad nitration case
120’：The hard mask layer of patterning
122’：The pad oxide of patterning
124’：The pad nitration case of patterning
130：Laying
130a：The laying of planarization
140、140a：Silicon-rich layer
140b：The silicon-rich layer of planarization
150：Silicon nitride
160：Packing material
160a：The packing material of planarization
A、B：Active region
G：Shallow trench isolation structure
P1：Convert manufacture craft
P2：It is densified manufacture craft
R：Groove
S：Surface
S1、S2：Contact surface
Embodiment
Fig. 1-Figure 10 illustrates the diagrammatic cross-section of the semiconductor fabrication process of one embodiment of the invention.As shown in Figure 1-Figure 3,
A substrate 110 with a recess R is provided.Specifically, as shown in Figure 1, there is provided substrate 110, wherein substrate 110 are, for example, one
Silicon base, one are containing silicon base, an III-V covers silicon base (such as GaN-on-silicon), a graphene covers silicon base
Or the semiconductor base such as silicon-coated insulated (silicon-on-insulator, a SOI) substrate (graphene-on-silicon).
Then, a hard mask layer 120 is formed in substrate 110.In the present embodiment, hard mask layer 120 can from bottom to top include a pad
Oxide layer 122 and one pads nitration case 124 in substrate 110, but the present invention is not limited.
As shown in Fig. 2 hard mask layer 120 is patterned to form the hard mask layer 120 ' of a patterning, it includes a figure
The pad nitration case 124 ' of the pad oxide 122 ' of case and a patterning.The method for forming the hard mask layer 120 ' of patterning can
For example,：First with the method for photoetching, a photoresist patterned is formed（Do not illustrate）In on hard mask layer 120, this figure
The photoresist of case（Do not illustrate）Pattern then define below correspond to recess R to be formed position.Then it is etched,
And with the photoresist of patterning（Do not illustrate）Pattern the hard mask layer 120 ' of patterning is formed as mask.Then exist
The photoresist of selective removal patterning（Do not illustrate）Afterwards, as shown in figure 3, the methods of recycling etching, will be patterned into
The pattern of hard mask layer 120 ' is transferred to substrate 110, to form recess R in substrate 110.
As shown in figure 4, form the surface S that a laying 130 covers substrate 110, particularly recess R comprehensively.Laying 130
It may be, for example, an oxide layer and/or a nitration case etc., for example can be produced via original place steam（(in situ steam
generation,ISSG）Manufacture craft is formed, but the present invention is not limited.
As shown in figure 5, a silicon-rich layer 140 is formed on laying 130.In the present embodiment, silicon-rich layer 140 is one siliceous
Layer.But in other embodiments, silicon-rich layer 140 or a silicon nitride layer, one silica layer, a silicon oxynitride layer or a nitridation
Carbon silicon layer etc. is rich in the combination materials layer of silicon composition, that is, in the plurality of combination materials layer, containing fixed than composition less than normal
Oxygen ratio, such as if silicon oxide layer, then its molecular formula is SiOx, and x is less than 2.Furthermore silicon-rich layer 140 can be by plasma
Body assistant chemical vapor deposition（Plasma Enhanced Chemical Vapor Deposition,PECVD）Manufacture craft or
Ald（Atomic Layer Deposition,ALD）The formation such as manufacture craft, silicon-rich layer is formed using which kind of mode
Depending on 140 are the effect by silicon-rich layer 140 to be formed.
The purpose that the present invention forms silicon-rich layer 140 is to be formed to prevent from being subsequently stuffed into recess R in silicon-rich layer 140
Packing material（Do not illustrate）In the composition that is either passed through in subsequent manufacturing processes of composition, such as oxygen diffused to by recess R
Substrate 110 in, occupy active region A, B of the semiconductor structures such as part transistor to be formed and expand formed shallow isolating trough
Structure（Do not illustrate）Volume.It is therefore prevented that the method for the composition of packing material or subsequent manufacturing processes pollution substrate 110 can example
Such as：（1）The composition of the packing material or subsequent manufacturing processes is absorbed with silicon-rich layer 140, such as the reaction source of silicon is provided, with consumption
Oxygen atom in the packing material, and then prevent the oxygen composition of packing material or subsequent manufacturing processes from entering in substrate 110.Now
Silicon-rich layer 140, which is preferably one, has structure loosely, can have sufficient space absorb packing material or subsequent manufacturing processes into
Point, now preferably it is applicable with plasma auxiliary chemical vapor deposition（Plasma Enhanced Chemical Vapor
Deposition,PECVD）Manufacture craft forms silicon-rich layer 140.Or（2）Directly stop the packing material or subsequently make work
The composition of skill enters in silicon-rich layer 140.Silicon-rich layer 140 now, which is preferably one, has finer and close structure, can effectively stop and fill out
The composition for filling material or subsequent manufacturing processes enters in silicon-rich layer 140, and therefore silicon-rich layer 140 is preferably applicable with ald
（Atomic Layer Deposition,ALD）Manufacture craft is formed.
In addition, silicon-rich layer 140 is preferably formed on laying 130, because silicon-rich layer 140 is rich in silicon composition and general substrate
110 be also silicon base, and laying 130 can isolate the two, formed silicon-rich layer 140 is had preferable structure, and laying
130 can further stop that the composition in packing material enters in substrate 110.Still further, when silicon-rich layer 140 stress compared with
When big, for example, one has heavily stressed silicon-rich silicon nitride layer, then laying 130 can be used as stress-buffer layer to prevent Silicon-rich
Layer 140 peels off.
As shown in fig. 6, an inclusion 150 is inserted in recess R.In the present embodiment, inclusion 150 nitrogenizes for a silicon
Thing；But in other embodiments, inclusion 150 or a Si oxide etc., the present invention is not limited.Inclusion 150 1
As be in a liquid state to adequately fill up recess R, wherein inclusion 150 is for example comprising trimethyl silicane alkanamine（trisilylamine,TSA）,
But the present invention is not limited.Because after semiconductor element micro, the depth of recess R is up to such as 3000 angstroms
(angstrom), opening diameter only has the size of 500 angstroms (angstrom), is intended to etch the groove of such high-aspect-ratio and makes its tool
There is flattened section structure wide at the top and narrow at the bottom to be actually not easy, be when inclusion 150 is in a liquid state shape, then completely can flow into and fill up
Has the recess R of high-aspect-ratio.Certainly, in other embodiments, inclusion 150 also can be in other physical property states.
Then as shown in fig. 7, carrying out a conversion manufacture craft P1, inclusion 150 is changed into a packing material 160, with
It is used between two active region A, B of the semiconductor elements such as transistor to be formed as insulation.In the present embodiment, packing material
160 be silicon monoxide, and when converting inclusion 150, this conversion manufacture craft P1 can at least oxidized portion silicon-rich layer 140,
And form an oxygen containing silicon-rich layer 140a.Because the silicon-rich layer 140 of the present embodiment is a silicrete, therefore preferably implement state one
In sample, silicon-rich layer 140 can be fully converted to one silica layer.In this way, silicon-rich layer 140 can convert in the lump with packing material 160
For silica, to be used as insulation, but the present invention is not limited.In other embodiments, when silicon-rich layer 140 is a silicon nitride
Layer, then oxygen containing silicon-rich layer 140a is a silicon oxynitride layer；When silicon-rich layer 140 is a carbonitride silicon layer, then oxygen containing silicon-rich layer
140a is a nitrogen oxidation carbon silicon layer.In the present embodiment, it is an oxidation manufacture craft to convert manufacture craft P1, but the present invention not with
This is limited.Specifically, oxidation manufacture craft can include and be passed directly into oxygen, ozone or vapor etc..Convert manufacture craft P1
Manufacture craft temperature be such as 500 DEG C~700 DEG C, so that inclusion 150 fully is changed into packing material 160.Certainly, filling out
Enter during thing 150 changes into packing material 160, have the silicon-rich layer 140 of part also while be oxidized and formed oxygen containing
Silicon-rich layer 140a.In one embodiment, oxygen containing silicon-rich layer 140a oxygen content is distributed in a gradient.For example, oxygen containing Silicon-rich
Layer 140a oxygen content is in one from packing material 160 and oxygen containing silicon-rich layer 140a contact surface S1 to oxygen containing silicon-rich layer 140a
It is distributed with the gradient that the contact surface S2 of laying 130 successively decreases.Oxygen containing silicon-rich layer 140a oxygen content number is then depending on being passed through
Depending on the concentration of oxygen or the structural compactness of silicon-rich layer 140 etc..Brought forward, which is stated, to be sayed, when silicon-rich layer 140 is by plasmaassisted
Chemical vapor deposition（Plasma Enhanced Chemical Vapor Deposition,PECVD）Manufacture craft is formed, then
With more loose structure, and more oxygen atom can be adsorbed, therefore oxygen containing silicon-rich layer 140a oxygen content is more；Work as Silicon-rich
Layer 140 is by ald（Atomic Layer Deposition,ALD）Manufacture craft is formed, then with comparatively dense knot
Structure, the oxygen atom of majority is barred from outside it by it, is located therein less oxygen atom, therefore oxygen containing silicon-rich layer 140a contains
Oxygen amount is less.
As shown in figure 8, a densification manufacture craft P2 is optionally carried out again, to be further densified packing material
160 and oxygen containing silicon-rich layer 140a.Densification manufacture craft P2 can include a hot manufacture craft or an oxygen-containing manufacture craft etc..
Densification manufacture craft P2 manufacture craft temperature is more preferably greater than 1000 DEG C, to reach significant fine and close effect.It is preferable one
In embodiment, densification manufacture craft P2 manufacture craft temperature is 1100 DEG C.Similar, silicon-rich layer 140a of the invention is same
Sample can be used to absorb or stop this densification manufacture craft P2 in itself or the oxygen atom by its high-temperature activation.
Then, planarizing fill material 160, oxygen containing silicon-rich layer 140a and laying 130, and as shown in figure 9, being formed
One planarization packing material 160a, one planarization silicon-rich layer 140b and one planarization laying 130a, be allowed to firmly
Mask layer 120 ' flushes.Afterwards, hard mask layer 120 ' is removed, as shown in Figure 10, forms a shallow trench isolation structure G.Then, can enter
The semiconductor fabrication process such as the transistor in row active region A, B.This semiconductor fabrication process for this area usual skill institute
It is known therefore repeat no more.
Hold, the present invention first inserts inclusion 150, then carries out converting manufacture craft P1 to form packing material 160 and extremely
The step of silicon-rich layer 140 of few oxidized portion, can apply first-class body chemical vapor phase growing（flowable chemical vapor
deposition,FCVD）Manufacture craft or a rotary coating dielectric layer（spin-on dielectric,SOD）Manufacture craft
Step, but the present invention is not limited.
In summary, the present invention proposes a kind of semiconductor structure and its manufacture craft, and it forms a silicon-rich layer in groove table
Face, particularly to form the groove surfaces of shallow trench isolation structure, silicon nitride is then filled with groove, then this silicon is nitrogenized
Thing is converted into packing material to be used as the insulation between two active regions.In this way, because the present invention is before silicon nitride is inserted
A silicon-rich layer has been initially formed in groove surfaces, be with the composition either packing material that can prevent from being passed through in conversion process in itself
Composition, such as oxygen atom diffuses in the substrate by groove, occupies the substrate of part active region and expand formed shallow ridges
The volume of isolation structure.Still further, silicon-rich layer can include a silicrete, a silicon nitride layer, one silica layer, a nitrogen oxygen
SiClx layer or a carbonitride silicon layer, and silicon-rich layer can be by plasma auxiliary chemical vapor deposition（Plasma Enhanced
Chemical Vapor Deposition,PECVD）Manufacture craft or ald（Atomic Layer Deposition,
ALD）The formation such as manufacture craft.
Presently preferred embodiments of the present invention is the foregoing is only, all equivalent changes done according to the claims in the present invention are with repairing
Decorations, it should all belong to the covering scope of the present invention.
Claims (14)
1. a kind of semiconductor structure, in a groove of a substrate, the semiconductor structure includes：
Laying, positioned at the surface of the groove；
Silicon-rich layer, on the laying；And
Packing material, in the silicon-rich layer and fill up the groove；
Wherein the silicon-rich layer includes oxygen containing silicon-rich layer；
And the oxygen content distribution gradient of the oxygen containing silicon-rich layer；
Wherein the silicon-rich layer includes silicrete, silicon nitride layer, silicon oxide layer, silicon oxynitride layer or carbonitride silicon layer；
Wherein gradient distribution is contact of the contact towards the silicon-rich layer with the laying from the packing material with the silicon-rich layer
Successively decrease in face.
2. semiconductor structure as claimed in claim 1, the wherein laying include oxide layer.
3. semiconductor structure as claimed in claim 1, the wherein packing material include silica.
4. a kind of semiconductor fabrication process, includes：
A groove is formed in a substrate；
Form the surface that a laying covers the groove；
A silicon-rich layer is formed on the laying；
A silicon nitride is inserted in the groove；And
A conversion manufacture craft is carried out, the silicon nitride is changed into silicon monoxide, and at least oxidized portion silicon-rich layer and shape
Into oxygen containing silicon-rich layer, the oxygen content distribution gradient of the oxygen containing silicon-rich layer；
Wherein the silicon-rich layer includes silicrete, silicon nitride layer, silicon oxide layer, silicon oxynitride layer or carbonitride silicon layer；
Wherein gradient distribution is from contact of the silica with the silicon-rich layer towards the silicon-rich layer and the contact surface of the laying
Successively decrease.
5. semiconductor fabrication process as claimed in claim 4, the wherein laying include oxide layer.
6. semiconductor fabrication process as claimed in claim 4, the wherein silicon-rich layer are included with plasma-enhanced CVD
Deposit (Plasma Enhanced Chemical Vapor Deposition, PECVD) manufacture craft or ald
(Atomic Layer Deposition, ALD) manufacture craft is formed.
7. the manufacture craft temperature of semiconductor fabrication process as claimed in claim 4, wherein the conversion manufacture craft is 500 DEG C
~700 DEG C.
8. semiconductor fabrication process as claimed in claim 4, wherein the conversion manufacture craft include an oxidation manufacture craft.
9. semiconductor fabrication process as claimed in claim 8, wherein the oxidation manufacture craft include and are passed through oxygen, ozone or water
Steam.
10. semiconductor fabrication process as claimed in claim 4, after the conversion manufacture craft is carried out, also include：
A densification manufacture craft is carried out, to be densified the silica and the silicon-rich layer.
11. the manufacture craft temperature of semiconductor fabrication process as claimed in claim 10, wherein the densification manufacture craft is high
In 1000 DEG C.
12. the manufacture craft temperature of semiconductor fabrication process as claimed in claim 11, wherein the densification manufacture craft is
1100℃。
13. semiconductor fabrication process as claimed in claim 4, the wherein silicon nitride include trimethyl silicane alkanamine
(trisilylamine,TSA)。
14. semiconductor fabrication process as claimed in claim 4, work is made wherein inserting the silicon nitride and carrying out the conversion
The step of skill is first-class body chemical vapor phase growing (flowable chemical vapordeposition, FCVD) manufacture craft
Or the step of rotary coating dielectric layer (spin-on dielectric, SOD) manufacture craft.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210223143.XA CN103515285B (en) | 2012-06-28 | 2012-06-28 | Semiconductor structure and its manufacture craft |
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| CN201210223143.XA CN103515285B (en) | 2012-06-28 | 2012-06-28 | Semiconductor structure and its manufacture craft |
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| CN103515285A CN103515285A (en) | 2014-01-15 |
| CN103515285B true CN103515285B (en) | 2018-03-27 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6576530B1 (en) * | 2002-10-01 | 2003-06-10 | Nanya Technology Corporation | Method of fabricating shallow trench isolation |
| CN1534758A (en) * | 2003-04-02 | 2004-10-06 | 株式会社瑞萨科技 | Semiconductor device mfg. method |
| CN101528974A (en) * | 2006-10-16 | 2009-09-09 | 应用材料股份有限公司 | Formation of high quality dielectric films of silicon dioxide for sti: usage of different siloxane-based precursors for harp II-remote plasma enhanced deposition processes |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040005781A1 (en) * | 2002-07-02 | 2004-01-08 | Chartered Semiconductor Manufacturing Ltd. | HDP SRO liner for beyond 0.18 um STI gap-fill |
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- 2012-06-28 CN CN201210223143.XA patent/CN103515285B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6576530B1 (en) * | 2002-10-01 | 2003-06-10 | Nanya Technology Corporation | Method of fabricating shallow trench isolation |
| CN1534758A (en) * | 2003-04-02 | 2004-10-06 | 株式会社瑞萨科技 | Semiconductor device mfg. method |
| CN101528974A (en) * | 2006-10-16 | 2009-09-09 | 应用材料股份有限公司 | Formation of high quality dielectric films of silicon dioxide for sti: usage of different siloxane-based precursors for harp II-remote plasma enhanced deposition processes |
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| CN103515285A (en) | 2014-01-15 |
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