CN103515285A - Semiconductor structure and manufacturing process thereof - Google Patents
Semiconductor structure and manufacturing process thereof Download PDFInfo
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- CN103515285A CN103515285A CN201210223143.XA CN201210223143A CN103515285A CN 103515285 A CN103515285 A CN 103515285A CN 201210223143 A CN201210223143 A CN 201210223143A CN 103515285 A CN103515285 A CN 103515285A
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- silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
Abstract
The invention discloses a semiconductor structure and manufacturing process thereof. The semiconductor structure is arranged in a groove formed in a substrate. The semiconductor structure comprises a pad layer, a silicon enrichment layer and a filling material, wherein the pad layer is arranged on the surface of the groove, the silicon enrichment layer is arranged on the pad layer, the filling material is arranged on the silicon enrichment layer, and the groove is filled up with the filling material. In addition, the invention further provides semiconductor manufacturing process which is used for manufacturing the semiconductor structure.
Description
Technical field
The present invention relates to a kind of semiconductor structure and manufacture craft thereof, and particularly relate to a kind of formation one silicon-rich layer in semiconductor structure and the manufacture craft thereof of groove surfaces.
Background technology
In current semiconductor fabrication process, general region oxidizing process (the localized oxidation isolation that adopts, LOCOS) or shallow isolating trough (shallow trench isolation, STI) method is carried out the isolation between element, to avoid the mutual interference of interelement phase, produces short circuit phenomenon.Yet along with the design of semiconductor chip is when manufacturing live width and become more and more thinner, the shortcoming such as the pit producing in LOCOS manufacture craft (pits), crystal defect (crystal defect) and beak (bird ' s beak) length is long, just the characteristic of semiconductor chip will be affected significantly, and the field oxide that LOCOS method produces occupies the integrated level (integration) that can affect whole semiconductor chip compared with large volume.Therefore in the semiconductor fabrication process of inferior micron (submicron), size degree shallow isolating trough (shallow trench isolation the is called for short STI) manufacture craft of amassing into less, that can improve semiconductor chip becomes the isolation technology being recently widely used then.
The manufacture method of typical STI is to make a groove at each MOS interelement of chip surface, and inserts dielectric material to produce the effect of electrical isolation.Dielectric material is generally silica.When forming silica, in order to form the step of silica or the high temperature of follow-up manufacture craft, can make oxygen diffuse to the other wish of groove to form in the silicon base of transistorized active region, and the silicon base oxidation of part is formed to silica.So, not only cannot accurately control the size of each shallow trench isolation structure, and be equivalent to the volume increase of formed shallow trench isolation structure, and reduce the silicon base of active region.Yet, along with the size of semiconductor element day by day micro to approaching physics limit, electrical performance and manufacture craft quality that the shallow trench isolation structures of different sizes and active region have had a strong impact on element on it.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor structure and manufacture craft thereof, it forms a silicon-rich layer in groove surfaces, particularly in order to form the groove surfaces of shallow trench isolation structure, to address the above problem.
For reaching above-mentioned purpose, the invention provides the groove that a kind of semiconductor structure is arranged in a substrate.Semiconductor structure includes a laying, a silicon-rich layer and a packing material.Laying is positioned at the surface of groove.Silicon-rich layer is positioned on laying.Packing material is positioned in silicon-rich layer and fills up groove.
The present invention also provides a kind of semiconductor fabrication process, includes following step.First, form a groove in a substrate.Then, form the surface that a laying covers groove.Continue, form a silicon-rich layer on laying.Then, insert a silicon nitride in groove.Then, carry out a conversion manufacture craft, silicon nitride is changed into silicon monoxide, and oxidized portion silicon-rich layer at least.
Based on above-mentioned, the present invention proposes a kind of semiconductor structure and manufacture craft thereof, it forms a silicon-rich layer in groove surfaces, particularly in order to form the groove surfaces of shallow trench isolation structure, then insert silicon nitride in groove, then this silicon nitride is converted into packing material usings and use as insulation between active region.So, because the present invention first formed silicon-rich layer in groove surfaces before inserting silicon nitride, be composition can prevent from conversion process being passed into for example oxygen atom diffuse in the other substrate of groove, the volume that it occupies the substrate of part active region and expands formed shallow trench isolation structure.
Accompanying drawing explanation
Fig. 1-Figure 10 is the generalized section of the semiconductor fabrication process of one embodiment of the invention.
Main element symbol description
110: substrate
120: hard mask layer
122: pad oxide
124: pad nitration case
120 ': the hard mask layer of patterning
122 ': the pad oxide of patterning
124 ': the pad nitration case of patterning
130: laying
130a: the laying of planarization
140,140a: silicon-rich layer
140b: the silicon-rich layer of planarization
150: silicon nitride
160: packing material
160a: the packing material of planarization
A, B: active region
G: shallow trench isolation structure
P1: transform manufacture craft
P2: densification manufacture craft
R: groove
S: surface
S1, S2: contact-making surface
Embodiment
Fig. 1-Figure 10 illustrates the generalized section of the semiconductor fabrication process of one embodiment of the invention.As shown in Figure 1-Figure 3, provide a substrate 110 with a recess R.Specifically, as shown in Figure 1, substrate 110 is provided, wherein substrate 110 be for example a silicon base, one containing silicon base, a San Wu family cover silicon base (for example GaN-on-silicon), a Graphene covers the semiconductor bases such as silicon base (graphene-on-silicon) or one silicon-coated insulated (silicon-on-insulator, SOI) substrate.Then, form a hard mask layer 120 in substrate 110.In the present embodiment, hard mask layer 120 from bottom to top can comprise a pad oxide 122 and and pad nitration case 124 in substrate 110, but the present invention is not as limit.
As shown in Figure 2, by hard mask layer 120 patternings to form the hard mask layer 120 ' of a patterning, the pad nitration case 124 ' of the pad oxide 122 ' that it comprises a patterning and a patterning.The method that forms the hard mask layer 120 ' of patterning can be for example: the method for first utilizing photoetching, form the photoresist (not illustrating) of a patterning on hard mask layer 120, the pattern of the photoresist of this patterning (not illustrating) defines the position that its corresponding wish in below forms recess R.Then carry out etching, and be used as with the pattern of the photoresist (not illustrating) of patterning the hard mask layer 120 ' that mask forms patterning.Then after the photoresist (not illustrating) of selective removal patterning, as shown in Figure 3, the methods such as recycling etching, by the design transfer of the hard mask layer 120 ' of patterning to substrate 110, to form recess R in substrate 110.
As shown in Figure 4, form a laying 130 and cover the surperficial S of substrate 110, particularly recess R comprehensively.Laying 130 can be such as being an oxide layer and/or a nitration case etc., can for example via original place steam, produce that ((in situ steam generation, ISSG) manufacture craft forms, but the present invention is not as limit.
As shown in Figure 5, form a silicon-rich layer 140 on laying 130.In the present embodiment, silicon-rich layer 140 is a silicrete.But in other embodiments, silicon-rich layer 140 also can be the combination materials layer that a silicon nitride layer, one silica layer, a silicon oxynitride layer or a carbonitride silicon layer etc. are rich in silicon composition, that is in the plurality of combination materials layer, contain the ratio lower than the normal fixed oxygen than forming, if silicon oxide layer for example, its molecular formula is SiOx, and x is less than 2.Moreover, silicon-rich layer 140 can be by plasma auxiliary chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) manufacture craft or ald (Atomic Layer Deposition, ALD) formation such as manufacture craft, adopting which kind of mode to form silicon-rich layer 140 is that the effect that forms silicon-rich layer 140 by wish is determined.
The object that the present invention forms silicon-rich layer 140 is for preventing that the follow-up recess R that fills in is formed at the composition passing in composition in the packing material (not illustrating) in silicon-rich layer 140 or follow-up manufacture craft, oxygen for example, diffuse in the other substrate 110 of recess R, occupy part wish and form active region A, the B of the semiconductor structures such as transistor and expand the volume of formed shallow trench isolation structure (not illustrating).Therefore, the composition that prevents packing material or follow-up manufacture craft pollutes the method for substrate 110 can be for example: (1) absorbs the composition of these packing materials or follow-up manufacture craft with silicon-rich layer 140, the reaction source of silicon is for example provided, to consume the oxygen atom in this packing material, and then prevent that the oxygen composition of packing material or follow-up manufacture craft from entering in substrate 110.Now silicon-rich layer 140 is preferably one and has looser structure, can there is sufficient space to absorb the composition of packing material or follow-up manufacture craft, now better applicable with plasma auxiliary chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) manufacture craft formation silicon-rich layer 140.Or (2) directly stop that the composition of this packing material or follow-up manufacture craft enters in silicon-rich layer 140.Silicon-rich layer 140 is now preferably one and has finer and close structure, the composition that can effectively stop packing material or follow-up manufacture craft enters in silicon-rich layer 140, and silicon-rich layer 140 so better being suitable for form with ald (Atomic Layer Deposition, ALD) manufacture craft.
In addition, silicon-rich layer 140 is better to be formed on laying 130, because silicon-rich layer 140 is rich in silicon composition and general substrate 110 is also silicon base, laying 130 can be isolated the two, make formed silicon-rich layer 140 there is preferably structure, and laying 130 can further stop that the composition in packing material enters in substrate 110.Further, when the stress of silicon-rich layer 140 is larger, for example, be one to there is heavily stressed silicon-rich silicon nitride layer, laying 130 can be used as stress-buffer layer and peels off with prevention silicon-rich layer 140.
As shown in Figure 6, insert thing 150 in recess R.In the present embodiment, inserting thing 150 is a silicon nitride; But in other embodiments, insert thing 150 and also can be a Si oxide etc., the present invention is not as limit.Insert thing 150 and be generally in a liquid state fully to fill up recess R, wherein insert thing 150 and for example comprise trimethyl silicane alkanamine (trisilylamine, TSA), but the present invention is not as limit.Because after semiconductor element micro, the degree of depth of recess R can reach for example 3000 dusts (angstrom), opening diameter only has the size of 500 dusts (angstrom), want the groove of etching high-aspect-ratio like this and make it there is flattened section structure wide at the top and narrow at the bottom real in being difficult for, with when inserting thing 150 and be in a liquid state shape, can complete inflow and fill up the recess R of tool high-aspect-ratio.Certainly, in other embodiments, insert thing 150 and also can be other physical property states.
Then as shown in Figure 7, carry out a conversion manufacture craft P1, will insert thing 150 and change into a packing material 160, to be positioned at wish, form two active region A of the semiconductor elements such as transistor, between B, be used as to insulate.In the present embodiment, packing material 160 is silicon monoxide, and when thing 150 is inserted in conversion, this transforms at least oxidized portion silicon-rich layer 140 of manufacture craft P1, and forms an oxygen containing silicon-rich layer 140a.Because the silicon-rich layer 140 of the present embodiment is a silicrete, therefore preferably implement in aspect one, silicon-rich layer 140 can be converted into one silica layer completely.So, silicon-rich layer 140 can be converted into silica in the lump with packing material 160, and with what be used as to insulate, but the present invention is not as limit.In other embodiments, when silicon-rich layer 140 is a silicon nitride layer, oxygen containing silicon-rich layer 140a is a silicon oxynitride layer; When silicon-rich layer 140 is a carbonitride silicon layer, oxygen containing silicon-rich layer 140a is a nitrogen carbonoxide silicon layer.In the present embodiment, transforming manufacture craft P1 is an oxidation manufacture craft, but the present invention is not as limit.Particularly, oxidation manufacture craft can comprise and directly passes into oxygen, ozone or steam etc.The manufacture craft temperature that transforms manufacture craft P1 is for example 500 ℃～700 ℃, fully will insert thing 150, changes into packing material 160.Certainly, change in the process of packing material 160 inserting thing 150, the silicon-rich layer 140 that has a part is also simultaneously oxidized and form oxygen containing silicon-rich layer 140a.In one embodiment, the oxygen content of oxygen containing silicon-rich layer 140a is a gradient distribution.For example, the oxygen content of oxygen containing silicon-rich layer 140a is the gradient distribution that a contact-making surface S1 from packing material 160 and oxygen containing silicon-rich layer 140a successively decreases to the contact-making surface S2 of oxygen containing silicon-rich layer 140a and laying 130.The oxygen content number of oxygen containing silicon-rich layer 140a is depending on the concentration of passed into oxygen or the structural compactness of silicon-rich layer 140 etc.Brought forward state say, when silicon-rich layer 140 is by plasma auxiliary chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) manufacture craft forms, there is comparatively loose structure, and can adsorb more oxygen atom, therefore the oxygen content of oxygen containing silicon-rich layer 140a is more; When silicon-rich layer 140 is by ald (Atomic Layer Deposition, ALD) manufacture craft forms, and has comparatively fine and close structure, and it is barred from most oxygen atoms outside it, less oxygen atom is positioned at wherein, therefore the oxygen content of oxygen containing silicon-rich layer 140a is less.
As shown in Figure 8, optionally carry out again a densification manufacture craft P2, with further densification packing material 160 and oxygen containing silicon-rich layer 140a.Densification manufacture craft P2 can comprise a hot manufacture craft or and contain oxygen manufacture craft etc.The manufacture craft temperature of densification manufacture craft P2 is better for 1000 ℃, to reach significant fine and close effect.In a preferred embodiment, the manufacture craft temperature of densification manufacture craft P2 is 1100 ℃.Similar, silicon-rich layer 140a of the present invention equally can be in order to absorb or to stop this densification manufacture craft P2 itself or be subject to the oxygen atom of its high-temperature activation.
Subsequently, planarization packing material 160, oxygen containing silicon-rich layer 140a and laying 130, and as shown in Figure 9, form the laying 130a of the packing material 160a of a planarization, the silicon-rich layer 140b of a planarization and a planarization, make it to flush with hard mask layer 120 '.Afterwards, remove hard mask layer 120 ', as shown in figure 10, form a shallow trench isolation structure G.Then, can carry out the semiconductor fabrication process such as transistor in active region A, B.Therefore this semiconductor fabrication process is this area conventionally knows that the knowledgeable is known and repeats no more.
Hold, the present invention first inserts thing 150, transform again manufacture craft P1 with form packing material 160 and at least the step of the silicon-rich layer 140 of oxidized portion can apply first-class body chemical vapor phase growing (flowable chemical vapor deposition, FCVD) manufacture craft or a rotary coating dielectric layer (spin-on dielectric, SOD) step of manufacture craft, but the present invention is not as limit.
In sum, the present invention proposes a kind of semiconductor structure and manufacture craft thereof, it forms a silicon-rich layer in groove surfaces, particularly in order to form the groove surfaces of shallow trench isolation structure, then insert silicon nitride in groove, then this silicon nitride is converted into packing material usings and use as insulation between two active regions.So, because the present invention first formed a silicon-rich layer in groove surfaces before inserting silicon nitride, composition can prevent from conversion process being passed into or the composition of packing material itself, oxygen atom for example, diffuse in the other substrate of groove, occupy the substrate of part active region and expand the volume of formed shallow trench isolation structure.Further, silicon-rich layer can comprise a silicrete, a silicon nitride layer, one silica layer, a silicon oxynitride layer or a carbonitride silicon layer, and silicon-rich layer can be by plasma auxiliary chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) formation such as manufacture craft or ald (Atomic Layer Deposition, ALD) manufacture craft.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (19)
1. a semiconductor structure, is arranged in a groove of a substrate, and this semiconductor structure includes:
Laying, is positioned at the surface of this groove;
Silicon-rich layer, is positioned on this laying; And
Packing material, is positioned in this silicon-rich layer and fills up this groove.
2. semiconductor structure as claimed in claim 1, wherein this laying comprises oxide layer.
3. semiconductor structure as claimed in claim 1, wherein this silicon-rich layer comprises silicrete, silicon nitride layer, silicon oxide layer, silicon oxynitride layer or carbonitride silicon layer.
4. semiconductor structure as claimed in claim 1, wherein this silicon-rich layer comprises oxygen containing silicon-rich layer.
5. semiconductor structure as claimed in claim 4, wherein the oxygen content distribution gradient of this oxygen containing silicon-rich layer.
6. semiconductor structure as claimed in claim 5, wherein to distribute be that the contact-making surface to this silicon-rich layer and this laying successively decreases from the contact-making surface of this packing material and this silicon-rich layer to this gradient.
7. semiconductor structure as claimed in claim 1, wherein this packing material comprises silica.
8. a semiconductor fabrication process, includes:
Form a groove in a substrate;
Form the surface that a laying covers this groove;
Form a silicon-rich layer on this laying;
Insert a silicon nitride in this groove; And
Carry out a conversion manufacture craft, this silicon nitride is changed into silicon monoxide, and this silicon-rich layer of oxidized portion at least.
9. semiconductor fabrication process as claimed in claim 8, wherein this laying comprises oxide layer.
10. semiconductor fabrication process as claimed in claim 8, wherein this silicon-rich layer comprises with plasma auxiliary chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) manufacture craft or ald (Atomic Layer Deposition, ALD) manufacture craft forms.
11. semiconductor fabrication process as claimed in claim 8, wherein this silicon-rich layer comprises silicrete, silicon nitride layer, silicon oxide layer, silicon oxynitride layer or carbonitride silicon layer.
12. semiconductor fabrication process as claimed in claim 8, wherein the manufacture craft temperature of this conversion manufacture craft is 500 ℃～700 ℃.
13. semiconductor fabrication process as claimed in claim 8, wherein this conversion manufacture craft comprises an oxidation manufacture craft.
14. semiconductor fabrication process as claimed in claim 13, wherein this oxidation manufacture craft comprises and passes into oxygen, ozone or steam.
15. semiconductor fabrication process as claimed in claim 8, after carrying out this conversion manufacture craft, also comprise:
Carry out a densification manufacture craft, with this silica of densification and this silicon-rich layer.
16. semiconductor fabrication process as claimed in claim 15, wherein the manufacture craft temperature of this densification manufacture craft is higher than 1000 ℃.
17. semiconductor fabrication process as claimed in claim 16, wherein the manufacture craft temperature of this densification manufacture craft is 1100 ℃.
18. semiconductor fabrication process as claimed in claim 8, wherein this silicon nitride comprises trimethyl silicane alkanamine (trisilylamine, TSA).
19. semiconductor fabrication process as claimed in claim 8, the step of wherein inserting this silicon nitride and carrying out this conversion manufacture craft is first-class body chemical vapor phase growing (flowable chemical vapor deposition, FCVD) step of manufacture craft or a rotary coating dielectric layer (spin-on dielectric, SOD) manufacture craft.
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| CN201210223143.XA CN103515285B (en) | 2012-06-28 | 2012-06-28 | Semiconductor structure and its manufacture craft |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6576530B1 (en) * | 2002-10-01 | 2003-06-10 | Nanya Technology Corporation | Method of fabricating shallow trench isolation |
| US20040005781A1 (en) * | 2002-07-02 | 2004-01-08 | Chartered Semiconductor Manufacturing Ltd. | HDP SRO liner for beyond 0.18 um STI gap-fill |
| CN1534758A (en) * | 2003-04-02 | 2004-10-06 | 株式会社瑞萨科技 | Semiconductor device mfg. method |
| CN101528974A (en) * | 2006-10-16 | 2009-09-09 | 应用材料股份有限公司 | Formation of high quality dielectric films of silicon dioxide for sti: usage of different siloxane-based precursors for harp II-remote plasma enhanced deposition processes |
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- 2012-06-28 CN CN201210223143.XA patent/CN103515285B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040005781A1 (en) * | 2002-07-02 | 2004-01-08 | Chartered Semiconductor Manufacturing Ltd. | HDP SRO liner for beyond 0.18 um STI gap-fill |
| US6576530B1 (en) * | 2002-10-01 | 2003-06-10 | Nanya Technology Corporation | Method of fabricating shallow trench isolation |
| CN1534758A (en) * | 2003-04-02 | 2004-10-06 | 株式会社瑞萨科技 | Semiconductor device mfg. method |
| CN101528974A (en) * | 2006-10-16 | 2009-09-09 | 应用材料股份有限公司 | Formation of high quality dielectric films of silicon dioxide for sti: usage of different siloxane-based precursors for harp II-remote plasma enhanced deposition processes |
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