TWI541936B - Semiconductor structure and process thereof - Google Patents

Description

Semiconductor structure and its process

The present invention relates to a semiconductor structure and process thereof, and more particularly to a semiconductor structure for forming a germanium-rich layer on a surface of a recess and a process therefor.

In current semiconductor processes, localized oxidation isolation (LOCOS) or shallow trench isolation (STI) methods are generally used to isolate components to avoid short-circuit phenomena caused by mutual interference between components. However, as the design and manufacturing line width of semiconductor wafers become finer, the pits, crystal defects, and bird's beak lengths generated in the LOCOS process are too long. The characteristics of the semiconductor wafer will be greatly affected, and the field oxide layer produced by the LOCOS method occupies a large volume and affects the integration of the entire semiconductor wafer. Therefore, in a submicron semiconductor process, a small size and improved semiconductor wafer shallow trench isolation (STI) process has become a widely used isolation technology.

A typical STI is fabricated by making a recess between the MOS components on the surface of the wafer and filling the dielectric material to create an electrical isolation effect. The dielectric material is typically cerium oxide. In the formation of yttrium oxide, the high temperature of the step of forming yttrium oxide or a subsequent process causes oxygen to diffuse into the ruthenium substrate adjacent to the groove to form the active region of the transistor, and a portion of the ruthenium substrate is oxidized to form ruthenium oxide. In this way, not only can not accurately control each shallow trench isolation junction The size of the structure is equivalent to an increase in the volume of the shallow trench isolation structure formed, and the base of the active region is reduced. However, as the size of semiconductor components is shrinking to near physical limits, different sizes of shallow trench isolation structures and active regions have severely affected the electrical performance and process quality of the components.

The present invention provides a semiconductor structure and process for forming a ytterbium-rich layer on a surface of a recess, particularly a recessed surface for forming a shallow trench isolation structure, to solve the above problems.

The present invention provides a semiconductor structure in a recess in a substrate. The semiconductor structure includes a liner layer, a germanium-rich layer, and a filler material. The backing layer is on the surface of the groove. The ruthenium rich layer is on the liner layer. The filler material is located on the rich layer and fills the grooves.

The present invention provides a semiconductor process comprising the steps described below. First, a recess is formed in a substrate. Next, a liner layer is formed to cover the surface of the groove. Successively, a ruthenium-rich layer is formed on the liner layer. Next, a nitride is filled in the recess. Then, a conversion process is performed to convert the niobium nitride into niobium oxide and at least partially oxidize the niobium-rich layer.

Based on the above, the present invention provides a semiconductor structure and a process thereof for forming a ruthenium-rich layer on a surface of a groove, particularly a groove surface for forming a shallow trench isolation structure, and then filling the ruthenium nitride into the groove, and then This niobium nitride is converted to a filler material for insulation between the active regions. Thus, since the present invention was formed prior to filling the niobium nitride The ruthenium-rich layer is on the surface of the groove so as to prevent the components introduced during the conversion process, such as oxygen atoms, from diffusing into the substrate beside the groove, occupying the base of the active region and expanding the volume of the shallow trench isolation structure formed. .

1 to 10 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention. As shown in Figures 1-3, a substrate 110 having a recess R is provided. In detail, as shown in FIG. 1, a substrate 110 is provided, wherein the substrate 110 is, for example, a germanium substrate, a germanium-containing substrate, a tri-five-layer germanium substrate (eg, GaN-on-silicon), and a graphene coating. A semiconductor substrate such as a graphene-on-silicon or a silicon-on-insulator (SOI) substrate. Next, a hard mask layer 120 is formed on the substrate 110. In this embodiment, the hard mask layer 120 may include a pad oxide layer 122 and a pad nitride layer 124 on the substrate 110 from bottom to top, but the invention is not limited thereto.

As shown in FIG. 2, the hard mask layer 120 is patterned to form a patterned hard mask layer 120' comprising a patterned pad oxide layer 122' and a patterned pad nitride layer 124'. . The method of forming the patterned hard mask layer 120 ′ can be, for example, first forming a patterned photoresist (not shown) on the hard mask layer 120 by using a lithography method, and the patterned photoresist ( The pattern (not shown) defines the position below which the groove R is to be formed. Etching is then performed and a patterned hard mask layer 120' is formed using a pattern of patterned photoresist (not shown) as a mask. Then, after selectively removing the patterned photoresist (not shown), as shown in FIG. 3, the pattern of the patterned hard mask layer 120' is transferred to the substrate 110 by etching or the like to form the substrate. A groove R is formed in 110.

As shown in FIG. 4, a liner layer 130 is formed to completely cover the substrate 110, particularly concave. The surface S of the groove R. The liner layer 130 can be, for example, an oxide layer and/or a nitride layer, etc., and can be formed, for example, by an in situ steam generation (ISSG) process, but the invention is not limited thereto.

As shown in FIG. 5, a germanium-rich layer 140 is formed on the liner layer 130. In the present embodiment, the germanium-rich layer 140 is a tantalum layer. In other embodiments, the antimony-rich layer 140 may also be a layer of a germanium-rich compound such as a tantalum nitride layer, a hafnium oxide layer, a hafnium oxynitride layer or a carbonitride layer, that is, The chemical material layer contains a ratio of oxygen lower than a normal composition, for example, if it is a ruthenium oxide layer, its molecular formula is SiOx and x is less than 2. Furthermore, the yttrium-rich layer 140 may be formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or an Atomic Layer Deposition (ALD) process, and a method for forming a lanthanum-rich layer 140 It depends on the role of the formation of the rich layer 140.

The purpose of forming the germanium-rich layer 140 in the present invention is to prevent the components which are subsequently filled in the recess R and which are formed in the filling material (not shown) on the germanium-rich layer 140 or the components which are introduced in the subsequent process, for example. Oxygen diffuses into the substrate 110 beside the recess R, occupies a portion of the active regions A, B of the semiconductor structure to be formed into a transistor and expands the volume of the shallow trench isolation structure (not shown) formed. Therefore, the method of preventing the filler material or the components of the subsequent process from contaminating the substrate 110 may, for example, be: (1) absorbing the filler material or a component of a subsequent process with the germanium-rich layer 140, for example, providing a reaction source of germanium to consume the filler material. The oxygen atoms, in turn, prevent the filler material or subsequent process oxygen components from entering the substrate 110. At this time, the ytterbium-rich layer 140 is preferably a structure having a loose structure, which has sufficient space for absorbing the filling material or a subsequent process. In this case, it is preferably applied by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process formation Rich layer 140. Alternatively, (2) directly blocking the filler material or subsequent process components into the enthalpy rich layer 140. At this time, the germanium-rich layer 140 is preferably a relatively dense structure, and the germanium can effectively block the filling material or the components of the subsequent process into the germanium-rich layer 140, and the germanium-rich layer 140 is therefore preferably suitable for atomic layer deposition (Atomic). Layer Deposition, ALD) Process formation.

In addition, the germanium-rich layer 140 is preferably formed on the liner layer 130. Since the germanium-rich layer 140 is rich in germanium and the substrate 110 is also a germanium substrate, the liner layer 130 can isolate the two, so that the formed layer is rich. Layer 140 has a preferred structure, and liner layer 130 can further block components of the fill material from entering substrate 110. Furthermore, when the stress of the germanium-rich layer 140 is large, such as a germanium-rich tantalum nitride layer having high stress, the liner layer 130 can serve as a stress buffer layer to prevent the germanium-rich layer 140 from peeling off.

As shown in Fig. 6, a fill 150 is filled in the recess R. In the present embodiment, the filling material 150 is a tantalum nitride; however, in other embodiments, the filling material 150 may also be a tantalum oxide or the like, and the invention is not limited thereto. The fill 150 is generally in a liquid state to sufficiently fill the recess R, wherein the fill 150 comprises, for example, trisilylamine (TSA), but the invention is not limited thereto. Since the depth of the groove R can be, for example, 3,000 angstroms when the semiconductor element is shrunk, and the opening diameter is only 500 angstroms, the groove having such a high aspect ratio is to be etched and made to have an upper width and a lower width. The smooth cross-sectional structure is not easy, so that when the filling material 150 is in a liquid state, it can completely flow into and fill the groove R having a high aspect ratio. Of course, in other embodiments, the filler 150 may also be in other physical states.

Then, as shown in FIG. 7, a conversion process P1 is performed to convert the fill 150 into A filling material 160 is used for insulation between the active regions A, B of the semiconductor element to be formed into a transistor or the like. In the present embodiment, the filler material 160 is niobium oxide, and when the filler 150 is converted, the conversion process P1 oxidizes at least a portion of the germanium-rich layer 140 to form an oxygen-rich germanium-rich layer 140a. Since the germanium-rich layer 140 of the present embodiment is a tantalum layer, in a preferred embodiment, the germanium-rich layer 140 can be completely converted into a hafnium oxide layer. Thus, the enriched layer 140 can be converted into yttrium oxide together with the filler material 160 for insulation, but the invention is not limited thereto. In other embodiments, when the antimony-rich layer 140 is a tantalum nitride layer, the oxygen-rich germanium-rich layer 140a is a hafnium oxynitride layer; when the antimony-rich layer 140 is a carbonitride layer, the oxygen-containing layer The ruthenium rich layer 140a is a carbon oxynitride layer. In the present embodiment, the conversion process P1 is an oxidation process, but the invention is not limited thereto. Specifically, the oxidation process may include direct introduction of oxygen, ozone or water vapor, and the like. The process temperature of the conversion process P1 is, for example, 500 ° C to 700 ° C to sufficiently convert the fill 150 into the filler material 160. Of course, during the conversion of the fill 150 into the filler material 160, a portion of the germanium-rich layer 140 is also oxidized to form an oxygen-rich germanium-rich layer 140a. In one embodiment, the oxygen-containing cerium-rich layer 140a has an oxygen content in a gradient distribution. For example, the oxygen-containing enthalpy-rich layer 140a has an oxygen content which decreases from the contact surface S1 of the self-filling material 160 to the oxygen-containing cerium-rich layer 140a to the contact surface S2 of the oxygen-containing cerium-rich layer 140a and the liner layer 130. Gradient distribution. The oxygen content of the oxygen-rich cerium-rich layer 140a depends on the concentration of oxygen to be introduced or the structural density of the cerium-rich layer 140. As mentioned above, when the yttrium-rich layer 140 is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, it has a loose structure and adsorbs more oxygen atoms, so oxygen-containing The ruthenium-rich layer 140a has a large oxygen content; when the yttrium-rich layer 140 is formed by an Atomic Layer Deposition (ALD) process, It has a relatively dense structure which blocks most of the oxygen atoms from it, so that less oxygen atoms are located therein, so the oxygen-rich cerium-rich layer 140a has less oxygen.

As shown in FIG. 8, the uniform densification process P2 can be selectively performed to further densify the fill material 160 and the oxygen-rich germanium-rich layer 140a. The densification process P2 may include a thermal process or an oxygen process. The process temperature of the densification process P2 is preferably higher than 1000 ° C to achieve a significant dense effect. In a preferred embodiment, the process temperature of the densification process P2 is 1100 °C. Similarly, the cerium-rich layer 140a of the present invention can also be used to absorb or block the oxygenation process of the densification process P2 itself or by its high temperature.

Subsequently, the filling material 160, the oxygen-containing germanium-rich layer 140a, and the liner layer 130 are planarized, and as shown in FIG. 9, a planarized filling material 160a, a planarized germanium-rich layer 140b, and a planarization are formed. The backing layer 130a is flush with the hard mask layer 120'. Thereafter, the hard mask layer 120' is removed, and as shown in Fig. 10, a shallow trench isolation structure G is formed. Then, a semiconductor process such as a transistor in the active regions A and B can be performed. This semiconductor process is well known to those of ordinary skill in the art and will not be described again.

According to the above description, the step of filling the filling material 150 and then performing the conversion process P1 to form the filling material 160 and at least oxidizing part of the cerium-rich layer 140 may be applied by flow chemical vapor deposition (FCVD). The process or a step of spin coating a spin-on dielectric (SOD) process, but the invention is not limited thereto.

In summary, the present invention provides a semiconductor structure and a process thereof for forming a ruthenium-rich layer on a surface of a groove, particularly a groove surface for forming a shallow trench isolation structure, and then filling The niobium nitride is introduced into the recess, and the tantalum nitride is converted into a filling material for insulation between the active regions. Thus, since the present invention forms a ruthenium-rich layer on the surface of the groove before filling the ruthenium nitride, it is possible to prevent the components introduced during the conversion process or the components of the filler material itself, such as oxygen atoms, from diffusing to The substrate adjacent to the recess occupies a portion of the active region and expands the volume of the shallow trench isolation structure formed. Further, the antimony layer may comprise a tantalum layer, a tantalum nitride layer, a niobium monoxide layer, a niobium oxynitride layer or a carbonitride layer, and the niobium rich layer may be plasma-assisted chemical vapor phase. Formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or an Atomic Layer Deposition (ALD) process.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110‧‧‧Base

120‧‧‧hard mask layer

122‧‧‧Mat oxide layer

124‧‧‧Material Nitride

120'‧‧‧ patterned hard mask

122'‧‧‧ patterned pad oxide

124'‧‧‧ patterned pad nitride layer

130‧‧‧ liner

130a‧‧‧Flating cushion layer

140, 140a‧‧‧ rich layer

140b‧‧‧flattened eucalyptus

150‧‧‧矽Nitride

160‧‧‧Filling materials

160a‧‧‧Flating filler material

A, B‧‧ active area

G‧‧‧Shallow trench isolation structure

P1‧‧‧ conversion process

P2‧‧‧ Densification process

R‧‧‧ groove

S‧‧‧ surface

S1, S2‧‧‧ contact surface

1 to 10 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

110‧‧‧Base

130a‧‧‧Flating cushion layer

140b‧‧‧flattened eucalyptus

160a‧‧‧Flating filler material

A, B‧‧ active area

R‧‧‧ groove

S‧‧‧ surface

S1, S2‧‧‧ contact surface

Claims (17)

A semiconductor structure is disposed in a recess of a substrate, the semiconductor structure comprising: a liner layer on a surface of the recess; a germanium-rich layer on the liner layer, wherein the germanium-rich layer comprises an oxygen-containing layer The cerium-rich layer, and the oxygen-containing enthalpy layer has a gradient of oxygen content; and a filler material is located on the cerium-rich layer and fills the groove. The semiconductor structure of claim 1, wherein the liner layer comprises an oxide layer. The semiconductor structure of claim 1, wherein the germanium-rich layer comprises a tantalum layer, a tantalum nitride layer, a hafnium oxide layer, a hafnium oxynitride layer or a carbonitride layer. The semiconductor structure of claim 1, wherein the gradient distribution decreases from a contact surface of the filler material with the germanium-rich layer toward a contact surface of the germanium-rich layer and the liner layer. The semiconductor structure of claim 1, wherein the filler material comprises ruthenium oxide. A semiconductor process comprising: forming a recess in a substrate; Forming a liner layer covering the surface of the recess; forming a ruthenium-rich layer on the liner layer; filling a niobium nitride in the recess; and performing a conversion process to convert the niobium nitride into an oxidation矽, and at least partially oxidize the ruthenium-rich layer. The semiconductor process of claim 6, wherein the liner layer comprises an oxide layer. The semiconductor process of claim 6, wherein the germanium-rich layer comprises a plasma enhanced chemical vapor deposition (PECVD) process or an atomic layer deposition (ALD) process. . The semiconductor process of claim 6, wherein the germanium-rich layer comprises a tantalum layer, a tantalum nitride layer, a hafnium oxide layer, a hafnium oxynitride layer or a carbonitride layer. For example, the semiconductor process described in claim 6 wherein the process temperature of the conversion process is from 500 ° C to 700 ° C. The semiconductor process of claim 6, wherein the conversion process comprises an oxidation process. The semiconductor process of claim 11, wherein the oxidizing process comprises introducing oxygen, ozone or water vapor. For example, in the semiconductor process described in claim 6, after performing the conversion process, the method further comprises: performing a uniform densification process to densify the cerium oxide and the cerium-rich layer. The semiconductor process of claim 13, wherein the process temperature of the densification process is higher than 1000 °C. The semiconductor process of claim 14, wherein the process temperature of the densification process is 1100 °C. The semiconductor process of claim 6, wherein the niobium nitride comprises trisilylamine (TSA). The semiconductor process of claim 6, wherein the step of filling the germanium nitride and performing the conversion process is a fluid chemical vapor deposition (FCVD) process or a spin coating dielectric process. The step of a spin-on dielectric (SOD) process.