CN113345834A - Low-voltage device and manufacturing method thereof - Google Patents
Low-voltage device and manufacturing method thereof Download PDFInfo
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- CN113345834A CN113345834A CN202110899264.5A CN202110899264A CN113345834A CN 113345834 A CN113345834 A CN 113345834A CN 202110899264 A CN202110899264 A CN 202110899264A CN 113345834 A CN113345834 A CN 113345834A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
Abstract
The invention provides a low-voltage device and a manufacturing method thereof. The manufacturing method of the low-voltage device comprises the steps of firstly providing a semiconductor substrate with a plurality of isolation structures, covering a pad oxide layer on the surface of the semiconductor substrate between the isolation structures, then executing an ion implantation process to form a plurality of well regions in the semiconductor substrate, separating the well regions through the isolation structures, enabling the lower surfaces of the isolation structures to be lower than the lower surfaces of the well regions, removing the pad oxide layer, and forming a grid oxide layer on the exposed surface of the semiconductor substrate, wherein the thickness of the grid oxide layer is less than 10 nm. Because a plurality of well regions are separated by a plurality of isolation structures, and the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions, the isolation effect between the well regions can be improved, the electric leakage problem of a low-voltage device is improved, and the reliability of the low-voltage device is improved. The low-voltage device is manufactured by the manufacturing method of the low-voltage device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a low-voltage device and a manufacturing method thereof.
Background
With the rapid development of science and technology, a large number of consumer electronic products (such as tablets or mobile phones) have become necessities of our lives. Chips such as an LED driver IC (LED driver IC) and a fingerprint sensor IC (FPS IC) included in consumer electronics can realize their functions by driving them at a low voltage of 1.8V or less. The market demand for pure low voltage devices is increasing. However, the conventional low-voltage device is easy to have the problem of electric leakage and poor in reliability.
Disclosure of Invention
The invention provides a low-voltage device and a manufacturing method thereof, which can improve the electric leakage problem of the low-voltage device and improve the reliability of the low-voltage device.
In order to achieve the above object, an aspect of the present invention provides a method for manufacturing a low voltage device. The manufacturing method of the low-voltage device comprises the following steps:
providing a semiconductor substrate, wherein a plurality of isolation structures are formed in the semiconductor substrate, and a pad oxide layer covers the surface of the semiconductor substrate between the isolation structures;
performing an ion implantation process to form a plurality of well regions in the semiconductor substrate, wherein the well regions are separated by a plurality of isolation structures, and the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions; and
and removing the pad oxide layer, and forming a gate oxide layer on the exposed surface of the semiconductor substrate, wherein the thickness of the gate oxide layer is less than 10 nm.
Optionally, the pad oxide layer is formed by using a furnace tube wet growth process, and the furnace tube wet growth process uses oxygen carrying water vapor as an oxidant.
Optionally, the method for forming the plurality of isolation structures in the semiconductor substrate includes:
sequentially forming the pad oxide layer, the hard mask layer and the patterned photoresist layer on the surface of the semiconductor substrate;
etching the hard mask layer by taking the patterned photoresist layer as a mask to form a patterned hard mask layer;
removing the patterned photoresist layer, etching the pad oxide layer and the semiconductor substrate by taking the patterned hard mask layer as a mask and stopping in the semiconductor substrate to form a plurality of grooves;
depositing and forming a first isolation medium layer on the semiconductor substrate, wherein the first isolation medium layer covers the patterned hard mask layer and the inner surfaces of the plurality of grooves, and the plurality of grooves are not filled with the first isolation medium layer;
depositing a second isolation medium layer on the semiconductor substrate, wherein the second isolation medium layer covers the upper surface of the first isolation medium layer and fills the plurality of grooves; and
and taking the patterned hard mask layer as a barrier layer, carrying out planarization treatment on the semiconductor substrate to remove the first isolation medium layer and the second isolation medium layer which are higher than the upper surface of the patterned hard mask layer to form a plurality of isolation structures, and then removing the patterned hard mask layer.
Optionally, the first isolation dielectric layer is a silicon oxide layer formed by TEOS deposition; the second isolation medium layer is a silicon oxide layer formed by adopting a high-density plasma deposition process.
Optionally, after the first isolation dielectric layer is formed, 25% to 35% of the depth of the plurality of trenches is filled with the first isolation dielectric layer.
Optionally, a distance between the lower surface of the isolation structure and the upper surface of the semiconductor substrate is 8000 to 9000 angstroms.
Optionally, the plurality of well regions include an N-well and a P-well, and the adjacent N-well and P-well are respectively located on two sides of the same isolation structure.
Optionally, a wet etching process is used to remove the pad oxide layer.
Optionally, the gate oxide layer is generated by an in-situ steam oxidation process.
Optionally, the thickness of the gate oxide layer is 60 angstroms to 70 angstroms.
Optionally, the thickness of the pad oxide layer is 300 angstroms to 400 angstroms.
The invention also provides a low-voltage device which is manufactured by adopting the manufacturing method of the low-voltage device.
The manufacturing method of the low-voltage device comprises the steps of firstly providing a semiconductor substrate with a plurality of isolation structures, covering a pad oxide layer on the surface of the semiconductor substrate between the isolation structures, then executing an ion implantation process to form a plurality of well regions in the semiconductor substrate, separating the well regions through the isolation structures, wherein the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions, then removing the pad oxide layer, and forming a gate oxide layer on the exposed surface of the semiconductor substrate, wherein the thickness of the gate oxide layer is less than 10 nm. The plurality of well regions are separated by the plurality of isolation structures, and the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions, so that the isolation effect among the well regions can be improved, the electric leakage problem of the low-voltage device can be improved, and the reliability of the low-voltage device can be improved; because the pad oxide layer may be damaged after the ion implantation process, the quality of the gate oxide layer can be ensured by removing the pad oxide layer and forming a new gate oxide layer, which is helpful for improving the performance of the low-voltage device.
The low-voltage device is manufactured by the manufacturing method of the low-voltage device, so that the plurality of well regions are separated by the plurality of isolation structures in the low-voltage device, and the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions, so that the isolation effect among the well regions can be improved, the electric leakage problem of the low-voltage device is improved, and the reliability of the low-voltage device is improved; and the gate oxide layer in the low-voltage device is regenerated after ion implantation, so that the quality of the gate oxide layer can be ensured, and the performance of the low-voltage device can be improved.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a low voltage device according to an embodiment of the invention.
Fig. 2 to 7 are schematic structural diagrams illustrating a process of manufacturing a low-voltage device by using a method for manufacturing a low-voltage device according to an embodiment of the invention.
Description of reference numerals: 100-a semiconductor substrate; 101-pad oxide layer; 102-a hard mask layer; 102 a-a patterned hard mask layer; 103-a photoresist layer; 104-a trench; 105-an isolation structure; 106-N well; 107-P well; 108-gate oxide layer.
Detailed Description
The low voltage device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to improve the leakage problem of the low-voltage device and improve the reliability of the low-voltage device, the embodiment provides a manufacturing method of the low-voltage device. Fig. 1 is a schematic flow chart illustrating a method for manufacturing a low voltage device according to an embodiment of the invention. As shown in FIG. 1, the method for manufacturing the low-voltage device comprises the following steps S1-S3.
Step S1: providing a semiconductor substrate, wherein a plurality of isolation structures are formed in the semiconductor substrate, and a pad oxide layer covers the surface of the semiconductor substrate between the isolation structures.
Step S2: and performing an ion implantation process to form a plurality of well regions in the semiconductor substrate, wherein the well regions are separated by a plurality of isolation structures, and the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions.
Step S3: and removing the pad oxide layer, and forming a gate oxide layer on the exposed surface of the semiconductor substrate, wherein the thickness of the gate oxide layer is less than 10 nm.
Fig. 2 to 7 are schematic structural diagrams illustrating a process of manufacturing a low-voltage device by using a method for manufacturing a low-voltage device according to an embodiment of the invention. The method for manufacturing the low voltage device of the present embodiment is further described with reference to fig. 2 to 7.
In this embodiment, the method of forming the plurality of isolation structures in the semiconductor substrate may include the following substeps S11-S15.
In step S11, as shown in fig. 2, a pad oxide layer 101, a hard mask layer 102 and a patterned photoresist layer 103 are sequentially formed on the semiconductor substrate 100.
The semiconductor substrate 100 may be a silicon substrate. But not limited thereto, the semiconductor substrate 100 may also be a Germanium substrate, a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like, and a certain doping particle may be implanted into the semiconductor substrate 100 according to design requirements to change electrical parameters.
The pad oxide layer 101 may be a silicon oxide layer. The thickness of the pad oxide layer 101 may be 300 to 400 angstroms. The principle of wet growth of the pad oxide layer in the furnace tube is as follows: to carry water vapor (H)2O) oxygen as an oxidizing agent reacts with silicon on the surface of the silicon substrate in the furnace tube to form silicon oxide, and the oxidizing agent also reaches SiO through the silicon oxide on the surface in a diffusion manner2The Si interface reacts with the silicon atoms to form new silicon oxide, so that the thickness of the silicon oxide layer is increased continuously to form a silicon oxide layer with a set thickness and serve as the pad oxide layer 101. The reaction formula of the furnace wet-grown pad oxide layer 101 is as follows: si(s) + O2(g)→SiO2(s)，Si(s)+2H2O(g)→SiO2(s)+2H2(g) In that respect The silicon oxide layer is grown by the furnace tube dry method, and oxygen is used as an oxidant to react with silicon on the surface of the silicon substrate in the furnace tube to generate silicon oxide. The reaction formula of the furnace tube dry-method growth silicon oxide layer is as follows: si(s) + O2(g)→SiO2(s)。
In this embodiment, the pad oxide layer 101 may be formed by a furnace tube wet growth process. Since the furnace tube wet-process growth silicon oxide layer takes oxygen carrying water vapor as an oxidant, the speed of generating silicon oxide is high, and the forming speed of the pad oxide layer 101 can be improved. For example, the time required for forming the pad oxide layer 101 of 300-400 angstroms by using the furnace tube wet growth is about 9.5 hours; the time required for forming the 300-400 angstrom pad oxide layer 101 by adopting the furnace tube dry growth is about 13 hours; therefore, the pad oxide layer with the same thickness formed by adopting the furnace tube wet growth can save about 27% of growth time and is beneficial to improving the manufacturing efficiency of the low-voltage device.
When the pad oxide layer 101 is formed by furnace wet growth, the furnace temperature may be 750-850 ℃, for example 800 ℃. When the pad oxide layer 101 is formed by furnace tube dry growth, the furnace tube temperature can be 1100-1200 ℃. Namely, the requirement of furnace tube wet growth on the temperature of the furnace tube is relatively low. In other embodiments, the pad oxide layer 101 may also be formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process, but the forming speed is relatively slow.
The hard mask layer 102 may be a silicon nitride layer. But not limited thereto, the hard mask layer 102 may also be a multi-layer structure, for example, the hard mask layer 102 may include a silicon nitride layer-a silicon oxide layer-a silicon nitride layer sequentially stacked on the surface of the pad oxide layer 101. The hard mask layer 102 may have a thickness of 1000 angstroms to 1300 angstroms.
The method for forming the patterned photoresist layer 103 may be: a photoresist is coated on the surface of the hard mask layer 102, and the photoresist on the hard mask layer 102 is exposed and developed to form the patterned photoresist layer 103. In order to improve the pattern accuracy of the patterned photoresist layer 103, the photoresist may be subjected to a post-exposure bake after being exposed.
After the end of substep S11, substep S12 is executed. As shown in fig. 3 and 4, the hard mask layer 102 is etched using the patterned photoresist layer 103 as a mask to form a patterned hard mask layer 102 a.
Performing a substep S13, removing the patterned photoresist layer 103, etching the pad oxide layer 101 and the semiconductor substrate 100 with the patterned hard mask layer 102a as a mask and stopping in the semiconductor substrate 100, and forming a plurality of trenches 104.
In this embodiment, an ashing process may be used to remove the patterned photoresist layer 103. The hard mask layer 102, the pad oxide layer 101, and the semiconductor substrate 100 may be etched using a dry etching process. The gas used in the dry etching process may be CHF3、CF4、CH2F2、HBr、Cl2Or SF6One or a combination thereof. Not limited thereto, the etching process may be a wet etching processThe hard mask layer 102, the pad oxide layer 101, and the semiconductor substrate 100. In this embodiment, the depth of the trench 104 may be 8000 to 9000 angstroms.
After the plurality of trenches are formed, a sub-step S14 is performed to fill the plurality of trenches 104 with an isolation medium to form the plurality of isolation structures 105.
In this embodiment, the isolation medium may include a first isolation medium layer and a second isolation medium layer, and the method of filling the isolation medium in the plurality of trenches 104 to form the plurality of isolation structures 105 may include: depositing and forming a first isolation medium layer on the semiconductor substrate 101, wherein the first isolation medium layer covers the patterned hard mask layer 102a and the inner surfaces of the plurality of trenches 104, and the first isolation medium layer does not fill the plurality of trenches 104; depositing a second isolation dielectric layer on the semiconductor substrate 100, wherein the second isolation dielectric layer covers the upper surface of the first isolation dielectric layer and fills the plurality of trenches 104; with the patterned hard mask layer 102a as a barrier layer, the semiconductor substrate 100 is planarized to remove the first isolation dielectric layer and the second isolation dielectric layer above the upper surface of the patterned hard mask layer 102a to form the plurality of isolation structures 105, and then the patterned hard mask layer 102a is removed.
It should be noted that, in this embodiment, since the depth of the trench 104 is relatively deep, when the trench 104 is filled, and the trench 104 is filled at one time, a hole is likely to occur in the isolation medium, and the hole is likely to affect the isolation effect of the isolation structure 105, in this embodiment, the trench 104 may be filled in two steps, so as to reduce the obtained hole (including the first isolation medium and the second isolation medium) in the isolation medium in the isolation structure 105, improve the isolation effect of the isolation structure 105, and improve the reliability of the low-voltage device.
The first isolation dielectric layer may be a silicon oxide layer formed by deposition of TEOS (tetraethylorthosilicate). TEOS and ozone (O)3) When silicon oxide is generated by reaction, TEOS has good fluidity and excellent covering and filling energy for the groove with high depth ratioTherefore, the bottom and the corners of the trench 104 can be completely filled, thereby avoiding the formation of voids at the bottom of the trench 104, and simultaneously, the TEOS is economical and can save the production cost.
The second isolation dielectric layer may be a silicon oxide layer formed by a high density plasma deposition (HDP) process. In the HDP process, deposition and etching are performed simultaneously, and by setting a suitable deposition-etch rate ratio (DS ratio), the second isolation dielectric layer can well fill the remaining portion (i.e., the unfilled portion) of the trench 104, and holes are not easily formed in the second isolation dielectric layer. But not limited thereto, the first and second isolation dielectric layers may be deposited using other deposition processes.
When the filling depth proportion of the first isolation dielectric layer in the trench 104 is less than 25%, the filling amount of the second isolation dielectric layer in the trench 104 is still larger, so that holes are easy to appear in the second isolation dielectric layer, and the filling quality of the trench 104 is poor; if the filling depth proportion of the first isolation dielectric layer in the trench 104 is greater than 35%, the first isolation dielectric layer in the trench is prone to generate holes, so in this embodiment, after the first isolation dielectric layer is formed, 25% -35% of the depth of the trenches 104 can be filled with the first isolation dielectric layer, and the rest of the trenches 104 can be filled with the second isolation dielectric layer.
In another embodiment, the trench 104 may be filled with an isolation dielectric (e.g., silicon oxide) at a time to reduce the manufacturing time and cost of the isolation structure 105, or the trench 104 may be filled in three or more steps.
In this embodiment, after the second isolation dielectric layer is formed, a Chemical Mechanical Polishing (CMP) process may be used to planarize the semiconductor substrate 100; alternatively, the semiconductor substrate 100 may be planarized by a combination of a chemical mechanical polishing process and a wet etching process.
In this embodiment, the distance between the lower surface of the isolation structure 105 and the upper surface of the semiconductor substrate 100 (i.e., the depth of the isolation structure 105) may be 8000 a to 9000 a, and since the depth of the isolation structure 105 is large, the ion implantation conditions need not be specially adjusted when the subsequent ion implantation forms the well region.
After the isolation structures 105 are formed on the semiconductor substrate 100, step S15 is performed to remove the patterned hard mask layer 102a, as shown in fig. 4. The patterned hard mask layer 102a may be removed by a dry etching process, or the patterned hard mask layer 102a may be removed by etching using a combination of dry etching and wet etching. For example, a hard mask layer of silicon nitride is removed using a hot phosphoric acid solution.
As shown in fig. 4, a plurality of the isolation structures 105 define a plurality of Active regions (Device Active areas) which are subsequently used to form well regions of low voltage devices.
After the end of step S1, step S2 is executed to perform an ion implantation process, so as to form a plurality of well regions in the semiconductor substrate 100 (specifically, on the active region), wherein the well regions are separated by the isolation structures 105, and the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions (i.e., the depth of the isolation structures 105 is greater than the depth of the well regions).
As shown in fig. 5, the plurality of well regions may include an N-well 106 and a P-well 107, and the adjacent N-well 106 and the adjacent P-well 107 may be respectively located at two sides of the same isolation structure 105. The ion implantation conditions for fabricating the N-well 106 and the P-well 107 are similar to those for forming CMOS devices.
In this embodiment, the method for forming the N-well 106 and the P-well 107 may include: forming a patterned first mask layer on the semiconductor substrate 100, wherein the patterned first mask layer exposes the surface of the N-well 106 forming region and covers the P-well 107 forming region and the surfaces of the isolation mechanisms 105; performing a first ion implantation on the semiconductor substrate 100 by using the patterned first mask layer as a mask to form a plurality of N wells; removing the first mask layer; forming a patterned second mask layer on the semiconductor substrate 100, wherein the patterned second mask layer exposes the surface of the P-well 107 forming region and covers the surfaces of the N-well 106 and the isolation structure 105; performing a second ion implantation on the semiconductor substrate 100 by using the patterned second mask layer as a mask to form a plurality of P wells 107; and removing the patterned second mask layer. In more detail, after the second ion implantation, the semiconductor substrate 100 is heat-treated to activate and diffuse impurity ions implanted into the semiconductor substrate 100, thereby forming a final N-well and a final P-well.
The depth of the N-well 106 and the depth of the P-well 107 can be made smaller than the depth of the isolation structure 105 (that is, the lower surfaces of the N-well 106 and the P-well 107 are on the lower surface of the isolation structure 105) by controlling the process parameters of the first ion implantation and the second ion implantation and the process parameters of the thermal treatment, so that the isolation structure 105 can effectively isolate the N-well 106 and the P-well 107, which is helpful for improving the leakage problem of the low-voltage device. The first mask layer and the second mask layer may both be photoresist layers.
After the well regions are formed, step S3 is performed, as shown in fig. 6 and 7, the pad oxide layer 101 is removed, and a gate oxide layer 108 is formed on the exposed surface of the semiconductor substrate 100, where the thickness of the gate oxide layer 108 is less than or equal to 10 nm.
During the ion implantation process, the pad oxide layer 101 may be damaged, and if the pad oxide layer 101 is used as the gate oxide layer, the performance of the low voltage device is poor. In order to improve the performance of the low voltage device, as shown in fig. 6, the relatively poor quality pad oxide layer 101 is removed, exposing the semiconductor substrate surfaces of the N-well 106 and the P-well 107. In this embodiment, the pad oxide layer 101 may be removed by a wet etching process, for example, using a DHF solution (i.e., HF, H)2O2And H2Mixed solution of O) or SPM solution (i.e. H)2SO4、H2O2And H2A mixture of O). Since the semiconductor substrate 100 is formed with low voltage wells and no high voltage region, no photomask is needed to protect the high voltage region during the etching process to remove the pad oxide layer 101, thereby avoiding the need to etch the pad oxide layerThe manufacturing process of the low-voltage device uses relatively few light covers and has relatively low production cost.
In this embodiment, the thickness of the gate oxide layer 108 is less than 10nm, for example, 60 to 70 angstroms, so that the low voltage device can operate and realize corresponding functions under low voltage driving of, for example, less than 1.8V. But not limited thereto, for low voltage devices in different application fields, gate oxide layers with different thicknesses can be generated to adjust gate voltages (threshold voltages) when different low voltage devices are switched on and off, thereby achieving the driving effect.
In this embodiment, the gate oxide layer 108 may be a silicon oxide layer. In the present embodiment, an In-Situ Steam oxidation (ISSG Oxide) process is used to form the gate Oxide layer 108, and the formed gate Oxide layer 108 has good coverage capability and uniformity, and the gate Oxide layer 108 has good compactness, which is helpful for improving the performance of the low-voltage device and improving the Mismatch problem of the device. The reaction formula of the silicon oxide layer generated by the in-situ steam oxidation process is Si(s) +2H2(g)+2O2(g)→SiO2(s)+2H2O(g)。
In the method for manufacturing the low voltage device of this embodiment, first, a semiconductor substrate 100 formed with a plurality of isolation structures 105 is provided, a pad oxide layer 101 covers a surface of the semiconductor substrate 100 between the isolation structures 105, then, an ion implantation process is performed to form a plurality of well regions (e.g., an N well 106 and a P well 107) in the semiconductor substrate 100, the well regions are separated by the isolation structures 105, and a lower surface of the isolation structures 105 is lower than a lower surface of the well regions (i.e., a depth of the isolation structures 105 extending into the semiconductor substrate from the upper surface of the semiconductor substrate 100 is deeper than a depth of the well regions extending into the semiconductor substrate), then, the pad oxide layer 101 is removed, and a gate oxide layer 108 is formed on an exposed surface of the semiconductor substrate 100, wherein a thickness of the gate oxide layer 108 is less than 10 nm. The well regions are separated by the isolation structures 105, and the lower surfaces of the isolation structures 105 are lower than the lower surfaces of the well regions, so that the isolation effect among the well regions can be improved, the electric leakage problem of a low-voltage device can be improved, and the reliability of the low-voltage device can be improved; since the pad oxide layer 101 may be damaged after the ion implantation process, the quality of the gate oxide layer 108 may be ensured by removing the pad oxide layer 101 and forming a new gate oxide layer 108, which is helpful for improving the performance of the low voltage device.
In addition, for manufacturers of chips (Foundry), time, labor and financial resources are required to develop new processes and new Process Design Kit (PDK) files on a large scale. The manufacturing method of the low-voltage device can be compatible with a standard CMOS process, so that the same set of PDK file can be shared with the CMOS process, a new PDK file does not need to be developed, and the development cost of the PDK file is saved.
The embodiment also provides a low-voltage device, and the low-voltage device can be manufactured by adopting the manufacturing method of the low-voltage device.
Referring to fig. 7, the low voltage device may include: a semiconductor substrate 100, an isolation structure 105 and a gate oxide layer 108. Specifically, a plurality of well regions (for example, including an N well 106 and a P well 107) are formed on the semiconductor substrate 100, the well regions are separated by the isolation structures 105, the lower surfaces of the isolation structures 105 are lower than the lower surfaces of the well regions, and a gate oxide layer 108 is formed on the surface of the semiconductor substrate (i.e., the surface of the semiconductor substrate 100 between the isolation structures 105) of the well regions.
In the low-voltage device of the embodiment, the plurality of well regions are separated by the plurality of isolation structures 105, and the lower surfaces of the isolation structures 105 are lower than the lower surfaces of the well regions, so that the isolation effect between the well regions can be improved, the problem of electric leakage of the low-voltage device is improved, and the reliability of the low-voltage device is improved; in addition, the gate oxide layer 108 in the low-voltage device is regenerated after ion implantation, so that the quality of the gate oxide layer 108 can be ensured, and the performance of the low-voltage device can be improved.
In this embodiment, the driving voltage of the low-voltage device may be below 1.8V.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (12)
1. A method for manufacturing a low-voltage device is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a plurality of isolation structures are formed in the semiconductor substrate, and a pad oxide layer covers the surface of the semiconductor substrate between the isolation structures;
performing an ion implantation process to form a plurality of well regions in the semiconductor substrate, wherein the well regions are separated by a plurality of isolation structures, and the lower surfaces of the isolation structures are lower than the lower surfaces of the well regions; and
and removing the pad oxide layer, and forming a gate oxide layer on the exposed surface of the semiconductor substrate, wherein the thickness of the gate oxide layer is less than 10 nm.
2. The method according to claim 1, wherein the pad oxide layer is formed by a furnace wet growth process, and the furnace wet growth process uses oxygen carrying water vapor as an oxidant.
3. The method of fabricating of claim 1, wherein forming the plurality of isolation structures in the semiconductor substrate comprises:
sequentially forming the pad oxide layer, the hard mask layer and the patterned photoresist layer on the surface of the semiconductor substrate;
etching the hard mask layer by taking the patterned photoresist layer as a mask to form a patterned hard mask layer;
removing the patterned photoresist layer, etching the pad oxide layer and the semiconductor substrate by taking the patterned hard mask layer as a mask and stopping in the semiconductor substrate to form a plurality of grooves;
depositing and forming a first isolation medium layer on the semiconductor substrate, wherein the first isolation medium layer covers the patterned hard mask layer and the inner surfaces of the plurality of grooves, and the plurality of grooves are not filled with the first isolation medium layer;
depositing a second isolation medium layer on the semiconductor substrate, wherein the second isolation medium layer covers the upper surface of the first isolation medium layer and fills the plurality of grooves; and
and taking the patterned hard mask layer as a barrier layer, carrying out planarization treatment on the semiconductor substrate to remove the first isolation medium layer and the second isolation medium layer which are higher than the upper surface of the patterned hard mask layer to form a plurality of isolation structures, and then removing the patterned hard mask layer.
4. The method of claim 3, wherein the first isolation dielectric layer is a silicon oxide layer formed by TEOS deposition; the second isolation medium layer is a silicon oxide layer formed by adopting a high-density plasma deposition process.
5. The method of claim 3, wherein after forming the first isolation dielectric layer, 25% to 35% of the depth of the plurality of trenches is filled with the first isolation dielectric layer.
6. The method of claim 1, wherein a distance between a lower surface of the isolation structure and an upper surface of the semiconductor substrate is 8000 to 9000 angstroms.
7. The method of claim 1, wherein the plurality of well regions comprise N-wells and P-wells, and wherein adjacent N-wells and P-wells are located on two sides of the same isolation structure.
8. The method of claim 1, wherein the pad oxide layer is removed using a wet etch process.
9. The method of claim 1, wherein the gate oxide layer is formed using an in-situ steam oxidation process.
10. The method of claim 1, wherein the gate oxide layer has a thickness of 60 to 70 angstroms.
11. The method of claim 1, wherein the pad oxide layer has a thickness of 300 to 400 angstroms.
12. A low-voltage device, characterized by being manufactured by the method of manufacturing a low-voltage device according to any one of claims 1 to 11.
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| CN202110899264.5A CN113345834A (en) | 2021-08-06 | 2021-08-06 | Low-voltage device and manufacturing method thereof |
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| CN202110899264.5A CN113345834A (en) | 2021-08-06 | 2021-08-06 | Low-voltage device and manufacturing method thereof |
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| CN114927465A (en) * | 2022-07-19 | 2022-08-19 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN114999907A (en) * | 2022-08-08 | 2022-09-02 | 合肥新晶集成电路有限公司 | Manufacturing method of grid oxide layer and manufacturing method of field effect transistor |
| US11862461B2 (en) | 2021-12-28 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method of forming oxide layer on a doped substrate using nitridation and oxidation process |
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| US11862461B2 (en) | 2021-12-28 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method of forming oxide layer on a doped substrate using nitridation and oxidation process |
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