CN113451119A - Method for improving uniformity of grid oxide layer - Google Patents
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- CN113451119A CN113451119A CN202010216931.0A CN202010216931A CN113451119A CN 113451119 A CN113451119 A CN 113451119A CN 202010216931 A CN202010216931 A CN 202010216931A CN 113451119 A CN113451119 A CN 113451119A
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 230000003647 oxidation Effects 0.000 claims abstract description 59
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 4
- 238000009279 wet oxidation reaction Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 12
- 239000001301 oxygen Substances 0.000 description 12
- 229910052760 oxygen Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a method for improving the uniformity of a grid oxide layer, which is characterized by comprising the following steps of: (1) providing a semiconductor substrate with a shallow trench isolation structure; (2) growing a first thermal oxidation layer on the semiconductor substrate in a thermal oxidation mode; (3) depositing a second deposited oxide layer on the first thermal oxide layer in a high-temperature oxidation mode, so as to form a target grid oxide layer; (4) and annealing the target grid oxide layer to obtain a final grid oxide layer. The method for improving the uniformity of the grid oxide layer can avoid the breakdown of an MOS device from the corner of the shallow trench isolation structure, and can break the thickness limitation of the grid oxide layer, so that the performance and the reliability of the device can be effectively improved to a great extent.
Description
Technical Field
The present invention relates generally to the field of semiconductor device manufacturing processes, and more particularly, to a method of improving gate oxide uniformity.
Background
At present, with the rapid development of very large scale integrated circuits and very large scale integrated circuits, increasingly strict requirements are put forward on the manufacturing process of semiconductor devices, and the preparation process of a gate oxide layer is a key technology in the manufacturing process of semiconductor devices, so that the electrical characteristics and reliability of the semiconductor devices can be directly influenced and determined, and particularly, the requirements on the gate oxide layer are correspondingly more strict when the characteristic dimension of Metal Oxide Semiconductor (MOS) devices enters the nanometer era.
In the field of manufacturing existing MOS devices, a Shallow Trench Isolation (STI) technique is widely used, in which a shallow trench is first formed on a semiconductor substrate by etching, then the shallow trench is filled by high density plasma deposition (HDP) or the like, and finally surface planarization is performed by Chemical Mechanical Polishing (CMP). However, the planarized shallow trench isolation structures have corners, and the gate oxide layer is required to be formed between at least two shallow trench isolation structures and to cover the corners of the shallow trench isolation structures.
The traditional growth method of the grid oxide layer adopts a one-step thermal oxidation mode, and has two problems: on one hand, because the oxidation speed at the corner of the shallow trench isolation structure is lower than that of the flat region, the thickness of the oxide layer grown at the corner is far smaller than that of the oxide layer grown at the flat region, so that a corresponding MOS device is easy to break down from the corner when in use to cause electric leakage, and the service life of the MOS device is further influenced. On the other hand, the thickness of the gate oxide layer grown thereby is limited due to the consumption of silicon by the thermal oxidation, and if the MOS device has a high requirement for the thickness of the gate oxide layer, the conventional thermal oxidation may not achieve the thickness requirement, because the growth speed is slower and slower as the grown oxide is thicker and thicker, the required growth time is multiplied, and the regrowth is not possible when the limit is reached.
The prior art case is described in more detail below with reference to figures 1-3: fig. 1 shows a semiconductor substrate 1 in which a shallow trench isolation structure 2 has been made, wherein the shallow trench isolation structure 2 has corners 3. Fig. 2 shows a prior art gate oxide layer 4 formed on the semiconductor substrate 1 of the shallow trench isolation structure 2 shown in fig. 1 by a thermal oxidation process. Fig. 3 is a partial enlarged view of fig. 2, in which the thickness of the gate oxide layer 4 at the corners is denoted by d1, d2, and the thickness of the gate oxide layer 4 at the flat region is denoted by d 3. In one example, the gate oxide layer has thicknesses d1, d2 at the corners of 12.6nm, 13.2nm, respectively, and a thickness d3 at the planar regions of 28.3 nm. It can be seen from this that the thickness d1, d2 of the gate oxide layer 4 at the corners is significantly smaller than the thickness d3 of the gate oxide layer 4 at the flat regions.
Based on this, the prior art still remains to be improved.
Disclosure of Invention
To solve the above technical problems, the present invention provides a method for improving uniformity of a gate oxide layer.
According to an embodiment of the present invention, a method for improving uniformity of a gate oxide layer includes the steps of:
(1) providing a semiconductor substrate with a shallow trench isolation structure;
(2) growing a first thermal oxidation layer on the semiconductor substrate in a thermal oxidation mode;
(3) depositing a second deposited oxide layer on the first thermal oxide layer in a high-temperature oxidation mode, so as to form a target grid oxide layer;
(4) and annealing the target grid oxide layer to obtain a final grid oxide layer.
Further, the step (2) of growing the first thermal oxide layer is performed at 700-900 ℃ and under normal pressure.
Further, the step (2) of growing the first thermal oxide layer adopts a dry oxygen oxidation process.
Further, the step (2) of growing the first thermal oxide layer adopts a wet oxygen oxidation process.
Further, the deposition of the second deposited oxide layer in the step (3) is performed at a temperature of 700 ℃ and 900 ℃ and under a pressure of 40 to 60 Pa.
Further, the step (3) of depositing the second oxide layer is performed by introducing SiH2Cl2And N2In the case of O gas.
Further, the thickness of the final gate oxide layer is 180-275A.
Further, the thickness of the first thermal oxidation layer is 10-25A.
Further, the thickness of the second deposited oxide layer is 170-250A.
Further, the method includes the step (5) of depositing a layer of polysilicon on the final gate oxide layer after the annealing treatment.
By adopting the technical scheme, the invention at least has the following beneficial effects:
according to the invention, a first thin thermal oxidation layer capable of ensuring uniformity and density is grown in a thermal oxidation mode, then a second deposited oxidation layer is deposited on the first thermal oxidation layer in a high-temperature oxidation mode, and then annealing treatment is carried out, so that the compactness of the second deposited oxidation layer is improved to enable the second deposited oxidation layer to be closer to the characteristic of the first thermal oxidation layer, and the adhesion between the second deposited oxidation layer and the first thermal oxidation layer is enhanced, therefore, the uniformity of a grid oxidation layer is greatly improved, the problem of thin oxidation layer at a silicon corner is effectively improved, an MOS device can be prevented from being punctured from the corner of a shallow trench isolation structure to cause electric leakage, the limitation of the thickness of the grid oxidation layer is broken, and the performance and reliability of the device can be effectively improved to a great extent.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a semiconductor substrate with shallow trench isolation structures formed therein;
FIG. 2 is a schematic cross-sectional view of a gate oxide layer formed on the semiconductor substrate of FIG. 1 by a prior art method;
FIG. 3 is an enlarged view of a portion of the circled portion of FIG. 2;
FIG. 4 is a flowchart of a method for improving uniformity of a gate oxide layer according to the present invention;
FIG. 5 is a schematic cross-sectional view of a gate oxide layer formed on the semiconductor substrate shown in FIG. 1 by the method of the present invention;
FIG. 6 is an enlarged view of a portion of the circled portion of FIG. 5;
fig. 7A and 7B are ID-VG curves for MOS devices with gate oxide layers formed by prior art methods and by the method of the present invention, respectively.
Detailed Description
Embodiments of the present disclosure are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; certain features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for a typical application. However, various combinations and modifications of the features consistent with the teachings of the present disclosure may be desirable for certain specific applications or implementations.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
The present invention provides a method 100 for improving the uniformity of a gate oxide layer, referring to fig. 1, the method 100 comprising the steps of: in step 102, a semiconductor substrate, such as the substrate shown in fig. 1, on which a shallow trench isolation structure has been formed is provided; in step 104, growing a first thermal oxide layer on the semiconductor substrate by means of thermal oxidation; depositing a second deposited oxide layer on the first thermal oxide layer by means of High Temperature Oxidation (HTO) to form a target gate oxide layer at step 106; in step 108, the target gate oxide layer is annealed to obtain a final gate oxide layer.
In one embodiment of the present invention, the semiconductor substrate is a silicon substrate. However, in other embodiments, the semiconductor substrate may be a substrate made of other materials besides a silicon substrate, such as a germanium substrate, a silicon germanium substrate, and the like. Before growing the gate oxide layer, the semiconductor substrate is made into a shallow trench isolation structure by a conventional method in the field.
In one embodiment of the present invention, the step 104 of growing the first thermal oxide layer on the semiconductor substrate by thermal oxidation is performed by using a dry oxygen oxidation process (i.e., in an oxygen atmosphere), at 700-900 ℃ (e.g., at 700 ℃, 800 ℃ and 900 ℃), respectively), and at normal pressure. The reaction equation is: o is2+Si→SiO2. That is, the reaction mechanism is that the introduced oxygen reacts with silicon atoms on the surface of the silicon substrate to form silicon dioxide, i.e., the first thermal oxide layer.
In another embodiment of the present invention, the step 104 of growing the first thermal oxide layer on the semiconductor substrate by thermal oxidation is performed by using a wet oxygen oxidation process (i.e. in a water-gas environment) at 700-900 ℃ (it is understood that, within the protection scope of the technical solution of the present invention, the temperature range of 700-900 ℃ (for example, at 700 ℃, 800 ℃ and 900 ℃), respectively, may meet the technical purpose of the present invention in practice, and is performed at normal pressure. The reaction equation is: h2O+Si→SiO2+H2. That is, the reaction mechanism is that the introduced water vapor reacts with silicon atoms on the surface of the silicon substrate to form silicon dioxide, i.e., the first thermal oxide layer.
The first thermal oxide layer is grown at a slower speed by adopting a dry oxygen oxidation process, but H + bonds are not doped in the grown oxide layer; in contrast, the first thermal oxide layer grows faster with a wet oxygen oxidation process, but with H+The bonds are doped in the grown oxide layer. H+Charges are attracted to cause leakage.
In a preferred embodiment of the present invention, the growth thickness of the first thermal oxide layer is 10-25A, and it can be understood that 10-25A is the growth thickness that can be obtained by the technical solution of the present invention, and the thickness of the first thermal oxide layer can ensure uniformity and compactness of the oxide layer. The growth rate of the first thermal oxidation layer is about 6-10A/h, and the growth time is 1-3 hours.
In one embodiment of the present invention, the step 106 of depositing the second deposited oxide layer on the first thermal oxide layer by high temperature oxidation is performed by introducing SiH at 700-900 ℃ (for example, at 700 ℃, 800 ℃ and 900 ℃), respectively2Cl2And N2Under the condition of O mixed gas (the ratio is 1: 2), the reaction is carried out under the low pressure of 40-60 Pa. The reaction equation is SiH2Cl2+2N2O→SiO2+2N2+2 HCl. That is, the reaction mechanism is the presence of SiH2Cl2And N2And reacting the O mixed gas at high temperature to generate silicon dioxide, namely a second deposited oxide layer. Compared with a thermal oxidation mode, the high-temperature oxidation mode is adopted, so that the thickness of the second deposition oxide layer is not limited, and any required thickness can be deposited according to the requirement.
In a preferred embodiment of the present invention, the thickness of the second deposited oxide layer is 170 to 250A. The deposition rate of the second deposited oxide layer is about 120-180A/h, and the deposition time is about 1-2 hours.
In one embodiment of the present invention, the annealing process of the target gate oxide layer in step 108 is performed at 900-1000 ℃. The annealing treatment is used for repairing the lattice damage and defects of the second deposited oxide layer, improving the compactness of the second deposited oxide layer to be closer to the compactness of the first thermal oxide layer, and helping to strengthen the adhesion between the second deposited oxide layer and the first thermal oxide layer.
In a preferred embodiment of the present invention, the thickness of the final gate oxide layer is 180-275A. The annealing process does not change the thickness of the first thermal oxide layer and/or the second deposited oxide layer.
In one embodiment of the present invention, the method 100 further includes the additional step of depositing a layer of polysilicon over the final gate oxide layer after the annealing process.
Specific embodiments of the present invention are described below:
example 1
Providing a semiconductor substrate with a shallow trench isolation structure; growing a first thermal oxidation layer on the semiconductor substrate by adopting a dry oxygen oxidation process at 800 ℃ in a thermal oxidation mode; depositing a second deposited oxide layer on the first thermal oxide layer by means of high-temperature oxidation at 800 ℃; annealing the second deposited oxide layer at 950 ℃; after the annealing process, a layer of polysilicon is deposited.
Example 2
Providing a semiconductor substrate with a shallow trench isolation structure; growing a first thermal oxidation layer on the semiconductor substrate by adopting a dry oxygen oxidation process at 700 ℃ in a thermal oxidation mode; depositing a second deposited oxide layer on the first thermal oxide layer by means of high-temperature oxidation at 900 ℃; annealing the second deposited oxide layer at 1000 ℃; after the annealing process, a layer of polysilicon is deposited.
Example 3
Providing a semiconductor substrate with a shallow trench isolation structure; growing a first thermal oxidation layer on the semiconductor substrate by adopting a dry oxygen oxidation process at 900 ℃ in a thermal oxidation mode; depositing a second deposited oxide layer on the first thermal oxide layer by means of high-temperature oxidation at 700 ℃; annealing the second deposited oxide layer at 900 ℃; after the annealing process, a layer of polysilicon is deposited.
Example 4
Providing a semiconductor substrate with a shallow trench isolation structure; growing a first thermal oxidation layer on the semiconductor substrate by adopting a wet oxygen oxidation process at 800 ℃ in a thermal oxidation mode; depositing a second deposited oxide layer on the first thermal oxide layer by means of high-temperature oxidation at 800 ℃; annealing the second deposited oxide layer at 950 ℃; after the annealing process, a layer of polysilicon is deposited.
The beneficial effects of the present invention are described below with reference to fig. 5, 6, and 7A-7B:
fig. 5 shows a schematic cross-sectional view of a gate oxide layer formed on the semiconductor substrate shown in fig. 1 by the method of the present invention. It can be seen that: the formed gate oxide is divided into two parts, a first thermal oxide layer 5 on the lower side and a second deposited oxide layer 6 on the upper side. Fig. 6 is a partial enlarged view of fig. 5, wherein the thickness of the gate oxide layer at the corners is denoted by d1 ' and d2 ', and the thickness of the gate oxide layer at the flat region is denoted by d3 '. In one embodiment, the thicknesses d1 'and d 2' of the gate oxide layer formed by the method of the present invention at the corners are 23.6nm and 24.5nm, respectively, and the thickness d3 'at the flat region is 27.4nm, respectively, so it can be seen that the thickness d 1', d2 'of the gate oxide layer formed by the method of the present invention at the corners is not significantly different from the thickness d 3' at the flat region. Therefore, compared with the prior art, the method greatly improves the uniformity of the grid oxide layer and effectively solves the problem that the oxide layer at the corner of the silicon is thinner.
Fig. 7A and 7B show ID-VG curves for MOS devices with gate oxide layers formed by prior art methods and by the method of the present invention, respectively. As can be seen from fig. 7A: the current ID corresponding to the voltage VG of 0 at the time of stress (stress)10s of the MOS device in which the gate oxide layer is formed by the method of the related art is significantly increased compared to that at the time of initial (init), indicating that there is significant leakage. As can be seen from fig. 7B, the current ID corresponding to the voltage VG of 0 when the MOS device with the gate oxide layer formed by the method of the present invention is stressed for 10s or even stressed for 100s is still equal to the current ID corresponding to the voltage VG of 0 at the initial time, and there is no significant current increase, which indicates that there is no leakage. Therefore, compared with the prior art, the method can prevent the MOS device from being broken down from the corner of the shallow trench isolation structure to cause electric leakage, and can effectively improve the performance and reliability of the device to a great extent.
The above-described embodiments are possible examples of implementations and are presented merely for a clear understanding of the principles of the invention. Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for improving uniformity of a gate oxide layer, comprising:
(1) providing a semiconductor substrate with a shallow trench isolation structure;
(2) growing a first thermal oxidation layer on the semiconductor substrate in a thermal oxidation mode;
(3) depositing a second deposited oxide layer on the first thermal oxide layer in a high-temperature oxidation mode, so as to form a target grid oxide layer;
(4) and annealing the target grid oxide layer to obtain a final grid oxide layer.
2. The method as claimed in claim 1, wherein the step (2) of growing the first thermal oxide layer is performed at a temperature of 700-900 ℃ and under normal pressure.
3. The method of claim 2, wherein the step (2) of growing the first thermal oxide layer is performed by a dry oxidation process.
4. The method of claim 2, wherein the step (2) of growing the first thermal oxide layer is performed by a wet oxidation process.
5. The method as claimed in claim 1, wherein the step (3) of depositing the second deposited oxide layer is performed at a temperature of 700-900 ℃ and a pressure of 40-60 Pa.
6. The method as claimed in claim 5, wherein the step (3) of depositing the second oxide layer is performed by introducing SiH2Cl2And N2In the case of O gas.
7. The method of claim 1, wherein the final gate oxide layer has a thickness of 180-275A.
8. The method as claimed in claim 7, wherein the thickness of the first thermal oxide layer is 10-25A.
9. The method as claimed in claim 7, wherein the second deposited oxide layer has a thickness of 170-250A.
10. The method for improving the uniformity of a gate oxide layer as claimed in claim 1, further comprising the step (5) of depositing a layer of polysilicon on said final gate oxide layer after said annealing.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030073270A1 (en) * | 2001-10-15 | 2003-04-17 | Yoshiyuki Hisada | Method of fabricating SiC semiconductor device |
| GB2377548B (en) * | 2001-01-05 | 2003-06-18 | Esm Ltd | Method of fabricating a gate dielectric layer for a thin film transistor |
| CN101290882A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of oxide layer of gate capable of enhancing homogeneity |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2377548B (en) * | 2001-01-05 | 2003-06-18 | Esm Ltd | Method of fabricating a gate dielectric layer for a thin film transistor |
| US20030073270A1 (en) * | 2001-10-15 | 2003-04-17 | Yoshiyuki Hisada | Method of fabricating SiC semiconductor device |
| CN101290882A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of oxide layer of gate capable of enhancing homogeneity |
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