TWI574409B - 半導體結構與其形成方法 - Google Patents
半導體結構與其形成方法 Download PDFInfo
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- TWI574409B TWI574409B TW104126493A TW104126493A TWI574409B TW I574409 B TWI574409 B TW I574409B TW 104126493 A TW104126493 A TW 104126493A TW 104126493 A TW104126493 A TW 104126493A TW I574409 B TWI574409 B TW I574409B
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- 239000004065 semiconductor Substances 0.000 title claims description 211
- 238000000034 method Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000000463 material Substances 0.000 claims description 75
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 50
- 229910052796 boron Inorganic materials 0.000 claims description 50
- 239000011358 absorbing material Substances 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 44
- 230000005855 radiation Effects 0.000 claims description 37
- 229910052732 germanium Inorganic materials 0.000 claims description 33
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 33
- 230000003213 activating effect Effects 0.000 claims description 9
- 238000010521 absorption reaction Methods 0.000 claims description 5
- 230000007547 defect Effects 0.000 claims description 5
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- 239000006096 absorbing agent Substances 0.000 claims 1
- 239000002019 doping agent Substances 0.000 description 56
- 238000001994 activation Methods 0.000 description 23
- 230000004913 activation Effects 0.000 description 22
- 230000005684 electric field Effects 0.000 description 12
- 230000000694 effects Effects 0.000 description 9
- 150000001638 boron Chemical class 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052762 osmium Inorganic materials 0.000 description 2
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 1
- HITXEXPSQXNMAN-UHFFFAOYSA-N bis(tellanylidene)molybdenum Chemical compound [Te]=[Mo]=[Te] HITXEXPSQXNMAN-UHFFFAOYSA-N 0.000 description 1
- WGDSTGHBOKMWCA-UHFFFAOYSA-N bis(tellanylidene)zirconium Chemical compound [Te]=[Zr]=[Te] WGDSTGHBOKMWCA-UHFFFAOYSA-N 0.000 description 1
- ZMIGMASIKSOYAM-UHFFFAOYSA-N cerium Chemical compound [Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce][Ce] ZMIGMASIKSOYAM-UHFFFAOYSA-N 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- WXANAQMHYPHTGY-UHFFFAOYSA-N cerium;ethyne Chemical compound [Ce].[C-]#[C] WXANAQMHYPHTGY-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002290 germanium Chemical class 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- SMKQIOCKGHFKQZ-UHFFFAOYSA-N phosphanylidynecerium Chemical compound [Ce]#P SMKQIOCKGHFKQZ-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/02104—Forming layers
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- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Description
本發明係關於半導體材料,更特別關於半導體材料之製程。
半導體裝置的製作通常關於許多製程步驟。舉例來說,製作場效電晶體的製程通常包含掺雜半導體基板,比如將所需雜質添加至基板中以形成源極/汲極接面。許多不同方法可用以掺雜基板,比如離子佈植、擴散、與磊晶成長。此外,在製作半導體裝置於基板上之前,通常需先活化導入基板中的掺質。活化掺質的步驟包含溶解掺質晶格,以及將掺質原子/分子自間隙點位傳輸至基板其晶格結構中的晶格點位。舉例來說,掺質的活化方法可為快速熱回火(RTA)或微秒熱回火(MSA)。
在某些條件下,製作半導體裝置的製程若與微波相關,其包含的電磁波波長通長介於1m至1mm之間(對應0.3至300GHz之間的頻率)。當施加微波至包含電偶極的某一材料如介電材料時,電偶極的方向將改變以對應改變的微波射線電場,且此材料可吸收微波射線以產生熱。材料對微波射線電場的回應,可由複電容率(ε(ω)*)量測,其取決於電場頻率:
在上式中,ω為電場頻率,ε(ω)'為複電容率的實數部份(如介電常數,而ε(ω)"為介電損失因子。此外,ε0指的是真空電容率,εr(ω)'為相對介電常數,而εr(ω)"為相對介電損失因子。
若某一材料可吸收微波射線,則可以損失正切(tanδ)表示:
在上式中,μ'為材料的磁電容率的實數部份,而μ"為磁損失因子。在忽略磁損失因子的情況下(比如μ"=0),材料的損失正切如下:
若某一材料的損失正切小(比如tanδ<0.01),則大部份的微波通過材料(即材料僅吸收少量微波)。若某一材料具有即高的損失正切(比如tanδ>10),則材料反射大部份的微波而僅吸收少量微波。具有中等損失正切的材料(比如10tanδ0.01)才能吸收微波。
本發明一實施例提供之半導體結構,包括:基板,以及源極/汲極接面與基板相連且包含半導體材料,半導體材料之鍺組成含量介於約50%至約95%之間。
本發明一實施例提供之半導體結構,包括:基板;以及源極/汲極接面與基板相連且包含半導體材料,半導體材料具有:較下層,包含鍺;以及較上層,掺雜有硼,且較上層的硼濃度大於較下層的硼濃度。
本發明一實施例提供之半導體結構的形成方法,包括:接收半導體結構的基板,形成源極/汲極接面與基板相連,其中形成源極/汲極接面之步驟包括:形成半導體材料,半導體材料包括鍺,以及以硼掺雜半導體材料,使半導體材料之較上層的硼濃度大於半導體材料之較下層的硼濃度。
d、d1、d2、d3‧‧‧距離
102、204、206、304、306‧‧‧微波吸收材料
104、202、302、404、504‧‧‧半導體結構
308‧‧‧外殼
310‧‧‧微波口
312、314‧‧‧熱源
402、502、506‧‧‧微波吸收層
602、604、606、710、720、730、740、750、760、770、810、820、830、910、920、930、940、1010、1020、1030、1040、1110、1120、1130、1140、1150、1160‧‧‧步驟
1310‧‧‧基板
1310a‧‧‧表面
1310b‧‧‧鰭狀物
1320、1320a‧‧‧閘極
1320b‧‧‧間隔物
1330‧‧‧溝槽定義牆
1340‧‧‧半導體層
1350‧‧‧半導體材料
1360‧‧‧較上層
1370‧‧‧源極/汲極接面
第1圖係一例中,以微波射線活化掺質的示意圖。
第2圖係另一例中,以微波射線活掺質的示意圖。
第3圖係一例中,以微波射線活化掺質之裝置的示意圖。
第4圖係一例中,以微波射線活化掺質的示意圖。
第5圖係另一例中以微波射線活化掺質的示意圖。
第6圖係一例中,以微波射線活化掺質的流程圖。
第7圖係另一例中,以微波射線活化掺質的流程圖。
第8圖係一例中,第7圖之步驟770的流程圖。
第9圖係另一例中,第7圖之步驟770的流程圖。
第10圖係另一例中,第7圖之步驟770的流程圖。
第11圖係另一例中,第7圖之步驟770的流程圖。
第12圖係一例中,濃度對深度的曲線圖。
第13圖係一例中,半導體結構的示意圖。
用於活化掺質的習知技術如RTA與MSA通常需要高製程溫度。舉例來說,RTA的溫度通常高於950℃,而MSA的溫度高於1050℃。上述製程高溫可能不適於某些新型半導體裝置。舉例來說,用於新型互補式金氧半(CMOS)裝置的某些材料如鍺或錫具有低熔點,這將限制製作裝置的製程溫度。
第1圖係一例中,採用微波射線活化掺質的示意圖。如第1圖所示,微波吸收材料102係置於半導體結構104外一段距離d處,且半導體結構104包含掺質。微波射線可施加至微波吸收材料102與半導體結構104,以活化半導體結構104中的掺質。
半導體結構104具有小損失正切值,即無法有效吸收微波射線。另一方面,微波吸收材料102具有較大的損失正切值(比如介於約0.01至約2之間),其可吸收足夠的微波射線並增加半導體結構104上的電場密度。在電場密度增加處,半導體結構104的損失正切值可增加以更有效的吸收微波射線,可活化半導體結構104中的掺質以製作半導體裝置。
舉例來說,半導體結構可包含接面,其具有一定數量的掺質。舉例來說,包含掺質的接面可形成於基板上,其形成方法可為化學氣相沉積(CVD)的磊晶成長,且製程溫度介於約300℃至約600℃之間。微波吸收材料102可回應施加的微波射線,以加強半導體結構104上的電場密度。當形成於半導體結構104中的掺質其偶極越多時,這些偶極將對應施加的微波射線振動及/或轉動。在電場密度增加時,半導體結構104可
吸收更多微波射線。若半導體結構104上的電場密度超過臨界值,則偶極與偶極運動(如振動及/或轉動)將破壞掺質與半導體結構104中的間隙點位之間的鍵結,即活化掺質。微波吸收材料102與半導體結構之間的距離可調整以改善活化掺質。舉例來說,掺質可包含磷、磷為主的分子、鍺、氦、硼、硼為主的分子、或上述之組合。
在一實施例中,施加至微波吸收材料102之微波射
線其頻率可介於約2GHz至約10GHz之間。舉例來說,微波吸收材料102可包含掺雜硼的矽鍺、磷化矽、鈦、鎳、氮化矽、氧化矽、碳化矽、或上述之組合。微波吸收材料102的尺寸可遠大於半導體結構104,使半導體結構104上的電場密度幾乎一致。舉例來說,半導體結構104可包含半導體基板、絕緣層上半導體結構、或半導體薄膜結構。
在另一實施例中,半導體結構104的溫度可維持於
500℃至600℃之間以控制掺質擴散。舉例來說,微波射線可施加至微波吸收材料102與半導體結構104一段時間,比如約40秒至約300秒之間。
第2圖係另一例中,以微波射線活化掺質的示意
圖。如第2圖所示,半導體結構202包含掺質且位於兩個微波吸收材料204與206之間。微波射線可施加至半導體結構202與微波吸收材料204與206,以活化半導體結構202中的掺質。舉例來說,微波吸收材料204與206可具有相同的損失正切值或不同的損失正切值。舉例來說,微波吸收材料204與半導體結構202之間的距離d1,可與微波吸收材料206與半導體結構202之間的
距離d2相同或不同。距離d1與d2可調整以改善活化掺質的效果。在一實施例中,微波吸收材料204可位於半導體結構202的上表面上,而微波吸收材料206可圍於半導體結構202的下表面下。在另一實施例中,微波吸收材料204可位於半導體結構202的側表面上,而微波吸收材料206可位於半導體結構202的另一側表面上。在又一實施例中,多個微波吸收材料可位於半導體結構202之上表面上、下表面下、及一或多個側表面上。
第3圖係一例中,採用微波射線活化掺質之裝置的
示意圖。如第3圖所示,外殼308內的半導體結構302包含掺質且位於兩個微波吸收材料304與306之間。外殼308包含一或多個微波口310以導入微波。舉例來說,外殼308可由金屬材料所組成。微波吸收材料304與306可分別藉由熱源312與314先預熱至預定溫度(比如介於約500℃至約600℃之間),以增加微波吸收材料304與306吸收微波射線的效果。舉例來說,熱源312與314可包含氬燈、氙燈、或鎢-鹵素燈。在另一例中,熱源312與314可包含一或多個電源如矽控整流器。
第4圖係一例中,採用微波射線活化掺質的示意
圖。如第4圖所示,微波吸收層402可形成於半導體結構404上,且半導體結構404包含掺質。微波射線可施加至微波吸收層402與半導體結構404。舉例來說,微波吸收層402形成於半導體結構404上的方法可為磊晶成長(比如CVD)。微波吸收層402的厚度可調整為介於約30nm至約250nm之間,以改善掺質活化的效果。在活化掺質後,可實質上移除微波吸收層402,且移除方法可為蝕刻(如濕蝕刻或乾蝕刻)或化學機械研磨。
第5圖係另一例中,採用微波射線活化掺質的示意
圖。如第5圖所示,微波吸收層502可形成於半導體結構504的上表面上,而另一微波吸收層506可形成於半導體結構504的下表面下,且半導體結構504包含掺質。微波射線可施加至半導體結構504與微波吸收層502及506以活化掺質。在一實施例中,微波吸收層502可形成於半導體結構504的側表面上,而微波吸收層506可形成於半導體結構504的另一側表面上。在另一實施例中,多個微波吸收層可形成於半導體結構504之上表面上、下表面下、及一或多個側表面上。
第6圖係一例中,採用微波射線活化掺質的流程
圖。如第6圖所示,步驟602提供基板,且基板包含多個雜質如掺質。步驟604提供一或多個微波吸收材料。微波吸收材料可增加與半導體結構相關的電場密度。步驟606施加微波射線至微波吸收材料與半導體結構,活化多個掺質以用於製作半導體裝置。微波吸收材料係設置以增加回應微波射線的電場密度,並增加半導體結構對微波射線的吸收以活化掺質。
第13圖係一例中,半導體結構如鰭狀場效電晶體(FinFET)之示意圖。在一實施例中,至少一半導體結構104、202、404、與504為FinFET(如第13圖所示之FinFET)。在另一實施例中,至少一半導體結構104、202、404、與504為平面FET。
第7圖係另一例中,採用微波射線(比如界面極化加熱)活化掺質的流程圖。如第7圖所示,步驟710接收半導體結構(如第1圖所示之半導體結構104)之基板(如第13圖所示之基板1310)。如第13圖所示,基板1310包含表面1310a,與自表面
1310a向上延伸之鰭狀物1310b。在一實施例中,基板1310包含矽、鍺、III-V族化合物、或上述之組合。舉例來說,基板1310包含約95%的矽。
步驟720形成第13圖之半導體結構其閘極1320於
基板1310上。在一實施例中,閘極1320為虛置閘極。在另一實施例中,閘極1320為FinFET之功能閘極。如第13圖所示,閘極1320包含通常延伸橫越鰭狀物1310b之閘極1320a,以及位於閘極1320a之每一側上的間隔物1320b。在一實施例中,閘極1320a為多晶矽或任何合適的金屬材料。舉例來說,金屬材料包含但不限於錫、氮化鉭、鋯矽化物、鉬矽化物、組矽化物、鎳矽化物、氮化鎢、或其他合適的p型功函數金屬材料。
步驟730形成溝槽,其延伸至鰭狀物1310b中。上
述溝槽由溝槽定義牆(如第13圖之半導體結構之溝槽定義牆1330)所定義。在一實施例中,溝槽自鰭狀物1310b之表面向下的深度介於約30nm至約70nm之間。
步驟740形成半導體層(如第13圖之半導體結構之
半導體層1340)於溝槽定義牆1330上,以填入部份溝槽。舉例來說,半導體層1340之厚度介於約5nm至約15nm之間。在一實施例中,半導體層1340包含鍺。半導體層1340亦可包含矽、硼、或上述之組合。舉例來說,半導體層1340為矽鍺或掺雜硼的矽鍺。在某些實施例中,半導體層1340的鍺組成含量小於約50%(比如約35%)。在某些實施例中,半導體層1340之硼濃度介於約1E21原子/cm3至約5E21原子/cm3之間(比如約3.7E21原子/cm3)。
在一實施例中,步驟740包含形成半導體層1340的多個子層,且最外側之子層的鍺組成含量朝最內側之子層的鍺組成含量逐漸增加。在另一實施例中,步驟740包含形成半導體層1340的多個子層,且最外側之子層的硼濃度朝最內側之子層的硼濃度逐漸降低。
步驟750形成半導體材料(如第13圖之半導體結構之半導體材料1350)於半導體層1340上,以實質上填滿溝槽。在一實施例中,半導體材料1350包含鍺。半導體材料1350亦可包含矽、硼、或上述之組合。舉例來說,半導體材料1350為矽鍺或掺雜硼的矽鍺。在某些實施例中,半導體材料1350的鍺組成含量大於半導體層1340的鍺組成含量。舉例來說,半導體材料1350的鍺組成含量介於約50%至約95%之間。在某些實施例中,半導體材料1350的硼濃度小於半導體層1340的硼濃度。舉例來說,半導體材料1350的硼濃度介於約2E20原子/cm3至約1E21原子/cm3之間。
步驟760掺雜硼至半導體材料1350,使半導體材料1350的較上層1360之硼濃度高於半導體材料的較下層之硼濃度。舉例來說,較上層1360的硼濃度介於約1E21原子/cm3至約5E21原子/cm3之間。在一實施例中,較上層1360的硼自鰭狀物1310b之表面向下的深度介於約5nm至約15nm之間。
值得注意的是,溝槽定義牆1330、半導體層1340、與半導體材料1350中至少一者構成半導體結構104之源極/汲極接面1370。在一實施例中,源極/汲極接面1370與閘極1320a之間的距離d3介於約1nm至約9nm之間。
在某些實施例中,源極/汲極接面1370形成於基板(比如基體基板或絕緣層上矽(SOI)基板)上。在其他實施例中,源極/汲極接面1370由基板上延伸至基板中。
步驟770活化掺質如半導體材料1350之鍺或硼,且活化方法如後續所述。
第8圖係一例中,第7圖之步驟770的流程圖。如第8圖所示,步驟810接收微波吸收材料如第1圖之微波吸收材料102。步驟820調整微波吸收材料102與半導體結構104相隔之距離(如第1圖中的距離d),以改善掺質活化的效果。在一實施例中,距離d介於約2mm至約10mm之間。步驟830施加微波射線至微波吸收材料102與半導體結構104以活化掺質。
在步驟830中,微波吸收材料102增加較上層1360之硼對微波射線的吸收程度,使較上層1360的硼產生熱(比如高於1100℃)且活化較上層1360的硼。如此一來,步驟770後可得較高的活化硼濃度(與步驟770前之較上層1360之硼濃度實質上相同),其可用於本發明之半導體結構104之源極/汲極接面1370其半導體材料1350之較上層1360。第12圖係一例中,濃度對深度的曲線圖。如第12圖所示的實施例中,半導體結構104之源極/汲極接面1370其半導體材料1350之較上層1360之活化硼濃度,介於約1E21原子/cm3至約5E21原子/cm3之間。在另一實施例中,步驟770後之半導體材料1350之較下層的活化硼濃度,與步驟770前之半導體材料1350之較下層的硼濃度實質上相同。舉例來說,半導體材料1350之較下層的活化硼濃度介於約2E20原子/cm3至1E21原子/cm3之間。在又一實施例中,步驟
770後之半導體層1340之活化硼濃度,與步驟770前之半導體層1340之硼濃度實質上相同。舉例來說,半導體層1340之活化硼濃度介於約1E21原子/cm3至5E21原子/cm3之間。
此外在步驟830中(比如施加微波射線至微波吸收
材料102與半導體結構104),可減少之前步驟產生的結晶缺陷以達較低的結晶缺陷密度,以用於本發明之半導體結構104之源極/汲極接面1370其半導體材料1350之活化鍺與活化硼。在一實施例中,半導體結構104之源極/汲極接面1370其半導體材料1350之活化鍺的結晶缺陷密度小於約1E12原子/cm3。舉例來說,半導體結構104之源極/汲極接面1370其半導體材料1350之活化鍺的結晶缺陷密度為約1E7原子/cm3。在另一實施例中,半導體結構104之源極/汲極接面1370其半導體材料1350之較上層1360的活化硼之結晶缺陷密度介於約1E5原子/cm3至約1E7原子/cm3之間。
在某些實施例中,步驟770後之半導體層1340其活
化鍺的組成濃度,與步驟前之半導體層1340之鍺的組成濃度實質上相同(比如小於約50%)。在其他實施例中,步驟770後之半導體材料1350其活化鍺的組成濃度,與步驟770前之半導體材料1350之鍺的組成濃度實質上相同(比如介於約50%至95%之間)。
此外在步驟830中(比如施加微波射線至微波吸收
材料102與半導體結構104),基板1310的溫度均維持於約500℃至約600℃之間。如此一來,與活化掺質的習知技藝(如RTA,其加熱整個半導體結構至超過950℃)不同,此實施例選擇性加
熱半導體結構104之源極/汲極接面1370之較上層1360的硼,而半導體結構104之基板1310可維持於較低溫度。基板1310可作為散熱器,使半導體結構104可快速降溫。如此一來,本發明之半導體結構104之源極/汲極接面1370其半導體材料1350之較上層的活化硼具有較淺的深度,比如與步驟770前之較上層1360之硼深度實質上相同。如第12圖所示的實施例中,半導體結構104之源極/汲極接面1370其半導體材料1350之較上層的活化硼自源極/汲極接面1370之表面向下的深度介於約5nm至約15nm之間。
在一實施例中,步驟770(如活化掺質)後的源極/
汲極接面1370其厚度介於約30nm至約70nm之間。此外,步驟770後的半導體層1340維持於實質上相同的厚度(比如介於約5nm至約15nm之間)。此外,步驟770後的源極/汲極接面1370與閘極1320a之間的距離d3介於約1nm至約9nm之間,如第13圖所示。
如第7圖所示,步驟780形成源極/汲極接點(比如第
13圖之半導體結構之源極/汲極接點1380)於源極/汲極接面1370上。源極/汲極接點1380之材料可包含但不限於鎢、鋁、鈦、鎳、鈷、或類似物。
值得注意的是,由於源極/汲極接面1370之半導體
材料1350具有高鍺組成含量,且源極/汲極接面1370之半導體材料1350的較上層1360之硼具有淺深度及高濃度,本發明中源極/汲極接點1380與半導體結構104之源極/汲極接面1370之間具有較低的接觸電阻。在一實施例中,半導體結構104之源極/
汲極接點1380與源極/汲極接面1370之間的接觸電阻小於約5E-9歐姆.cm2。舉例來說,半導體結構104之源極/汲極接點1380與源極/汲極接面1370之間的接觸電阻為約8E-10歐姆.cm2。
第9圖係另一例中,第7圖之步驟770的流程圖。第
9圖中的步驟910接收位於一對微波吸收材料(如第2圖之微波吸收材料204與206)之間的半導體結構(如第2圖之半導體結構202)。步驟920調整微波吸收材料204與半導體結構202之表面之間的距離(如第2圖所示的距離d1),以改善掺質活化的效果。
在一實施例中,距離d1介於約2mm至約10mm之間。步驟930亦調整微波吸收材料206與半導體結構202之表面之間的距離(如第2圖所示的距離d2),以改善掺質活化的效果。在一實施例中,距離d2介於約2mm至約10mm之間。步驟940施加微波射線至微波吸收材料204與206及半導體結構202以活化掺質。
第10圖係另一例中,第7圖之步驟770之流程圖。
如第10圖所示,步驟1010順應性地形成微波吸收層(如第4圖所示之微波吸收層402)於半導體結構(如第4圖所示之半導體結構404)之表面上。步驟1020調整微波吸收層402的厚度(比如介於約30nm至約250nm之間),以改善掺質活化的效果。步驟1030施加微波射線至微波吸收層402與半導體結構404以活化掺質。步驟1040自半導體結構404移除微波吸收層402,且移除方法可為濕蝕刻、乾蝕刻、化學機械研磨、或上述之組合。
第11圖係另一例中,第7圖之步驟770之流程圖。
如第11圖所示,步驟1110順應性地形成第一微波吸收層(如第5圖所示之微波吸收層502)於半導體結構(如第5圖之半導體結構
504)的表面上。步驟1120調整微波吸收層502之厚度(比如介於約30nm至約250nm之間)以改善掺質活化的效果。步驟1130順應性地形成第二微波吸收層(如第5圖所示之微波吸收層506)於半導體結構504的另一表面上。步驟1140調整微波吸收層506之厚度(比如介於約30nm至約250nm之間)以改善掺質活化的效果。步驟1150施加微波射線至微波吸收層502與506及半導體結構504以活化掺質。步驟1160自半導體結構504移除微波吸收層502與506。
在一實施例中,形成與半導體結構的基板相連之
輕掺雜源極/汲極(LDD)。LDD的形成方法包括以多個掺質掺雜半導體結構的一區域;接收微波吸收材料或形成微波吸收材料於半導體結構上;調整微波吸收材料與半導體結構之間的距離或調整微波吸收材料的厚度;以及施加微波射線至微波吸收材料與半導體結構。
上述內容採用實施例揭露本發明,包含最佳模式
使本領域中具有通常知識者得以進行與採用本發明。本發明的可專利範疇可包含本技術領域中具有通常知識者可思及的其他實施例。本技術領域中具有通常知識者應理解,多種實施例並不需依一或多個特定細節實施,且可搭配其他置換及/或額外方法、材料、或構件實施。常見結構、材料、或步驟不未詳述於上述內容,以避免本發明之多種實施例不清楚。圖式中的多種實施例僅用以說明實施例,而不必然依比例繪示。在一或多個實施例中,可依任何合適方式結合特定特徵、結構、材料、或特性。在其他實施例中,可包含及/或省略額外的或揭示之
多種層狀物及/或結構。多種步驟可描述為多個分開的依序步驟以利理解本發明。然而描述的步驟順序並非必然的順序步驟。在特定實施例中,這些步驟不需依描述的步驟順序進行。上述步驟可依不同順序進行(比如依序或同時進行),而不需依實施例的內容進行。此外還可進行多種額外步驟。其他實施例亦可省略某些步驟。
上述內容與下述申請專利範圍可包含用語如左、右、頂、底、上、下、較上、較下、第一、第二、或類似用語。這些用語僅用以描述而非侷限本發明。舉例來說,相對垂直位置的用語如基板或積體電路之裝置側(或主動表面)可稱作基板的「上表面」。以標準地面框架(standard terrestrial frame)作為參照,實際上基板可位於任何方向,使基板的「上」側可低於「下」側,且仍落入用語「上」的涵義中。除非特別規定,本文及申請專利範圍之用語「之上」如第一層位於第二層之上並非指第一層必然直接位於第二層之上,在第一層和第一層之上的第二層之間可能有第三層或其他結構。用語「之下」如第一層位於第二層之下並非指第一層必然直接位於第二層之下,在第二層和第二層之下的第一層之間可能有第三層或其他結構。上述裝置或物品的實施例可於許多位置和方向上製造、使用、或封裝。本技術領域中具有通常知識者依據上述內容,多可對圖式中的多種構件進行多種等效結合及置換。
d‧‧‧距離
102‧‧‧微波吸收材料
104‧‧‧半導體結構
Claims (12)
- 一種半導體結構,包括:一基板;以及一源極/汲極接面與該基板相連且包含一半導體材料,該半導體材料之鍺組成含量介於約50%至約95%之間,其中該半導體材料之鍺的結晶缺陷密度小於約1E12原子/cm3。
- 如申請專利範圍第1項所述之半導體結構,其中:該源極/汲極接面更包括一半導體層,且該半導體層包含鍺;該半導體材料形成於該半導體層上;以及該半導體材料之鍺組成含量大於該半導體層之鍺組成含量。
- 一種半導體結構,包括:一基板;以及一源極/汲極接面與該基板相連且包含一半導體材料,該半導體材料具有:一較下層,包含鍺;以及一較上層,掺雜有硼,且該較上層的硼濃度大於該較下層的硼濃度,其中該較上層之硼的結晶缺陷密度介於約1E5原子/cm3至約1E7原子/cm3之間。
- 如申請專利範圍第3項所述之半導體結構,其中該上層的硼濃度大於約1E21原子/cm3。
- 如申請專利範圍第3項所述之半導體結構,更包括一源極/ 汲極接點形成於該源極/汲極接面上,其中該源極/汲極接點與該源極/汲極接面之接觸電阻小於約5E-9歐姆.cm2。
- 如申請專利範圍第3項所述之半導體結構,其中該較上層之硼自該源極/汲極接面向下之深度介於約5nm至約15nm之間。
- 一種半導體結構的形成方法,包括:接收一半導體結構的一基板;以及形成一源極/汲極接面與該基板相連,其中形成該源極/汲極接面之步驟包括:形成一半導體材料,該半導體材料包括鍺;以硼掺雜該半導體材料,使該半導體材料之一較上層的硼濃度大於該半導體材料之一較下層的硼濃度;以及施加一微波射線至一微波吸收材料與該半導體結構,以活化該半導體材料之鍺與硼,且該微波吸收材料設置以增加半導體材料之鍺與硼對微波射線的吸收。
- 如申請專利範圍第7項所述之半導體結構的形成方法,其中該較上層之硼濃度大於約1E21原子/cm3。
- 如申請專利範圍第7項所述之半導體結構的形成方法,其中:形成該源極/汲極接面之步驟更包括形成一半導體層,該半導體層之鍺組成含量小於該半導體材料之鍺組成含量;以及該半導體材料係形成於該半導體層上。
- 如申請專利範圍第7項所述之半導體結構的形成方法,其中 該半導體材料之鍺組成含量大於約50%。
- 如申請專利範圍第7項所述之半導體結構的形成方法,其中活化該半導體材料之鍺與硼的步驟更包括:形成該微波吸收材料於該半導體結構上;以及調整該微波吸收材料的厚度。
- 如申請專利範圍第7項所述之半導體結構的形成方法,其中活化該半導體材料之鍺與硼的步驟更包括:接收該微波吸收材料;以及調整該微波吸收材料與該半導體結構相隔之距離。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5908313A (en) * | 1996-12-31 | 1999-06-01 | Intel Corporation | Method of forming a transistor |
US20110008952A1 (en) * | 2009-07-07 | 2011-01-13 | Tomonori Aoyama | Method and apparatus for manufacturing semiconductor device |
US20110068407A1 (en) * | 2009-09-24 | 2011-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with Metal Gates and Stressors |
US20120153387A1 (en) * | 2010-12-21 | 2012-06-21 | Murthy Anand S | Transistors with high concentration of boron doped germanium |
US20130248999A1 (en) * | 1999-09-28 | 2013-09-26 | Glenn A. Glass | Contact resistance reduction employing germanium overlayer pre-contact metalization |
US20130270561A1 (en) * | 2012-04-17 | 2013-10-17 | International Business Machines Corporation | Method for forming semiconductor device with epitaxy source and drain regions independent of patterning and loading |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5045898A (en) * | 1988-08-30 | 1991-09-03 | At&T Bell Laboratories | CMOS integrated circuit having improved isolation |
WO1999057344A1 (fr) * | 1998-05-01 | 1999-11-11 | Nippon Steel Corporation | Plaquette de semi-conducteur en silicium et son procede de fabrication |
JP2002280304A (ja) * | 2001-03-22 | 2002-09-27 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
AU2003228925A1 (en) * | 2002-05-10 | 2003-11-11 | Varian Semiconductor Equipment Associates, Inc. | Methods and systems for dopant profiling |
US6949482B2 (en) * | 2003-12-08 | 2005-09-27 | Intel Corporation | Method for improving transistor performance through reducing the salicide interface resistance |
US7598142B2 (en) * | 2007-03-15 | 2009-10-06 | Pushkar Ranade | CMOS device with dual-epi channels and self-aligned contacts |
US8236660B2 (en) * | 2010-04-21 | 2012-08-07 | International Business Machines Corporation | Monolayer dopant embedded stressor for advanced CMOS |
JP2013069977A (ja) * | 2011-09-26 | 2013-04-18 | Toshiba Corp | 半導体装置の製造方法 |
US20130292774A1 (en) * | 2012-05-07 | 2013-11-07 | Globalfoundries Inc. | Method for forming a semiconductor device having raised drain and source regions and corresponding semiconductor device |
US9490128B2 (en) * | 2012-08-27 | 2016-11-08 | Ultratech, Inc. | Non-melt thin-wafer laser thermal annealing methods |
TWI508191B (zh) * | 2013-03-21 | 2015-11-11 | Univ Nat Chiao Tung | 半導體元件製造方法 |
US9601619B2 (en) * | 2013-07-16 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with non-uniform P-type impurity profile |
US9012315B2 (en) * | 2013-08-09 | 2015-04-21 | Taiwan Semiconductor Manufacturing Company Limited | Methods and systems for dopant activation using microwave radiation |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5908313A (en) * | 1996-12-31 | 1999-06-01 | Intel Corporation | Method of forming a transistor |
US20130248999A1 (en) * | 1999-09-28 | 2013-09-26 | Glenn A. Glass | Contact resistance reduction employing germanium overlayer pre-contact metalization |
US20110008952A1 (en) * | 2009-07-07 | 2011-01-13 | Tomonori Aoyama | Method and apparatus for manufacturing semiconductor device |
US20110068407A1 (en) * | 2009-09-24 | 2011-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with Metal Gates and Stressors |
US20120153387A1 (en) * | 2010-12-21 | 2012-06-21 | Murthy Anand S | Transistors with high concentration of boron doped germanium |
US20130270561A1 (en) * | 2012-04-17 | 2013-10-17 | International Business Machines Corporation | Method for forming semiconductor device with epitaxy source and drain regions independent of patterning and loading |
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