TWI567823B - 顯示面板與其製造方法 - Google Patents

顯示面板與其製造方法 Download PDF

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TWI567823B
TWI567823B TW103144723A TW103144723A TWI567823B TW I567823 B TWI567823 B TW I567823B TW 103144723 A TW103144723 A TW 103144723A TW 103144723 A TW103144723 A TW 103144723A TW I567823 B TWI567823 B TW I567823B
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insulating layer
fluoride ion
layer
region
display panel
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TW103144723A
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TW201624567A (zh
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李冠鋒
蔣國璋
顏子旻
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群創光電股份有限公司
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Priority to TW103144723A priority Critical patent/TWI567823B/zh
Priority to US14/958,049 priority patent/US9595537B2/en
Priority to JP2015248383A priority patent/JP6708357B2/ja
Publication of TW201624567A publication Critical patent/TW201624567A/zh
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Publication of TWI567823B publication Critical patent/TWI567823B/zh
Priority to US15/418,964 priority patent/US9917114B2/en

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Description

顯示面板與其製造方法
本發明係關於顯示面板，更特別關於其上的絕緣層。
現有沉積絕緣層(如氧化矽或氮化矽)之步驟中，在重複多次後需清潔沉積腔室。一般而言，清潔沉積腔室的方法係以遠端電漿處理含氟氣體(比如氬氣+NF3)以形成氟離子(F-)，再將氟離子輸送至沉積腔室。然而上述清潔製程將殘留氟離子於沉積腔室中，並混入沉積形成的絕緣層中。上述氟離子累積在絕緣層表面的程度會影響到半導體元件的性能，太多或太少都會有不好的影響，故目前需要調整以改善半導體元件的性能。
本發明一實施例提供之顯示面板，包括：第一基板；第一絕緣層，位於第一基板上；半導體層，位於第一絕緣層上；以及第二絕緣層，位於半導體層與第一絕緣層上，且第二絕緣層具有鄰近第一絕緣層的表面；其中第二絕緣層中與表面相隔0-40nm的第一區域之氟離子增益率介於80%至95%之間。
本發明一實施例提供之顯示面板，包括：第一基板；半導體層，位於第一基板上；第一絕緣層，位於半導體層上；以及第二絕緣層，位於第一絕緣層上，且第二絕緣層具有鄰近第一 基板的表面，其中第二絕緣層中與表面相隔0-40nm的第一區域之氟離子增益率介於80%至95%之間。
本發明一實施例提供之顯示面板的製造方法，包括：(1)以電漿源提供氟離子至沉積腔室中，以清潔沉積腔室；(2)在步驟(1)後，沉積氟離子吸收層於沉積腔室的內壁上；(3)在步驟(2)後，將第一基板傳輸至沉積腔室中，且第一基板上已沉積有第一絕緣層與半導體層；以及(4)在步驟(3)後，沉積第二絕緣層於第一絕緣層與半導體層上。
11‧‧‧遠端電漿源
13‧‧‧沉積腔室
14‧‧‧氟離子吸收層
15‧‧‧第一基板
17‧‧‧半導體層
18‧‧‧表面
19‧‧‧第二絕緣層
20‧‧‧第二基板
30‧‧‧顯示介質
40A、40B、40C、50A、50B‧‧‧薄膜電晶體
41‧‧‧閘極
43‧‧‧第一絕緣層
45A‧‧‧源極
45B‧‧‧汲極
第1至3圖係本發明一實施例中，沉積第二絕緣層的示意圖。
第4圖係本發明第一與第二實施例中，SIMS的量測結果示意圖。
第5A-5C與6A-6B圖係本發明實施例中，薄膜電晶體的結構。
第7圖係本發明實施例中，顯示面板的結構。
本發明一實施例提供一種顯示面板的製造方法。如第1圖所示，遠端電漿源(Remote plasma source)11施加至含氟化學品(如Ar+NF3)以形成氟離子。接著將上述氟離子導入沉積腔室13中，以清潔沉積腔室13。
接著減少沉積腔室13中的氟離子，再將第一基板15傳輸至沉積腔室13中。上述第一基板15已沉積有第一絕緣層43與半導體層17。在本發明一實施例中，第一基板15可為透光(如玻璃、石英、或類似物)或不透光(如晶圓、陶瓷、或類似物)之剛性 無機材質，亦可為塑膠、橡膠、聚酯、聚亞醯胺或聚碳酸酯等可撓性有機材質。在本發明一實施例中，第一絕緣層43可為氧化矽、氮化矽、氮氧化矽、或其組合，半導體層17可為非晶質矽(amorphous Silicon)、多晶矽(poly-Silicon)、氧化銦鎵鋅(Indium-Gallium-Zinc Oxide，IGZO)、氧化銦鎵鋅錫(Indium-Gallium-Zinc-Tin Oxide，IGZTO)、氧化鋅(Zinc oxide，ZnO)、氧化銦鋅錫(Indium-Zinc-Tin Oxide，IZTO)、氧化鎵鋅(Gallium-Zinc Oxide，GZO)、氧化鋅錫(Zinc-Tin Oxide，ZTO)。
在本發明一實施例中，上述減少沉積腔室13中的氟離子之步驟，包括使用一泵浦將未反應之氟離子以及與氟離子反應而形成之化合物抽離沉積腔室13，以及沉積氟離子吸收層14於沉積腔室13的內壁上，如第2圖所示。一般而言，為避免氟離子吸收層14影響之後形成的第二絕緣層19(見第3圖)組成，氟離子吸收層14之組成與第二絕緣層19之組成較佳相同。舉例來說，若後續形成之第二絕緣層19包含氧化矽，則氟離子吸收層14亦為氧化矽。若後續形成之第二絕緣層19包含氮化矽，則氟離子吸收層14亦為氮化矽。若後續形成之第二絕緣層19包含氮氧化矽，則氟離子吸收層14亦為包含氮化矽與氧化矽之雙層結構。然上述僅為較佳實施例而已，氟離子吸收層14與第二絕緣層19的組成也可不同。本發明不同實施例中，氟離子吸收層14為厚度介於200至1000nm之間的氧化矽層、氮化矽層、或氮化矽層與氧化矽層之雙層結構。
接著如第3圖所示，沉積第二絕緣層19於第一絕緣層43與半導體層17上，且第二絕緣層19具有鄰近第一絕緣層43的表 面18。如前所述，第二絕緣層19可為氧化矽、氮化矽、氮氧化矽、或其組合。由於在沉積第二絕緣層19前，於沉積腔室13的內壁上沉積氟離子吸收層14，可以減少沉積腔室13中的氟離子，因此可有效降低第二絕緣層19中的氟離子累積在表面18的濃度。
在本發明另一實施例中，半導體層17係位於第一絕緣層43與第一基板15之間。後續形成氟離子吸收層14與沉積第二絕緣層19之步驟與前述類似，在此不贅述。
在以下實施例中，SIMS(Secondary Ion Mass Spectrometry)被使用來量測氟離子在第二絕緣層19中的含量，且量測的區域位於第一基板的非顯示區。雖然量測的區域位於第一基板的非顯示區，但在沉積製程中，第二絕緣層是整面的形成在顯示區與非顯示區中，因此，第二絕緣層在非顯示區的氟離子含量分布會相同於第二絕緣層在顯示區的氟離子含量分布。實施例的量測條件如下：Apparatus used：CAMECA IMS 6F
Source：Cs+
Energy：15KeV
Collected area(in diameter)：30μm
SIMS的量測結果顯示，在實施例中，第二絕緣層19中與表面18不同距離處具有不同的氟離子含量，其中，SIMS所偵測到的氟離子訊號強度係以每秒計數值(counts per second)為單位。有鑑於SIMS會因為使用不同偵測離子源而造成氟離子訊號強度不一致的問題，本發明提出一種不受偵測離子源種類影響的氟離子含量的量測方法，其係將總量測區域中某一深度下的氟離子 訊號強度扣除氟離子背景強度，以得到該深度下的氟離子校正值。若將氟離子校正值對總量測區域所涵蓋的深度做積分，即為總量測區域的氟離子增益值。更進一步，若將氟離子校正值對一被定義區域所涵蓋的深度做積分，再除以總量測區域的氟離子增益值，即為該區域的氟離子增益率。在本發明中，總量測區域被定義為第二絕緣層中與表面相隔0~80nm的區域，而氟離子背景強度被定義為第二絕緣層中與表面相隔40~80nm的第二區域B所量測到的最低的氟離子訊號強度。
在第一實施例中，在抽離沉積腔室13中的氟離子後，於沉積腔室的內壁上沉積厚度約200nm的氧化矽層，以減少沉積腔室13中的氟離子。由於先減少沉積腔室13中的氟離子，可降低第二絕緣層19靠近表面18的氟離子濃度。SIMS的量測結果，如第4圖所示，第二絕緣層19中與表面18相隔0-40nm的第一區域A之氟離子訊號強度的極大值為1.79E6(C/S)，而第二絕緣層19中與表面相隔40~80nm的第二區域B所量測到的最低的氟離子訊號強度係為氟離子背景強度IB。將第一實施例中隨距離變化的氟離子訊號強度(如實線所示)扣除氟離子背景強度IB後得到的氟離子校正值對第一區域A(與表面18相距0~40nm)做積分，即為第一區域A的氟離子增益值。若將氟離子校正值對總量測區域T(與表面18相距0~80nm)做積分，即為總量測區域T的氟離子增益值。將第一區域A的氟離子增益值除以總量測區域T的氟離子增益值，即為第一區域A的氟離子增益率，經計算後其值約為88%，且第二絕緣層19中與表面18相隔40-80nm的第二區域B之氟離子增益率約為12%。此外，增加沉積於沉積腔室內壁上的氧化矽層厚度，可進一步降 低第一區域A之氟離子增益率。若預先沉積厚度約1000nm的氧化矽層，則第一區域A之氟離子增益率可為82%，而第二區域B之氟離子增益率為18%。也就是說，若使用氧化矽作為氟離子吸收層14，第一區域A之氟離子增益率與第二區域B之氟離子增益率的比值約為4.6~7.3之間。
在第二實施例中，在抽離沉積腔室13中的氟離子後，於沉積腔室的內壁上沉積厚度約200nm的氮化矽層，以減少沉積腔室13中的氟離子。由於先減少沉積腔室13中的氟離子，可降低第二絕緣層19靠近表面18的氟離子濃度。SIMS的量測結果，如第4圖所示，第二絕緣層19中與表面18相隔0-40nm的第一區域A之氟離子訊號強度的極大值為8.09E5(C/S)，而第二絕緣層19中與表面18相隔40~80nm的第二區域B所量測到的最低的氟離子訊號強度係為氟離子背景強度IC(IB與IC的值在第4圖中近乎重疊)。將第二實施例中隨距離變化的氟離子訊號強度(如虛線所示)扣除氟離子背景強度IC後得到的氟離子校正值對第一區域A(與表面18相距0~40nm)做積分，即為第一區域A的氟離子增益值。若將氟離子校正值對總量測區域T(與表面相距0~80nm)做積分，即為總量測區域T的氟離子增益值。將第一區域A的氟離子增益值除以總量測區域T的氟離子增益值，即為第一區域A的氟離子增益率，經計算後其值約為95%，且第二絕緣層19中與表面18相隔40-80nm的第二區域B之氟離子增益率約為5%。同樣的，增加預先沉積的氮化矽層的厚度，可再降低第一區域A之氟離子增益率。若預先沉積厚度約1000nm的氮化矽層，則第一區域A之氟離子增益率可為88%，而第二區域B之氟離子增益率為12%。也就是說，若使用氮 化矽作為氟離子吸收層14，第一區域A之氟離子增益率與第二區域B之氟離子增益率的比值約為7.3~19.0。
在第三實施例中，在抽離沉積腔室13中的氟離子後，於沉積腔室的內壁上沉積厚度約200nm的氮化矽層與氧化矽層之雙層結構，以減少沉積腔室13中的氟離子。由於先減少沉積腔室13中的氟離子，可降低第二絕緣層19靠近表面18的氟離子濃度。SIMS的量測結果顯示，第二絕緣層19中與表面18相隔0-40nm的第一區域A之氟離子訊號強度的極大值為2.57E6(C/S)，且第二絕緣層19中與表面18相隔0-40nm的第一區域A之氟離子增益率約為83%，且第二絕緣層19中與表面18相隔40-80nm的第二區域B之氟離子增益率約為17%。同樣的，增加預先沉積的氮化矽層與氧化矽層之雙層結構的厚度，可再降低第一區域A之氟離子增益率。若預先沉積厚度約1000nm的氮化矽層與氧化矽層，則第一區域A之氟離子增益率可為80%，而第二區域B之氟離子增益率為20%。也就是說，若使用氮化矽與氧化矽作為氟離子吸收層14，第一區域A之氟離子增益率與第二區域B之氟離子增益率的比值約為4.0~4.9。
總結來說，在第一至第三實施例中，若先在沉積腔室13中預先沉積一氟離子吸收層14，再沉積第二絕緣層19，可降低第二絕緣層19靠近表面18的氟離子濃度，電性量測結果顯示，在第一至第三實施例中，薄膜電晶體的臨界電壓介於0V至1V之間，且磁滯值介於0V至0.5V之間。
SIMS量測結果顯示，不同成分的氟離子吸收層14都具有降低氟離子集中在第二絕緣層19的表面18的效果，差異僅在 於程度不同。由前述可知，若使用氮化矽與氧化矽的雙層結構作為氟離子吸收層14，則第二絕緣層19中與表面18相隔0-40nm的第一區域A之氟離子增益率為約80%~83%。若使用氧化矽作為氟離子吸收層14，則第二絕緣層19中與表面18相隔0-40nm的第一區域A之氟離子增益率為約82%~88%。使用氮化矽作為氟離子吸收層14，則第二絕緣層19中與表面18相隔0-40nm的第一區域A之氟離子增益率為約88%~95%。
由上述可知，先減少沉積腔室13中的氟離子，可有效降低後續沉積於半導體層17上的第二絕緣層19之氟離子累積在表面18的濃度，進而改善薄膜電晶體的性質(如臨界電壓與磁滯值)。
上述結構可進一步應用於各種型態的薄膜電晶體。如第5A圖所示，當薄膜電晶體40A為底閘極結構時，可先形成閘極41與第一絕緣層43於第一基板15上，再形成半導體層17於第一絕緣層43上。接著圖案化半導體層17，以作為薄膜電晶體40A之通道層。之後形成源極45A與汲極45B於圖案化之半導體層17兩側上，以電性連接圖案化之半導體層17(即薄膜電晶體40B之通道層)的兩側。接著形成第二絕緣層19於第一絕緣層43、源極45A、汲極45B、與圖案化之半導體層17上。在形成第二絕緣層19前，需先減少沉積腔室13中的氟離子如前述。
如第5B圖所示，當薄膜電晶體40B為底閘極結構時，可先形成閘極41與第一絕緣層43於第一基板15上，再形成源極45A與汲極45B於閘極41兩側上的第一絕緣層43上。接著形成半導體層17於上述結構上，再圖案化半導體層17以形成薄膜電晶體 40B之通道層。上述源極45A與汲極45B電性連接圖案化之半導體層17的兩側。接著形成第二絕緣層19於圖案化之半導體層17、源極45A、與汲極45B上。在形成第二絕緣層19前，需先減少沉積腔室13中的氟離子如前述。
如第5C圖所示，當薄膜電晶體40C為底閘極結構時，可先形成閘極41與第一絕緣層43於第一基板15上，再形成半導體層17於第一絕緣層43上，並圖案化半導體層17以作為薄膜電晶體40C之通道層。接著形成第二絕緣層19於半導體層17上。在形成第二絕緣層19前，需先減少沉積腔室13中的氟離子如前述。接著圖案化第二絕緣層19以露出半導體層17之兩側，再形成源極45A與汲極45B分別電性連接至半導體層17的兩側。
如第6A圖所示，當薄膜電晶體50A為頂閘極結構時，可先形成源極45A與汲極45B於半導體層17兩側上，且上述源極45A與45B電性連接半導體層17的兩側。半導體層17即薄膜電晶體50A之通道層。接著形成第一絕緣層43於半導體層17、源極45A、與汲極45B上。接著形成閘極41於第一絕緣層43上。最後形成第二絕緣層19於閘極41與第一絕緣層43上，其中，第二絕緣層19具有鄰近第一基板15的表面18，形成第二絕緣層19前，需先減少沉積腔室13中的氟離子如前述。
如第6B圖所示，當薄膜電晶體50B為頂閘極結構時，可先形成半導體層17，並形成絕緣層與閘極層覆蓋半導體層17。接著圖案化絕緣層與閘極層，以形成第一絕緣層43與閘極41覆蓋半導體層17之中心部份。接著進行佈植製程，掺雜半導體層17的兩側，以定義源極45A與汲極45B。接著形成第二絕緣層19於第一 絕緣層43、閘極41與掺雜之半導體層(源極45A與汲極45B)上，其中，第二絕緣層19具有鄰近第一基板15的表面18。形成第二絕緣層19前，需先減少沉積腔室13中的氟離子如前述。
如第7圖所示，本發明一實施例的顯示面板更包含一第二基板20，以及位於該第一基板15與第二基板20之間的顯示介質30，其中，顯示介質可為液晶層或OLED元件。而第二基板20可為透光(如玻璃、石英、或類似物)之剛性無機材質，亦可為塑膠、橡膠、聚酯、聚亞醯胺或聚碳酸酯等可撓性有機材質。
雖然本發明已以數個實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
11‧‧‧遠端電漿源
13‧‧‧沉積腔室
14‧‧‧氟離子吸收層
15‧‧‧第一基板
17‧‧‧半導體層
18‧‧‧表面
19‧‧‧第二絕緣層
43‧‧‧第一絕緣層

Claims (20)

  1. 一種顯示面板，包括：一第一基板；一第一絕緣層，位於該第一基板上；一半導體層，位於該第一絕緣層上；以及一第二絕緣層，位於該半導體層與該第一絕緣層上，且該第二絕緣層具有一鄰近該第一絕緣層的表面；其中該第二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於80%至95%之間，其中，該第一區域之氟離子增益率，係為氟離子校正值於該第一區域的積分值，除以氟離子校正值於該第二絕緣層中與該表面相隔0~80nm的總量測區域的積分值，其中，該氟離子校正值係為該第二絕緣層中某一深度下的氟離子訊號強度扣除一氟離子背景強度，其中，該氟離子背景強度為該第二絕緣層中與該表面相隔40~80nm的第二區域所量測到的最低的氟離子訊號強度。
  2. 如申請專利範圍第1項所述之顯示面板，其中，該第二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於80%至83%之間。
  3. 如申請專利範圍第1項所述之顯示面板，其中，該第二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於82%至88%之間。
  4. 如申請專利範圍第1項所述之顯示面板，其中，該第二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於88%至95%之間。
  5. 如申請專利範圍第1項所述之顯示面板，更包括：一閘極，位於該第一基板與該第一絕緣層之間；以及一源極與一汲極，位於該第一絕緣層上，且分別電性連接至該半導體層之兩側，其中該第二絕緣層覆蓋該第一絕緣層、該半導體層、該源極、與該汲極。
  6. 如申請專利範圍第1項所述之顯示面板，更包括：一閘極，位於該第一基板與該第一絕緣層之間；以及一源極與一汲極，位於該第一絕緣層上，其中該半導體層係位於該源極與該汲極上，並電性連接至該源極與該汲極。
  7. 如申請專利範圍第1項所述之顯示面板，更包括：一閘極，位於該第一基板與該第一絕緣層之間；以及一源極與一汲極，位於該第一絕緣層上並分別對應該半導體層之兩側，該源極與該汲極分別穿過該第一絕緣層以電性連接至該半導體層。
  8. 如申請專利範圍第1項所述之顯示面板，更包括：一第二基板；以及一顯示介質，位於該第一基板與該第二基板之間。
  9. 一種顯示面板，包括：一第一基板；一半導體層，位於該第一基板上；一第一絕緣層，位於該半導體層上；以及一第二絕緣層，位於該第一絕緣層上，且該第二絕緣層具有一鄰近該第一基板的表面，其中該第二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於80%至95%之間，其中，該第一區域之氟離子增益率，係為氟離子校正值於該第一區域的積分值，除以氟離子校正值於該第二絕緣層中與該表面相隔0~80nm的總量測區域的積分值，其中，該氟離子校正值係為該第二絕緣層中某一深度下的氟離子訊號強度扣除一氟離子背景強度，其中，該氟離子背景強度為該第二絕緣層中與該表面相隔40~80nm的第二區域所量測到的最低的氟離子訊號強度。
  10. 如申請專利範圍第9項所述之顯示面板，其中，該第二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於80%至83%之間。
  11. 如申請專利範圍第9項所述之顯示面板，其中，該第二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於82%至88%之間。
  12. 如申請專利範圍第9項所述之顯示面板，其中，該第 二絕緣層中與該表面相隔0-40nm的第一區域之氟離子增益率介於88%至95%之間。
  13. 如申請專利範圍第9項所述之顯示面板，更包括：一閘極，位於該第一絕緣層與該第二絕緣層之間；以及一源極與一汲極，位於該第一基板上，且分別電性連接至該半導體層之兩側。
  14. 如申請專利範圍第9項所述之顯示面板，更包括：一閘極，位於該第一絕緣層與該第二絕緣層之間；其中該半導體層之兩側具有摻雜物以作為源極區與汲極區，且該第二絕緣層覆蓋該閘極、該源極區、與該汲極區。
  15. 如申請專利範圍第9項所述之顯示面板，更包括：一第二基板；以及一顯示介質，位於該第一基板與該第二基板之間。
  16. 一種顯示面板的製造方法，包括：(1)以一遠端電漿源提供氟離子至一沉積腔室中，以清潔該沉積腔室；(2)在步驟(1)後，沉積一氟離子吸收層於該沉積腔室的內壁上；(3)在步驟(2)後，將一第一基板傳輸至該沉積腔室中，且該第一基板上具有一第一絕緣層與一半導體層；以及(4)在步驟(3)後，沉積一第二絕緣層於該半導體層與該第一絕緣層上。
  17. 如申請專利範圍第16項所述之顯示面板的製造方法，其中該第二絕緣層包括氧化矽、氮化矽、或氮氧化矽層。
  18. 如申請專利範圍第16項所述之顯示面板的製造方法，其中該第二絕緣層為氧化矽層，而該氟離子吸收層包括200至1000nm之氧化矽層。
  19. 如申請專利範圍第16項所述之顯示面板的製造方法，其中該第二絕緣層為氮化矽層，而該氟離子吸收層包括200至1000nm之氮化矽層。
  20. 如申請專利範圍第16項所述之顯示面板的製造方法，其中該第二絕緣層為氮氧化矽層，而該氟離子吸收層包括200至1000nm之氧化矽層與氮化矽層的雙層結構。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120045904A1 (en) * 2010-08-20 2012-02-23 Applied Materials, Inc. Methods for forming a hydrogen free silicon containing dielectric film
TW201306100A (zh) * 2011-06-16 2013-02-01 Semiconductor Energy Lab 半導體裝置以及該半導體裝置的製造方法
US20140230730A1 (en) * 2004-04-12 2014-08-21 Applied Materials, Inc. Gas diffusion shower head design for large area plasma enhanced chemical vapor deposition
US20140256070A1 (en) * 2013-03-11 2014-09-11 Applied Materials, Inc. Plasma curing of pecvd hmdso film for oled applications
TW201448230A (zh) * 2013-06-03 2014-12-16 Renesas Electronics Corp 半導體裝置及半導體裝置之製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2708533B2 (ja) * 1989-03-14 1998-02-04 富士通株式会社 Ｃｖｄ装置の残留ガス除去方法
JPH0867984A (ja) * 1994-08-26 1996-03-12 Iwatani Internatl Corp プラズマｃｖｄでのクリーニング方法
US6020035A (en) * 1996-10-29 2000-02-01 Applied Materials, Inc. Film to tie up loose fluorine in the chamber after a clean process
TW460943B (en) * 1997-06-11 2001-10-21 Applied Materials Inc Reduction of mobile ion and metal contamination in HDP-CVD chambers using chamber seasoning film depositions
JP2001242803A (ja) * 2000-02-29 2001-09-07 Sony Corp 表示装置及びその製造方法
JP5697534B2 (ja) * 2010-05-14 2015-04-08 株式会社半導体エネルギー研究所 トランジスタの作製方法
TWI654764B (zh) * 2010-11-11 2019-03-21 日商半導體能源研究所股份有限公司 半導體裝置及其製造方法
JP2013004777A (ja) * 2011-06-17 2013-01-07 Renesas Electronics Corp 半導体装置の製造方法および成膜装置
JP6059566B2 (ja) * 2012-04-13 2017-01-11 株式会社半導体エネルギー研究所 半導体装置の作製方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140230730A1 (en) * 2004-04-12 2014-08-21 Applied Materials, Inc. Gas diffusion shower head design for large area plasma enhanced chemical vapor deposition
US20120045904A1 (en) * 2010-08-20 2012-02-23 Applied Materials, Inc. Methods for forming a hydrogen free silicon containing dielectric film
TW201306100A (zh) * 2011-06-16 2013-02-01 Semiconductor Energy Lab 半導體裝置以及該半導體裝置的製造方法
US20140256070A1 (en) * 2013-03-11 2014-09-11 Applied Materials, Inc. Plasma curing of pecvd hmdso film for oled applications
TW201448230A (zh) * 2013-06-03 2014-12-16 Renesas Electronics Corp 半導體裝置及半導體裝置之製造方法

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