TWI562306B - Semiconductor device and method of forming rdl over contact pad with high alignment tolerance or reduced interconnect pitch - Google Patents
Semiconductor device and method of forming rdl over contact pad with high alignment tolerance or reduced interconnect pitchInfo
- Publication number
- TWI562306B TWI562306B TW100125422A TW100125422A TWI562306B TW I562306 B TWI562306 B TW I562306B TW 100125422 A TW100125422 A TW 100125422A TW 100125422 A TW100125422 A TW 100125422A TW I562306 B TWI562306 B TW I562306B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- contact pad
- alignment tolerance
- over contact
- high alignment
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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US36781410P | 2010-07-26 | 2010-07-26 | |
US13/181,412 US9202713B2 (en) | 2010-07-26 | 2011-07-12 | Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch |
Publications (2)
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TW201209978A TW201209978A (en) | 2012-03-01 |
TWI562306B true TWI562306B (en) | 2016-12-11 |
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TW100125422A TWI562306B (en) | 2010-07-26 | 2011-07-19 | Semiconductor device and method of forming rdl over contact pad with high alignment tolerance or reduced interconnect pitch |
Country Status (4)
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US (1) | US9202713B2 (zh) |
CN (1) | CN102347253B (zh) |
SG (1) | SG177860A1 (zh) |
TW (1) | TWI562306B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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US8642446B2 (en) * | 2010-09-27 | 2014-02-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming protective structure around semiconductor die for localized planarization of insulating layer |
US9620413B2 (en) | 2012-10-02 | 2017-04-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
US9721862B2 (en) * | 2013-01-03 | 2017-08-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages |
US10204876B2 (en) | 2013-03-07 | 2019-02-12 | Maxim Integrated Products, Inc. | Pad defined contact for wafer level package |
US9275925B2 (en) | 2013-03-12 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
US9799590B2 (en) * | 2013-03-13 | 2017-10-24 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package |
US9322848B2 (en) | 2013-07-03 | 2016-04-26 | Globalfoundries Inc. | Ball grid array configuration for reliable testing |
JP6300533B2 (ja) * | 2014-01-15 | 2018-03-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
TWI641094B (zh) * | 2014-09-17 | 2018-11-11 | 矽品精密工業股份有限公司 | 基板結構及其製法 |
DE102015109856A1 (de) * | 2015-06-19 | 2016-12-22 | Danfoss Silicon Power Gmbh | Verfahren zum Herstellen einer für die Anbindung eines elektrischen Leiters geeigneten metallischen Kontaktfläche zur Kontaktierung eines Leistungshalbleiters, Leistungshalbleiter, Bond Buffer und Verfahren zur Herstellung eines Leistungshalbleiters |
US9947631B2 (en) * | 2015-10-14 | 2018-04-17 | Intel Corporation | Surface finishes for interconnection pads in microelectronic structures |
US10325870B2 (en) * | 2017-05-09 | 2019-06-18 | International Business Machines Corporation | Through-substrate-vias with self-aligned solder bumps |
KR102019355B1 (ko) | 2017-11-01 | 2019-09-09 | 삼성전자주식회사 | 반도체 패키지 |
Citations (2)
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US20050017343A1 (en) * | 2003-07-23 | 2005-01-27 | Kwon Yong-Hwan | Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same |
US20090283905A1 (en) * | 2008-03-19 | 2009-11-19 | Hsiang-Ming Huang | Conductive structure of a chip |
Family Cites Families (13)
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US4617193A (en) * | 1983-06-16 | 1986-10-14 | Digital Equipment Corporation | Planar interconnect for integrated circuits |
JPS6450443A (en) * | 1987-08-20 | 1989-02-27 | Toshiba Corp | Semiconductor device |
US5300461A (en) * | 1993-01-25 | 1994-04-05 | Intel Corporation | Process for fabricating sealed semiconductor chip using silicon nitride passivation film |
JP2002016065A (ja) | 2000-06-29 | 2002-01-18 | Toshiba Corp | 半導体装置 |
US6258705B1 (en) | 2000-08-21 | 2001-07-10 | Siliconeware Precision Industries Co., Ltd. | Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip |
US20030218246A1 (en) * | 2002-05-22 | 2003-11-27 | Hirofumi Abe | Semiconductor device passing large electric current |
TWI223882B (en) | 2003-06-30 | 2004-11-11 | Advanced Semiconductor Eng | Bumping process |
US6998335B2 (en) * | 2003-12-13 | 2006-02-14 | Chartered Semiconductor Manufacturing, Ltd | Structure and method for fabricating a bond pad structure |
US8791006B2 (en) | 2005-10-29 | 2014-07-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming an inductor on polymer matrix composite substrate |
US8158510B2 (en) * | 2009-11-19 | 2012-04-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming IPD on molded substrate |
US7528069B2 (en) | 2005-11-07 | 2009-05-05 | Freescale Semiconductor, Inc. | Fine pitch interconnect and method of making |
US8343809B2 (en) * | 2010-03-15 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die |
US8183095B2 (en) * | 2010-03-12 | 2012-05-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation |
-
2011
- 2011-07-12 US US13/181,412 patent/US9202713B2/en active Active
- 2011-07-18 SG SG2011051802A patent/SG177860A1/en unknown
- 2011-07-19 TW TW100125422A patent/TWI562306B/zh active
- 2011-07-26 CN CN201110255476.6A patent/CN102347253B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050017343A1 (en) * | 2003-07-23 | 2005-01-27 | Kwon Yong-Hwan | Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same |
US20090283905A1 (en) * | 2008-03-19 | 2009-11-19 | Hsiang-Ming Huang | Conductive structure of a chip |
Also Published As
Publication number | Publication date |
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US20120018874A1 (en) | 2012-01-26 |
US9202713B2 (en) | 2015-12-01 |
SG177860A1 (en) | 2012-02-28 |
CN102347253B (zh) | 2017-06-09 |
CN102347253A (zh) | 2012-02-08 |
TW201209978A (en) | 2012-03-01 |
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