TWI554171B - Method for fabricating buried-type conductive wiring - Google Patents

Method for fabricating buried-type conductive wiring Download PDF

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TWI554171B
TWI554171B TW103131768A TW103131768A TWI554171B TW I554171 B TWI554171 B TW I554171B TW 103131768 A TW103131768 A TW 103131768A TW 103131768 A TW103131768 A TW 103131768A TW I554171 B TWI554171 B TW I554171B
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conductive
conductive layer
pattern
substrate
fabricating
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TW103131768A
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TW201611689A (en
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張啟民
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欣興電子股份有限公司
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埋入式導電配線的製作方法 Buried conductive wiring manufacturing method

本發明係有關於一種導電配線的製作方法,尤指一種厚膜導電配線的製作方法。 The invention relates to a method for manufacturing a conductive wiring, in particular to a method for manufacturing a thick film conductive wiring.

近年隨電子技術的進展,供搭載諸如半導體元件、積體電路、電子零件等之用的配線基板,除輕薄短小化(Miniaturization)之外,亦朝高積體化、高輸出化及高速化急速進展。尤其,上述的配線基板的製程亦朝金屬配線細微化開發。例如,當在基材上形成諸如銅等金屬配線之際,一般可以採用濺鍍成膜與電解電鍍等製程。 In recent years, with the advancement of electronic technology, wiring boards for mounting semiconductor devices, integrated circuits, and electronic components have been rapidly integrated, high-output, and high-speed, in addition to miniaturization. progress. In particular, the above-described wiring board process has also been developed to miniaturize metal wiring. For example, when a metal wiring such as copper is formed on a substrate, a process such as sputtering film formation and electrolytic plating can be generally employed.

當以習知技術在基材上製作厚膜金屬配線時,因金屬配線的厚度會影響蝕刻能力,往往因蝕刻不潔影響產品製作良率,甚至無法製作出預期銅厚、配線間距的產品。 When a thick film metal wiring is formed on a substrate by a conventional technique, the thickness of the metal wiring affects the etching ability, and the etching yield is often affected by the uncleanness of the product, and it is impossible to produce a product having an expected copper thickness and wiring pitch.

本發明實施例在於提供一種厚膜導電配線的製作方法。 Embodiments of the present invention provide a method of fabricating a thick film conductive wiring.

本發明其中一實施例所提供的一種埋入式導電配線的製作方法。包括下列步驟。首先,提供一基材。接著,將所述基材進行圖案化處理,以於所述基材的上表面形成一第一凹槽區域。然後,於所述基材的上表面形成一導電層,其中所述導電層包括一導電圖案,所述導電圖案至少填入所述第一凹槽區域內,所述導電圖案在厚度方向上凸出於所述基材的上表面,所述導電圖案的側壁形成一第二凹槽區域,且所述第二凹槽區域內具有所述導電層的部分厚度。接著,於所述導電層上形成一第一犧牲圖案,其 中所述第一犧牲圖案至少填入所述第二凹槽區域內,所述第一犧牲圖案在厚度方向上凸出於所述導電圖案的上表面,所述第一犧牲圖案的側壁形成一第三凹槽區域,且所述第三凹槽區域暴露一部分的所述導電圖案。然後,將所述導電層進行電鍍處理,使所述第三凹槽區域所暴露的所述導電圖案增厚。最後,移除所述第一犧牲圖案,並且,移除所述第二凹槽區域內的所述導電層。 A method of fabricating a buried conductive wiring according to an embodiment of the present invention. Includes the following steps. First, a substrate is provided. Next, the substrate is patterned to form a first recessed region on the upper surface of the substrate. And forming a conductive layer on the upper surface of the substrate, wherein the conductive layer comprises a conductive pattern, the conductive pattern is at least filled in the first recessed region, and the conductive pattern is convex in a thickness direction The sidewall of the conductive pattern forms a second recessed region for the upper surface of the substrate, and the second recessed region has a partial thickness of the conductive layer. And forming a first sacrificial pattern on the conductive layer, The first sacrificial pattern is filled in at least the second recessed region, the first sacrificial pattern protrudes from an upper surface of the conductive pattern in a thickness direction, and sidewalls of the first sacrificial pattern form a a third recessed area, and the third recessed area exposes a portion of the conductive pattern. Then, the conductive layer is subjected to a plating treatment to thicken the conductive pattern exposed by the third recess region. Finally, the first sacrificial pattern is removed, and the conductive layer in the second recessed region is removed.

透過本發明實施例所提供的埋入式導電配線的製作方法,可不受限於蝕刻能力而製作出配線密度高、配線寬度窄的厚膜導電配線。 According to the method for fabricating the buried conductive wiring according to the embodiment of the present invention, a thick film conductive wiring having a high wiring density and a narrow wiring width can be produced without being limited to the etching ability.

為使能更進一步瞭解本發明的特徵及技術內容,請參閱以下有關本發明的詳細說明與附圖,然而所附圖式僅提供參考與說明用,並非用來對本發明加以限制者。 For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying drawings.

1‧‧‧基材 1‧‧‧Substrate

101‧‧‧基材的上表面 101‧‧‧ Upper surface of the substrate

2‧‧‧第一凹槽區域 2‧‧‧First groove area

3”‧‧‧初始導電層 3"‧‧‧ initial conductive layer

3、3’‧‧‧導電層 3, 3'‧‧‧ conductive layer

31、31’‧‧‧導電圖案 31, 31'‧‧‧ conductive patterns

301、301’‧‧‧上表面 301, 301’‧‧‧ upper surface

4、4’‧‧‧第二凹槽區域 4, 4'‧‧‧ second groove area

5‧‧‧第一犧牲圖案 5‧‧‧First Sacrifice Pattern

501‧‧‧上表面 501‧‧‧ upper surface

6‧‧‧第三凹槽區域 6‧‧‧ Third groove area

7‧‧‧第二犧牲圖案 7‧‧‧Second sacrificial pattern

8‧‧‧蝕刻阻擋層 8‧‧‧etching barrier

H1、H2‧‧‧厚度 H1, H2‧‧‧ thickness

H3‧‧‧高度 H3‧‧‧ Height

S1~S7‧‧‧步驟 S1~S7‧‧‧ steps

圖1A至圖1J顯示本發明一實施例之埋入式導電配線的製作方法的步驟流程。 1A to 1J are flowcharts showing the steps of a method of fabricating a buried conductive wiring according to an embodiment of the present invention.

圖2為本發明另一實施例之埋入式導電配線的製作方法的步驟流程圖。 2 is a flow chart showing the steps of a method for fabricating a buried conductive wiring according to another embodiment of the present invention.

請參閱圖1A至圖1J,圖1A至圖1J為本發明一實施例之具有埋入式導電配線的基板在製作過程中的側視示意圖,並且,圖1A至圖1J顯示本發明一實施例之埋入式導電配線的製作方法的步驟流程。 1A to FIG. 1J, FIG. 1A to FIG. 1J are schematic side views of a substrate having a buried conductive wiring in a manufacturing process according to an embodiment of the present invention, and FIGS. 1A to 1J show an embodiment of the present invention. The flow of steps in the method of manufacturing the buried conductive wiring.

請參考圖1A,首先,提供一個基材1。基材1的種類可依據實際需求而選擇。例如,當所述導電配線的製作方法是應用於半導體領域中,基材1可為含矽的半導體晶圓;在其它應用上,基材1可以是線路基板,而基材1的材料可以是聚碳酸酯(polycarbonate,PC)、聚碳酸酯與丙烯腈-丁二烯-苯乙烯共聚物(Acrylonitrile Butadiene Styrene,ABS)或含有玻璃纖維的材料。 基材1也可以是玻璃基材。 Referring to FIG. 1A, first, a substrate 1 is provided. The type of the substrate 1 can be selected according to actual needs. For example, when the manufacturing method of the conductive wiring is applied to the semiconductor field, the substrate 1 may be a germanium-containing semiconductor wafer; in other applications, the substrate 1 may be a circuit substrate, and the material of the substrate 1 may be Polycarbonate (PC), polycarbonate and acrylonitrile butadiene-styrene (ABS) or glass fiber-containing materials. The substrate 1 may also be a glass substrate.

接著,請參考圖1B,將基材1進行圖案化處理,以於基材1的上表面101形成第一凹槽區域2。關於將基材1進行圖案化處理的步驟的實施方式,可用雷射燒蝕基材1,以於基材1的上表面101開槽。如圖1B所示,所述第一凹槽區域2具有一預定深度。 Next, referring to FIG. 1B, the substrate 1 is patterned to form a first recessed region 2 on the upper surface 101 of the substrate 1. Regarding the embodiment of the step of patterning the substrate 1, the substrate 1 may be ablated with a laser to groove the upper surface 101 of the substrate 1. As shown in FIG. 1B, the first groove region 2 has a predetermined depth.

接著,請參考圖1C,為了於基材1的上表面101形成導電層3(圖1D),可先整面性地形成初始導電層3”於基材1的上表面101,其中,初始導電層3”是填滿第一凹槽區域2。形成初始導電層3”的方式可採用例如印刷導電膏、噴塗(Spray coating)、無電鍍製程(electroless plating)或濺鍍製程(Sputtering)等常見的導電材料塗佈製程。 Next, referring to FIG. 1C, in order to form the conductive layer 3 (FIG. 1D) on the upper surface 101 of the substrate 1, the initial conductive layer 3" may be formed over the entire surface of the upper surface 101 of the substrate 1, wherein the initial conductive layer Layer 3" is filled with the first recessed area 2. The manner in which the initial conductive layer 3" is formed may be, for example, a common conductive material coating process such as printing a conductive paste, a spray coating, an electroless plating, or a sputtering process.

然後,將初始導電層3”進行圖案化處理,使初始導電層3”形成所述導電層3於基材1的上表面101。關於將初始導電層3”進行圖案化處理的步驟的實施方式,可對初始導電層3”進行第一次的蝕刻處理。所述蝕刻處理可以採濕式蝕刻的方式。詳細而言,參圖1D,可先於初始導電層3”上形成犧牲圖案,例如圖1D所示的第二犧牲圖案7。第二犧牲圖案7可使用乾墨,而形成第二犧性圖案7的方式例如包括曝光及顯影等程序。其次,透過第二犧牲圖案7蝕刻初始導電層3”,也就是說,針對初始導電層3”沒有被第二犧牲圖案7覆蓋而裸露出來的部分進行蝕刻(例如進行咬銅處理),以圖案化初始導電層3”。在上述蝕刻初始導電層3”的程序中,裸露出來的初始導電層3”僅有一部分的厚度被蝕刻。最後,再移除第二犧牲圖案7,如圖1E所示。 Then, the initial conductive layer 3" is patterned to form the initial conductive layer 3" to form the conductive layer 3 on the upper surface 101 of the substrate 1. Regarding the embodiment of the step of patterning the initial conductive layer 3", the initial conductive layer 3" can be subjected to the first etching treatment. The etching process can be performed by wet etching. In detail, referring to FIG. 1D, a sacrificial pattern may be formed on the initial conductive layer 3", such as the second sacrificial pattern 7 shown in FIG. 1D. The second sacrificial pattern 7 may use a dry ink to form a second sacrificial pattern. The method of 7 includes, for example, exposure and development, etc. Next, the initial conductive layer 3" is etched through the second sacrificial pattern 7, that is, the portion where the initial conductive layer 3" is not covered by the second sacrificial pattern 7 and is exposed. Etching (eg, a copper bite process) to pattern the initial conductive layer 3". In the above-described process of etching the initial conductive layer 3", only a portion of the thickness of the exposed initial conductive layer 3" is etched. Finally, the second sacrificial pattern 7 is removed again, as shown in FIG. 1E.

綜上,導電層3可形成於基材1的上表面101。可參考圖1E,導電層3包括導電圖案31,導電圖案31是至少填入基材1的第一凹槽區域2內,並且,導電圖案31在厚度方向上是凸出於基材1的上表面101。亦即,導電圖案31的上表面301與基材1的上表面101兩者之間在厚度方向上具有一預定距離。此外,導電 圖案31的側壁形成第二凹槽區域4,第二凹槽區域4內具有導電層3的部分厚度H2。形成於基材1之上表面101的導電層3,可藉由第二凹槽區域4內的厚度H2而全面導通,以利後續的電鍍處理。 In summary, the conductive layer 3 can be formed on the upper surface 101 of the substrate 1. Referring to FIG. 1E, the conductive layer 3 includes a conductive pattern 31 which is filled at least into the first recessed region 2 of the substrate 1, and the conductive pattern 31 protrudes from the substrate 1 in the thickness direction. Surface 101. That is, the upper surface 301 of the conductive pattern 31 and the upper surface 101 of the substrate 1 have a predetermined distance in the thickness direction. In addition, conductive The sidewall of the pattern 31 forms a second recessed region 4 having a portion of the thickness H2 of the conductive layer 3 therein. The conductive layer 3 formed on the upper surface 101 of the substrate 1 can be fully turned on by the thickness H2 in the second recessed region 4 for subsequent plating treatment.

值得一提的是,如圖1C中所示的初始導電層3”的厚度H1(亦即,初始導電層3”的上表面至基材1的上表面101的垂直距離)可依據第一凹槽區域2的間距、導電配線的預期線距及導電配線的預期線寬而做調整,以利於上述蝕刻初始導電層3”的實施。 It is worth mentioning that the thickness H1 of the initial conductive layer 3" as shown in FIG. 1C (that is, the vertical distance from the upper surface of the initial conductive layer 3" to the upper surface 101 of the substrate 1) may be based on the first concave The pitch of the groove region 2, the expected line pitch of the conductive wiring, and the expected line width of the conductive wiring are adjusted to facilitate the implementation of the etching of the initial conductive layer 3".

於本發明另一未繪示的實施例中,關於將初始導電層3”進行圖案化處理的步驟的實施方式,所述蝕刻處理可以採乾式蝕刻,以雷射燒蝕初始導電層3”。具體而言,可依據實際需求,例如依據初始導電層3”的材質、初始導電層3”的厚度H1或者導電層3於第二凹槽區域4內的殘留厚度H2等,對雷射能量與雷射的掃描時間做調整,以避免雷射燒蝕過量而使所述第二凹槽區域4暴露出基材1的上表面101,或避免雷射能量不足而使所述第二凹槽區域4未達到預期的深度。 In another embodiment of the present invention, with respect to an embodiment of the step of patterning the initial conductive layer 3", the etching process may be dry etched to ablate the initial conductive layer 3". Specifically, depending on actual needs, for example, depending on the material of the initial conductive layer 3", the thickness H1 of the initial conductive layer 3", or the residual thickness H2 of the conductive layer 3 in the second recessed region 4, etc., The scanning time of the laser is adjusted to avoid excessive laser ablation to expose the second recessed region 4 to the upper surface 101 of the substrate 1, or to avoid insufficient laser energy to cause the second recessed region 4 did not reach the expected depth.

需要說明的是,如圖1E所示,本具體實施例中,導電圖案31是對應於基材1的第一凹槽區域2,進一步而言,導電圖案31的側壁可緊鄰第一凹槽區域2的側壁。 It should be noted that, as shown in FIG. 1E , in the specific embodiment, the conductive pattern 31 is corresponding to the first recessed region 2 of the substrate 1 . Further, the sidewall of the conductive pattern 31 may be adjacent to the first recessed region. 2 side walls.

接著,請參考圖1F,於導電層3上形成第一犧牲圖案5,第一犧牲圖案5是至少填入第二凹槽區域4內,並且,第一犧牲圖案5在厚度方向上是凸出於導電圖案31的上表面301。亦即,第一犧牲圖案5在厚度方向上的高度H3是大於導電圖案31在厚度方向上的高度。第一犧牲圖案5在厚度方向上的高度H3亦為第一犧牲圖案5的上表面501至基材1的上表面101的垂直距離,而導電圖案31在厚度方向上的高度亦為導電圖案31的上表面301至基材1的上表面101的垂直距離。此外,第一犧牲圖案5的側壁形成第三凹槽區域6,所述第三凹槽區域6可暴露出至少 一部分的導電圖案31。 Next, referring to FIG. 1F, a first sacrificial pattern 5 is formed on the conductive layer 3, the first sacrificial pattern 5 is filled in at least the second recess region 4, and the first sacrificial pattern 5 is convex in the thickness direction. On the upper surface 301 of the conductive pattern 31. That is, the height H3 of the first sacrificial pattern 5 in the thickness direction is greater than the height of the conductive pattern 31 in the thickness direction. The height H3 of the first sacrificial pattern 5 in the thickness direction is also the vertical distance from the upper surface 501 of the first sacrificial pattern 5 to the upper surface 101 of the substrate 1, and the height of the conductive pattern 31 in the thickness direction is also the conductive pattern 31. The vertical distance from the upper surface 301 to the upper surface 101 of the substrate 1. Furthermore, the sidewall of the first sacrificial pattern 5 forms a third recessed region 6, which may expose at least A portion of the conductive pattern 31.

以下詳細說明於導電層3上形成所述第一犧牲圖案5的實施方式。舉例來說,可先於導電層3上整面性地形成一層第一犧牲層(圖未繪式),其中第一犧牲層可填滿第二凹槽區域4。然後,將第一犧牲層進行圖案化處理,使第一犧牲層形成所述第一犧牲圖案5。第一犧牲層可使用乾墨,而圖案化第一犧牲圖案5的方式例如包括曝光及顯影等程序。 An embodiment in which the first sacrificial pattern 5 is formed on the conductive layer 3 will be described in detail below. For example, a first sacrificial layer (not shown) may be formed on the conductive layer 3 in a full-surface manner, wherein the first sacrificial layer may fill the second recess region 4. Then, the first sacrificial layer is patterned to form the first sacrificial layer to form the first sacrificial pattern 5. The first sacrificial layer may use dry ink, and the manner of patterning the first sacrificial pattern 5 includes, for example, exposure and development processes.

藉此,第一犧牲圖案5可對應於第二凹槽區域4而形成於第二凹槽區域4內所殘留的導電層3上。如圖1F所示,本實施例中,第一犧牲圖案5可填滿第二凹槽區域4,且第一犧牲圖案5的側壁與導電圖案31的側壁可部分切齊,換言之,第三凹槽區域6可暴露出導電圖案31的全部。另一方面而言,第一犧牲圖案5與導電圖案31為正負互補,但發明並不以此為限。 Thereby, the first sacrificial pattern 5 can be formed on the conductive layer 3 remaining in the second recessed region 4 corresponding to the second recessed region 4. As shown in FIG. 1F, in the embodiment, the first sacrificial pattern 5 can fill the second recessed region 4, and the sidewall of the first sacrificial pattern 5 and the sidewall of the conductive pattern 31 can be partially aligned, in other words, the third recess. The groove region 6 may expose all of the conductive patterns 31. On the other hand, the first sacrificial pattern 5 and the conductive pattern 31 are positive and negative complementary, but the invention is not limited thereto.

接著,參考圖1F至圖1G,將導電層3進行電鍍處理,使第三凹槽區域6所暴露的導電圖案31增厚。於本實施例中,導電圖案31是增厚至第一犧牲圖案5在厚度方向上的高度H3。換言之,經增厚的導電圖案31’在厚度方向上的高度可與第一犧牲圖案5在厚度方向上的高度H3相同。 Next, referring to FIG. 1F to FIG. 1G, the conductive layer 3 is subjected to a plating treatment to thicken the conductive pattern 31 exposed by the third recess region 6. In the present embodiment, the conductive pattern 31 is thickened to a height H3 of the first sacrificial pattern 5 in the thickness direction. In other words, the height of the thickened conductive pattern 31' in the thickness direction may be the same as the height H3 of the first sacrificial pattern 5 in the thickness direction.

然後,為了移除第一犧牲圖案5及移除第二凹槽區域4’內所殘留的導電層3’,可於導電圖案31’上形成一層蝕刻阻擋層8,以保護導電圖案31’。蝕刻阻擋層8的材料例如包括錫及鉛。接著,在蝕刻阻擋層8的保護下,以去墨方式移除第一犧牲圖案5,如圖1H所示。所述去墨方式例如是利用溶劑浸泡第一犧牲圖案5或是利用電漿體將第一犧牲圖案5剝除。 Then, in order to remove the first sacrificial pattern 5 and remove the conductive layer 3' remaining in the second recessed region 4', an etch stop layer 8 may be formed on the conductive pattern 31' to protect the conductive pattern 31'. The material of the etching stopper layer 8 includes, for example, tin and lead. Next, under the protection of the etch barrier layer 8, the first sacrificial pattern 5 is removed by deinking, as shown in FIG. 1H. The deinking method is, for example, immersing the first sacrificial pattern 5 with a solvent or stripping the first sacrificial pattern 5 with a plasma.

接著,參考圖1I,為了移除第一凹槽區域2內所殘留的導電層3’,可在蝕刻阻擋層8的保護下,對導電層3’進行第二次的蝕刻處理。相似於第一次的蝕刻處理,所述第二次的蝕刻處理同樣可以採濕式咬銅的方式或是乾式雷射燒蝕的方式。第二凹槽區域 4’內的導電層3’僅具有部分厚度,導電層3’的所述部分厚度例如可以是小於5微米,因此,不論是使用濕式蝕刻的方式或是乾式蝕刻的方式,第二凹槽區域4’內的導電層3’皆可被輕易去除。 Next, referring to FIG. 1I, in order to remove the conductive layer 3' remaining in the first recess region 2, the conductive layer 3' may be subjected to a second etching treatment under the protection of the etching stopper layer 8. Similar to the first etching process, the second etching process can also be a wet copper bite or a dry laser ablation. Second groove area The conductive layer 3' in 4' has only a partial thickness, and the thickness of the portion of the conductive layer 3' may be, for example, less than 5 microns, and therefore, whether by wet etching or dry etching, the second groove The conductive layer 3' in the region 4' can be easily removed.

最後,如圖1J所示,只要移除蝕刻阻擋層8,即可完成導電配線的製作,而獲得厚膜導電配線,例如厚銅配線。於本發明一實施例中,所述厚銅配線的厚度(亦即,導電圖案31’的厚度)可大於50微米,且所述厚銅配線的配線間距可達到小於50微米的等級。如圖1A至圖1H所示的實施例中,所述厚銅配線的配線間距亦為第二凹槽區域4、4’的寬度。 Finally, as shown in FIG. 1J, as long as the etching stopper layer 8 is removed, fabrication of the conductive wiring can be completed, and thick film conductive wiring such as thick copper wiring can be obtained. In an embodiment of the invention, the thickness of the thick copper wiring (i.e., the thickness of the conductive pattern 31') may be greater than 50 micrometers, and the wiring pitch of the thick copper wiring may be less than 50 micrometers. In the embodiment shown in Figs. 1A to 1H, the wiring pitch of the thick copper wiring is also the width of the second recessed regions 4, 4'.

上述實施例可歸納出本發明另一實施例之埋入式導電配線的製作方法,請參照圖2之流程圖。首先,提供一基材(步驟S1);接著,將所述基材進行圖案化處理,以於所述基材的上表面形成一第一凹槽區域(步驟S2);然後,於所述基材的上表面形成一導電層,其中所述導電層包括一導電圖案,所述導電圖案至少填入所述第一凹槽區域內,所述導電圖案在厚度方向上凸出於所述基材的上表面,所述導電圖案的側壁形成一第二凹槽區域,且所述第二凹槽區域內具有所述導電層的部分厚度(步驟S3);接著,於所述導電層上形成一第一犧牲圖案,其中所述第一犧牲圖案至少填入所述第二凹槽區域內,所述第一犧牲圖案在厚度方向上凸出於所述導電圖案的上表面,所述第一犧牲圖案的側壁形成一第三凹槽區域,且所述第三凹槽區域暴露一部分的所述導電圖案(步驟S4);然後,將所述導電層進行電鍍處理,使所述第三凹槽區域所暴露的所述導電圖案增厚(步驟S5);其次,移除所述第一犧牲圖案(步驟S6);以及移除所述第二凹槽區域內的所述導電層(步驟S7)。 The above embodiment can be summarized as a method for fabricating the buried conductive wiring according to another embodiment of the present invention. Please refer to the flowchart of FIG. First, a substrate is provided (step S1); then, the substrate is patterned to form a first groove region on the upper surface of the substrate (step S2); then, at the base Forming a conductive layer on the upper surface of the material, wherein the conductive layer includes a conductive pattern, the conductive pattern is at least filled in the first recessed region, and the conductive pattern protrudes from the substrate in a thickness direction The upper surface of the conductive pattern forms a second recessed region, and the second recessed region has a partial thickness of the conductive layer (step S3); then, a conductive layer is formed on the conductive layer a first sacrificial pattern, wherein the first sacrificial pattern is filled in at least the second recessed region, the first sacrificial pattern protrudes from an upper surface of the conductive pattern in a thickness direction, the first sacrifice a sidewall of the pattern forms a third recessed region, and the third recessed region exposes a portion of the conductive pattern (step S4); then, the conductive layer is subjected to a plating process to cause the third recessed region The exposed conductive pattern is thickened (step S5) Secondly, the first sacrificial pattern is removed (step S6); and the conductive layer in the second recessed region is removed (step S7).

綜上所述,本發明實施例提供一種埋入式導電配線的製作方法,其利用第一次蝕刻處理,以圖案化初始導電層3”,再利用第二次蝕刻處理,以移除第二凹槽區域內所殘留的導電層厚度。所 述埋入式導電配線的製作方法藉由此兩段式的蝕刻方式來進行導電配線的製作,可不受限於蝕刻能力,進而避免因蝕刻不完全所造成的導電良率不佳的問題。 In summary, the embodiments of the present invention provide a method for fabricating a buried conductive wiring, which uses a first etching process to pattern the initial conductive layer 3", and then uses a second etching process to remove the second The thickness of the conductive layer remaining in the recessed area. In the method for fabricating the buried conductive wiring, the conductive wiring is formed by the two-stage etching method, and the etching capability is not limited, thereby avoiding the problem of poor conductivity due to incomplete etching.

此外,所述埋入式導電配線的製作方法利用基材1之上表面101所形成的第一凹槽區域2,可建立厚膜導電配線(例如厚銅配線)的埋入深度;利用基材1之上表面101所形成的導電圖案31可建立厚膜導電配線(例如厚銅配線)的第一階段高度,再利用凸出於導電圖案31之上表面301的第一犧牲圖案5,可建立厚膜導電配線(例如厚銅配線)的第二階段高度。所述導電配線的製作方法可以製作出配線密度高、配線寬度窄的配線。 In addition, the method for fabricating the buried conductive wiring utilizes the first recessed region 2 formed by the upper surface 101 of the substrate 1 to establish a buried depth of the thick film conductive wiring (eg, thick copper wiring); The conductive pattern 31 formed by the upper surface 101 can establish a first-stage height of the thick film conductive wiring (for example, thick copper wiring), and can be established by using the first sacrificial pattern 5 protruding from the upper surface 301 of the conductive pattern 31. The second stage height of thick film conductive wiring (such as thick copper wiring). In the method of manufacturing the conductive wiring, wiring having a high wiring density and a narrow wiring width can be produced.

以上所述僅為本發明的較佳可行實施例,非因此侷限本發明的專利範圍,故舉凡運用本發明說明書及圖式內容所做的等效技術變化,均包含於本發明的保護範圍內。 The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, equivalent technical changes made by using the present specification and the contents of the drawings are included in the protection scope of the present invention. .

S1~S7‧‧‧步驟 S1~S7‧‧‧ steps

Claims (10)

一種埋入式導電配線的製作方法,包括:提供一基材;將所述基材進行圖案化處理,以於所述基材的上表面形成一第一凹槽區域;於所述基材的上表面形成一導電層,其中所述導電層包括一導電圖案,所述導電圖案至少填入所述第一凹槽區域內,所述導電圖案在厚度方向上凸出於所述基材的上表面,所述導電圖案的側壁形成一第二凹槽區域,且所述第二凹槽區域內具有所述導電層的部分厚度;於所述導電層上形成一第一犧牲圖案,其中所述第一犧性圖案至少填入所述第二凹槽區域內,所述第一犧牲圖案在厚度方向上凸出於所述導電圖案的上表面,所述第一犧牲圖案的側壁形成一第三凹槽區域,且所述第三凹槽區域暴露一部分的所述導電圖案;將所述導電層進行電鍍處理,使所述第三凹槽區域所暴露的所述導電圖案增厚;移除所述第一犧牲圖案;以及移除所述第二凹槽區域內的所述導電層。 A method for fabricating a buried conductive wiring, comprising: providing a substrate; patterning the substrate to form a first recessed region on an upper surface of the substrate; Forming a conductive layer on the upper surface, wherein the conductive layer comprises a conductive pattern, the conductive pattern is at least filled in the first recessed region, and the conductive pattern protrudes from the substrate in a thickness direction a surface, a sidewall of the conductive pattern forms a second recess region, and the second recess region has a partial thickness of the conductive layer; a first sacrificial pattern is formed on the conductive layer, wherein a first sacrificial pattern is filled in at least the second recessed region, the first sacrificial pattern protrudes from an upper surface of the conductive pattern in a thickness direction, and a sidewall of the first sacrificial pattern forms a third a recessed area, wherein the third recessed area exposes a portion of the conductive pattern; and the conductive layer is subjected to a plating process to thicken the conductive pattern exposed by the third recessed area; First sacrificial pattern; The conductive layer is removed in the region of the second groove. 如請求項第1項所述之埋入式導電配線的製作方法,其中於所述基材的上表面形成所述導電層的步驟中,更進一步包括:整面性地形成一初始導電層於所述基材的上表面,其中所述初始導電層填滿所述第一凹槽區域;以及將所述初始導電層進行圖案化處理。 The method of manufacturing the buried conductive wiring of claim 1, wherein the step of forming the conductive layer on the upper surface of the substrate further comprises: forming an initial conductive layer over the entire surface An upper surface of the substrate, wherein the initial conductive layer fills the first recess region; and the initial conductive layer is patterned. 如請求項第2項所述之埋入式導電配線的製作方法,其中將所 述初始導電層進行圖案化處理的步驟中,更進一步包括:形成一第二犧牲圖案於所述初始導電層上;透過所述第二犧牲圖案蝕刻所述初始導電層;以及移除所述第二犧牲圖案。 The method for fabricating a buried conductive wiring according to claim 2, wherein The step of performing the patterning process on the initial conductive layer further includes: forming a second sacrificial pattern on the initial conductive layer; etching the initial conductive layer through the second sacrificial pattern; and removing the first Two sacrificial patterns. 如請求項第1項所述之埋入式導電配線的製作方法,其中將所述初始導電層進行圖案化處理的步驟中,更進一步包括:以雷射燒蝕所述初始導電層。 The method for fabricating a buried conductive wiring according to claim 1, wherein the step of patterning the initial conductive layer further comprises: ablation of the initial conductive layer by laser. 如請求項第1項所述之埋入式導電配線的製作方法,其中將所述導電層進行電鍍處理的步驟之後及移除所述第一犧牲圖案的步驟之前,更進一步包括:於所述導電層上形成一蝕刻阻擋層。 The method for fabricating a buried conductive wiring according to claim 1, wherein the step of performing the plating treatment on the conductive layer and the step of removing the first sacrificial pattern further comprises: An etch stop layer is formed on the conductive layer. 如請求項第5項所述之埋入式導電配線的製作方法,其中移除所述第二凹槽區域內的所述導電層的步驟之後,更進一步包括:移除所述蝕刻阻擋層。 The method of fabricating the buried conductive wiring of claim 5, wherein the step of removing the conductive layer in the second recessed region further comprises: removing the etch stop layer. 如請求項第1項所述之埋入式導電配線的製作方法,其中所述導電圖案是增厚至所述第一犧牲圖案在厚度方向上的高度。 The method of fabricating a buried conductive wiring according to claim 1, wherein the conductive pattern is thickened to a height of the first sacrificial pattern in a thickness direction. 如請求項第1項所述之埋入式導電配線的製作方法,其中所述第一凹槽區域的側壁緊鄰所述導電圖案的側壁。 The method of fabricating a buried conductive wiring according to claim 1, wherein a sidewall of the first recessed region is adjacent to a sidewall of the conductive pattern. 如請求項第1項所述之埋入式導電配線的製作方法,其中所述導電圖案的側壁與所述第一犧牲圖案的側壁部分切齊。 The method of fabricating a buried conductive wiring according to claim 1, wherein a sidewall of the conductive pattern is aligned with a sidewall portion of the first sacrificial pattern. 如請求項第1項所述之埋入式導電配線的製作方法,其中所述 形成導電層的方法包括印刷導電膏。 The method for fabricating a buried conductive wiring according to claim 1, wherein the method A method of forming a conductive layer includes printing a conductive paste.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW340297B (en) * 1997-03-14 1998-09-11 Compeq Mfg Co Ltd Process for sealing a ball grid array IC free of substrate and free of solder ball
TW200501839A (en) * 2003-06-13 2005-01-01 Sanyo Electric Co Method for making a semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW340297B (en) * 1997-03-14 1998-09-11 Compeq Mfg Co Ltd Process for sealing a ball grid array IC free of substrate and free of solder ball
TW200501839A (en) * 2003-06-13 2005-01-01 Sanyo Electric Co Method for making a semiconductor device

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