JP2005236188A - Method for forming conductor pattern - Google Patents

Method for forming conductor pattern Download PDF

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JP2005236188A
JP2005236188A JP2004046179A JP2004046179A JP2005236188A JP 2005236188 A JP2005236188 A JP 2005236188A JP 2004046179 A JP2004046179 A JP 2004046179A JP 2004046179 A JP2004046179 A JP 2004046179A JP 2005236188 A JP2005236188 A JP 2005236188A
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resist layer
conductor pattern
transparent conductive
conductive film
film
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Eiji Shinohara
英司 篠原
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP2004046179A priority Critical patent/JP2005236188A/en
Priority to KR1020050014383A priority patent/KR100602912B1/en
Priority to CNB2005100519669A priority patent/CN100334710C/en
Publication of JP2005236188A publication Critical patent/JP2005236188A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/26—Devices for calling a subscriber
    • H04M1/27—Devices whereby a plurality of signals may be stored simultaneously
    • H04M1/274—Devices whereby a plurality of signals may be stored simultaneously with provision for storing more than one subscriber number at a time, e.g. using toothed disc
    • H04M1/2745—Devices whereby a plurality of signals may be stored simultaneously with provision for storing more than one subscriber number at a time, e.g. using toothed disc using static electronic memories, e.g. chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G06F21/32—User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
    • G10L15/00—Speech recognition
    • G10L15/02—Feature extraction for speech recognition; Selection of recognition unit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/42—Systems providing special services or facilities to subscribers
    • H04M3/487—Arrangements for providing information services, e.g. recorded voice services or time announcements
    • H04M3/493—Interactive information services, e.g. directory enquiries ; Arrangements therefor, e.g. interactive voice response [IVR] systems or voice portals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M2215/00—Metering arrangements; Time controlling arrangements; Time indicating arrangements
    • H04M2215/62—Called party billing, e.g. reverse billing, freephone, collect call, 0800 or 0900

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  • Signal Processing (AREA)
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  • Computer Vision & Pattern Recognition (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a conductor pattern having no restriction of a resist material, and then capable of repeatedly using a photo mask once formed, and excellent in productivity. <P>SOLUTION: The method for forming the conductor pattern comprises steps of forming a transparent conductive film 4 on a mask substrate 3 with a shielding film 2 formed on one surface 1a side of a transparent substrate 1, depositing a resist layer 5 on the film 4, making the resist layer 5 a patterned resist layer 6 having a resist removal part 6a by irradiating light from the other surface 1b side of the mask substrate 3 to expose and develop the resist layer 5, plating and forming the conductor pattern on the film 4 exposed from the resist removal part 6a, and moving the conductive pattern to the wiring board by mounting a wiring board on the conductive pattern. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、導体パターンの製造方法に関するものであり、特に、生産性に優れた導体パターンの製造方法に関するものである。   The present invention relates to a method for manufacturing a conductor pattern, and more particularly to a method for manufacturing a conductor pattern with excellent productivity.

従来、半導体基板等に形成される微細配線の配線抵抗を低減させるために、配線を構成する導体の断面形状のアスペクト比を高くする試みがなされている。すなわち、微細配線を形成する関係上、導体幅を広げることには限界があるため、必然的に導体の厚みを大きくしてアスペクト比を大きくすることで導体断面の断面積の増加を図ろうとしている。この場合の導体の形成方法としては、スピンコート法等により基板上にレジスト層等を厚く形成し、次にレジスト層上にフォトマスクを重ねてから光を照射してレジスト層を露光、現像し、レジスト層が除去された部分にメッキを行うことで、比較的大きな厚みの導体を形成していた。   2. Description of the Related Art Conventionally, attempts have been made to increase the aspect ratio of the cross-sectional shape of a conductor constituting a wiring in order to reduce the wiring resistance of fine wiring formed on a semiconductor substrate or the like. In other words, because there is a limit to increasing the conductor width due to the formation of fine wiring, it is inevitably attempted to increase the cross-sectional area of the conductor cross section by increasing the thickness of the conductor and increasing the aspect ratio. Yes. In this case, the conductor is formed by, for example, forming a thick resist layer on the substrate by spin coating or the like, then overlaying a photomask on the resist layer, and then irradiating light to expose and develop the resist layer. The conductor having a relatively large thickness has been formed by plating the portion from which the resist layer has been removed.

しかし、上記の方法では、高粘度のレジスト溶液を厚く平滑に塗布することが難しいため、レジスト層表面が完全な平坦面になりにくい。このため、レジスト層と、レジスト層上に重ねるフォトマスクとの間で部分的に隙間が発生し、レジスト層の露光時にこの隙間の周辺で回折現象が起こる場合がある。本来、レジスト層を露光、現像することにより形成されるレジスト除去部の壁面は、基板面に対して垂直になるところ、前述の回折現象が起こるとこの壁面がテーパー面となり、形成すべき導体の導体幅が広がってしまい、微細な配線構造の形成が困難になるという問題があった。   However, in the above method, since it is difficult to apply a thick and smooth resist solution smoothly, the resist layer surface is unlikely to be a completely flat surface. For this reason, a gap is partially generated between the resist layer and the photomask superimposed on the resist layer, and a diffraction phenomenon may occur around the gap when the resist layer is exposed. Originally, the wall surface of the resist removal portion formed by exposing and developing the resist layer is perpendicular to the substrate surface. When the above-described diffraction phenomenon occurs, this wall surface becomes a tapered surface, and the conductor to be formed There is a problem that the conductor width is widened and it is difficult to form a fine wiring structure.

そこで最近では、例えば、下記非特許文献１に記載されているように、フォトマスクをリフトオフにより形成し、このフォトマスク上にレジスト層を形成してからフォトマスク側から光を照射してレジスト層を露光、現像する方法が提案されている。この非特許文献１に記載された方法を更に詳細に説明すると、同文献の図３（ａ）から図３（ｌ）に示すように、あらかじめ一面上に別回路用の透明配線がパターン形成されたガラス板等からなる透明基板を用意し、このＩＴＯからなる透明配線上に、ネガ型およびポジ型のレジスト層をパターン形成し、次に前記の各レジスト層上にクロム金合金膜を形成し、次にポジ型レジスト層のみを除去してクロム金合金膜を部分的にリフトオフしてフォトマスクとする。次にフォトマスク上にネガ型のレジスト層を厚く形成し、透明基板の他面側から光を照射してネガ型レジスト層の露光、現像を行い、次にネガ型レジスト層を除去し、フォトマスクを電極としてニッケルメッキを行い、ニッケルからなる導体を形成する。この方法によれば、マスクとなるクロム金合金膜とポジ型レジスト層とが密着しているため、前述の回折現象による問題を回避できるという利点がある。
「パート オブ ザ カンファレンス オン デザイン、キャラクタリゼーション、アンド パッケージング フォー エムイーエムエス アンド マイクロエレクトロニクス（Part of the Conference on Design, Characterization, and Packaging for MEMS and Microelectronics）」、１９９９年１０月、ｐ．４８６−４９３ Therefore, recently, for example, as described in Non-Patent Document 1 below, a photomask is formed by lift-off, a resist layer is formed on the photomask, and then light is irradiated from the photomask side to form a resist layer. A method for exposing and developing the film has been proposed. The method described in Non-Patent Document 1 will be described in more detail. As shown in FIGS. 3 (a) to 3 (l) of the same document, a transparent wiring for another circuit is previously patterned on one surface. A transparent substrate made of glass plate or the like is prepared, negative and positive resist layers are patterned on the transparent wiring made of ITO, and then a chromium gold alloy film is formed on each of the resist layers. Then, only the positive resist layer is removed, and the chromium gold alloy film is partially lifted off to form a photomask. Next, a negative resist layer is formed thickly on the photomask, light is irradiated from the other side of the transparent substrate to expose and develop the negative resist layer, and then the negative resist layer is removed and the photo resist is removed. Nickel plating is performed using the mask as an electrode to form a nickel conductor. According to this method, since the chromium gold alloy film serving as a mask and the positive resist layer are in close contact with each other, there is an advantage that the problem due to the diffraction phenomenon described above can be avoided.
“Part of the Conference on Design, Characterization, and Packaging for MEMS and Microelectronics”, October 1999, p. 486-493

しかし、上記非特許文献１に記載された方法では、レジスト層の材質に制限があり、ネガ型のレジストしか使用できないという制約がある。ネガ型レジストは一般に、解像度や剥離性といった面でポジ型レジストに劣るため、微細な配線構造の形成に向かないという欠点がある。また、非特許文献１に記載の方法では、フォトマスクとなるクロム金合金膜をその都度形成しなければならないという問題もある。   However, the method described in Non-Patent Document 1 has a restriction that the material of the resist layer is limited and only a negative resist can be used. Negative resists are generally inferior to positive resists in terms of resolution and releasability, and thus have a drawback that they are not suitable for forming fine wiring structures. Further, the method described in Non-Patent Document 1 also has a problem that a chromium gold alloy film to be a photomask has to be formed each time.

本発明は、上記事情に鑑みてなされたものであって、レジスト材料の制約がなく、しかも一度形成したフォトマスクを繰り返し利用することができ、生産性に優れた導体パターンの製造方法を提供することを目的とする。   The present invention has been made in view of the above circumstances, and provides a method for producing a conductor pattern that is free from restrictions on resist materials, can repeatedly use a photomask that has been formed, and has excellent productivity. For the purpose.

上記の目的を達成するために、本発明は以下の構成を採用した。
本発明の導体パターンの製造方法は、透明基板の一面側に遮光膜がパターン形成されてなるマスク部を有するマスク基板を用意し、該マスク部の全面に透明導電膜を形成する工程と、前記透明導電膜の上にポジ型またはネガ型のレジスト層を積層する工程と、前記マスク基板の他面側から光を照射して前記レジスト層を露光し、露光後のレジスト層を現像することにより、前記レジスト層を、前記遮光膜のパターンに対応して形成されたレジスト除去部を有するパターン化レジスト層とする工程と、前記レジスト除去部の底面に露出した前記透明導電膜上に、導体パターンをメッキして形成する工程と、形成された前記導体パターン上に配線基板を載置して前記導体パターンを前記配線基板に移す工程と、を具備してなることを特徴とする。 In order to achieve the above object, the present invention employs the following configuration.
The method for producing a conductor pattern of the present invention includes a step of preparing a mask substrate having a mask portion in which a light shielding film is patterned on one side of a transparent substrate, and forming a transparent conductive film on the entire surface of the mask portion; A step of laminating a positive or negative resist layer on the transparent conductive film, and irradiating light from the other side of the mask substrate to expose the resist layer, and developing the exposed resist layer A step of making the resist layer a patterned resist layer having a resist removal portion formed corresponding to the pattern of the light shielding film, and a conductive pattern on the transparent conductive film exposed on the bottom surface of the resist removal portion And a step of placing a wiring board on the formed conductive pattern and transferring the conductive pattern to the wiring board.

上記構成によれば、マスク部の全面に形成した透明導電膜を、導体パターンのメッキ形成の際の電極として利用するので、ポジ型、ネガ型のレジスト層のどちらも用いることができる。すなわち、ポジ型を用いた場合には露光した部分がレジスト除去部となってそこに導体パターンが形成され、一方ネガ型を用いた場合は露光されない部分がレジスト除去部となってそこに導体パターンが形成される。いずれの場合もレジスト除去部の底面に透明導電膜が露出するので、この透明導電膜をメッキの電極として利用することができる。
また、形成した導体パターンを配線基板に移すので、マスク基板を再利用することができる。
更に、透明導電膜を介してマスク基板にレジスト層を積層することによって、マスク基板とレジスト層との間隔がほぼ一定に保たれるので、これにより回折現象が発生するおそれがなく、レジスト除去部の壁面が垂直に形成されて導体パターンの広がりを防止できる。 According to the above configuration, since the transparent conductive film formed on the entire surface of the mask portion is used as an electrode in plating the conductor pattern, either a positive type or a negative type resist layer can be used. That is, when the positive type is used, the exposed portion becomes a resist removal portion, and a conductor pattern is formed there. On the other hand, when the negative type is used, the unexposed portion becomes a resist removal portion and there is a conductor pattern there. Is formed. In either case, since the transparent conductive film is exposed on the bottom surface of the resist removing portion, this transparent conductive film can be used as an electrode for plating.
Further, since the formed conductor pattern is transferred to the wiring substrate, the mask substrate can be reused.
Further, by laminating the resist layer on the mask substrate through the transparent conductive film, the distance between the mask substrate and the resist layer is kept substantially constant, so that there is no possibility of occurrence of diffraction phenomenon, and the resist removing portion. The wall surface is formed vertically to prevent the conductor pattern from spreading.

また本発明の導体パターンの製造方法は、先に記載の導体パターンの製造方法であり、前記遮光膜をＣｒまたはＡｌにより形成することを特徴とする。ＣｒまたはＡｌからなる遮光膜は遮光性に優れるので、レジスト層の露光、現像を精度よく行うことができ、微細な導体パターンを形成することができる。   The conductor pattern manufacturing method of the present invention is the conductor pattern manufacturing method described above, wherein the light shielding film is formed of Cr or Al. Since the light shielding film made of Cr or Al is excellent in light shielding properties, the resist layer can be exposed and developed with high precision, and a fine conductor pattern can be formed.

また本発明の導体パターンの製造方法は、先に記載の導体パターンの製造方法であり、前記配線基板に前記導体パターンを移す際に前記透明導電膜をエッチングして除去することを特徴とする。この構成により、マスク基板を傷つけることなくマスク基板から導体パターンを剥離させることができ、マスク基板の再利用を図ることができる。   The conductor pattern manufacturing method of the present invention is the conductor pattern manufacturing method described above, wherein the transparent conductive film is etched and removed when the conductor pattern is transferred to the wiring board. With this configuration, the conductor pattern can be peeled from the mask substrate without damaging the mask substrate, and the mask substrate can be reused.

また本発明の導体パターンの製造方法は、先に記載の導体パターンの製造方法であり、前記透明導電膜がアモルファスのＩＴＯ膜であることを特徴とする。アモルファスＩＴＯ膜はシュウ酸で容易に溶解することができるので、導体パターンを配線基板に移す際にシュウ酸エッッチングを行うことで、マスク基板から導体パターンを容易に剥離することができる。   The conductor pattern manufacturing method of the present invention is the conductor pattern manufacturing method described above, wherein the transparent conductive film is an amorphous ITO film. Since the amorphous ITO film can be easily dissolved with oxalic acid, the conductor pattern can be easily peeled from the mask substrate by performing oxalic acid etching when the conductor pattern is transferred to the wiring substrate.

また本発明の導体パターンの製造方法は、先に記載の導体パターンの製造方法であり、前記導体パターンを前記配線基板に移す前に、前記パターン化レジスト層を除去することを特徴とする。この構成により、マスク基板を傷つけることなくマスク基板から導体パターンを剥離させることができ、マスク基板の再利用を図ることができる。   The conductor pattern manufacturing method of the present invention is the conductor pattern manufacturing method described above, wherein the patterned resist layer is removed before the conductor pattern is transferred to the wiring board. With this configuration, the conductor pattern can be peeled from the mask substrate without damaging the mask substrate, and the mask substrate can be reused.

本発明の導体パターンの製造方法によれば、レジスト材料の制約がなく、しかも一度形成したフォトマスクを繰り返し利用することができ、生産性に優れた導体パターンの製造方法を提供することができる。   According to the method for producing a conductor pattern of the present invention, there is no restriction on the resist material, and a photomask once formed can be used repeatedly, and a method for producing a conductor pattern excellent in productivity can be provided.

以下、本発明の実施の形態を図面を参照して説明する。尚、以下の実施形態の説明に使用する図面は、本発明の導体パターンの製造方法の工程を説明するための図面であり、図示される各部の大きさや厚さや寸法等は、実際の製造工程における各部の大きさや厚さや寸法とは異なっている。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used to describe the following embodiments are drawings for explaining the process of the method for manufacturing a conductor pattern of the present invention, and the size, thickness, dimensions, etc. of each part shown in the drawings are actual manufacturing processes. This is different from the size, thickness and dimensions of each part.

［第１の実施形態］
以下、本発明の第１の実施形態を図１及び図２を参照して説明する。
本実施形態の導体パターンの製造方法は、マスク基板に透明導電膜を形成する工程と、レジスト層を積層する工程と、パターン化レジスト層を形成する工程と、メッキ工程と、導体パターンを配線基板に移す工程と、から概略構成されている。
まず、マスク基板に透明導電膜を形成する工程では、図１Ａに示すように、透明基板１の一面１ａ上に遮光膜２…が形成されてなるマスク基板３を用意する。透明基板１は、例えばガラス等の透明材料から構成されている。また遮光膜２は、ＣｒまたはＡｌ等の遮光性の高い金属膜から構成されている。この遮光膜２…は、図１Ａの手前側から奥側に向けて帯状に形成されている。また、遮光膜２…が形成された領域がマスク部Ｍとされている。図１Ａの例では、透明基板１の一面１ａのほぼ全面に遮光膜２が形成されているので、一面１ａ全面がマスク部Ｍになる。なお、遮光膜２…が一面１ａの一部に限定的に形成されている場合は、マスク部Ｍはその限定された領域を占める部分となる。 [First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
The method for producing a conductor pattern of this embodiment includes a step of forming a transparent conductive film on a mask substrate, a step of laminating a resist layer, a step of forming a patterned resist layer, a plating step, and a conductor pattern on a wiring board. And the process of transferring to.
First, in the step of forming a transparent conductive film on the mask substrate, as shown in FIG. 1A, a mask substrate 3 is prepared in which a light shielding film 2 is formed on one surface 1a of the transparent substrate 1. The transparent substrate 1 is made of a transparent material such as glass. The light shielding film 2 is made of a metal film having high light shielding properties such as Cr or Al. The light shielding films 2 are formed in a band shape from the near side to the far side in FIG. 1A. A region where the light shielding films 2 are formed is a mask portion M. In the example of FIG. 1A, since the light shielding film 2 is formed on almost the entire surface 1a of the transparent substrate 1, the entire surface 1a becomes the mask portion M. In addition, when the light shielding films 2... Are limitedly formed on a part of the one surface 1a, the mask portion M is a portion that occupies the limited region.

遮光膜２…同士の間隔ｄ１は好ましくは１μｍ以上に設定され、例えば１０μｍ程度が好ましい。また遮光膜２自体の幅ｗ１は、好ましくは１μｍ以上に設定され、例えば１０μｍ程度が好ましい。更に遮光膜２の厚みは、好ましくは９０ｎｍ以上３００ｎｍ以下の範囲に設定され、例えば１００ｎｍ程度が好ましい。 The distance d 1 between the light shielding films 2 is preferably set to 1 μm or more, and is preferably about 10 μm, for example. The width w 1 of the light shielding film 2 itself is preferably set to 1 μm or more, and preferably about 10 μm, for example. Furthermore, the thickness of the light-shielding film 2 is preferably set in a range of 90 nm to 300 nm, and preferably about 100 nm, for example.

次に、図１Ｂに示すように、マスク部Ｍの全面、すなわち透明基板１の一面１ａ全面に透明導電膜４を成膜する。透明導電膜４は、たとえば、アモルファスのＩＴＯ（インジウム錫オキサイド）などで形成することが好ましい。また、透明導電膜４の厚みは０．１５μｍ程度にするとよい。なお、マスク部Ｍが透明基板１の一面１ａの一部の領域のみに形成されている場合は、透明導電膜４もそのマスク部Ｍの形成領域に限定して成膜することが好ましい。   Next, as shown in FIG. 1B, a transparent conductive film 4 is formed on the entire surface of the mask portion M, that is, the entire surface 1 a of the transparent substrate 1. The transparent conductive film 4 is preferably formed of, for example, amorphous ITO (indium tin oxide). The thickness of the transparent conductive film 4 is preferably about 0.15 μm. In addition, when the mask part M is formed only in a partial region of the one surface 1 a of the transparent substrate 1, it is preferable to form the transparent conductive film 4 limited to the region where the mask part M is formed.

次にレジスト層を積層する工程およびパターン化レジスト層を形成する工程について説明する。
レジスト層を積層する工程では、図１Ｃに示すように、透明導電膜４の全面にポジ型のレジスト層５を積層する。レジスト層５の厚みは、１０μｍ以上１００μｍ以下の範囲が好ましく、３０μｍ程度がより好ましい。またレジスト層５はポジ型に限らず、ネガ型でもよい。
レジスト層５を形成した後、透明基板１の他面１ｂ側から紫外光ＵＶを照射する。紫外光ＵＶは一部が遮光膜２…により遮光され、別の一部は遮光膜２…の間を通過してレジスト層５を露光させる。
そして図１Ｄに示すように、レジスト層５の露光された部分をウエットエッチングにより除去（現像）することにより、レジスト除去部６ａを有するパターン化レジスト層６を形成する。レジスト除去部６ａの底面には透明導電膜４が露出する。また、本実施形態のように、ポジ型のレジスト層５を使用した場合には図１Ｄに示すように遮光膜２に対応する部分がレジスト除去部となるが、ネガ型のレジスト層を使用した場合には遮光層２が形成されていない部分がレジスト除去部となる。どちらの場合も、レジスト除去部の底面には透明導電膜４が露出する。 Next, the process of laminating a resist layer and the process of forming a patterned resist layer will be described.
In the step of laminating the resist layer, as shown in FIG. 1C, a positive resist layer 5 is laminated on the entire surface of the transparent conductive film 4. The thickness of the resist layer 5 is preferably in the range of 10 μm to 100 μm, and more preferably about 30 μm. The resist layer 5 is not limited to a positive type, and may be a negative type.
After forming the resist layer 5, ultraviolet light UV is irradiated from the other surface 1 b side of the transparent substrate 1. The ultraviolet light UV is partly shielded by the light shielding film 2... And another part passes between the light shielding films 2 to expose the resist layer 5.
Then, as shown in FIG. 1D, a patterned resist layer 6 having a resist removal portion 6a is formed by removing (developing) the exposed portion of the resist layer 5 by wet etching. The transparent conductive film 4 is exposed on the bottom surface of the resist removing portion 6a. Further, as in this embodiment, when a positive resist layer 5 is used, the portion corresponding to the light shielding film 2 is a resist removal portion as shown in FIG. 1D, but a negative resist layer is used. In this case, the portion where the light shielding layer 2 is not formed becomes a resist removal portion. In either case, the transparent conductive film 4 is exposed on the bottom surface of the resist removal portion.

次にメッキ工程について説明する。図２Ａに示すように、透明導電膜４を電極とするメッキ法により、パターン化レジスト層６のレジスト除去部６ａにＣｕ等からなる導体パターン７をメッキで形成する。具体的には例えば、硫酸銅等を含むメッキ液をレジスト除去部６ａ内の透明電極膜４に接触させてから、透明導電膜４に直流電流を印加してＣｕメッキを成長させる。導体パターン７の厚みはパターン化レジスト層６の厚みよりも薄くすることが好ましく、例えば２０μｍ程度がよい。
次に図２Ｂに示すように、ウエットエッチングによりパターン化レジスト層６を除去する。このようにして、マスク基板１上に所定の形状にパターン成形された導体パターン７が得られる。 Next, the plating process will be described. As shown in FIG. 2A, a conductor pattern 7 made of Cu or the like is formed by plating on the resist removal portion 6a of the patterned resist layer 6 by plating using the transparent conductive film 4 as an electrode. Specifically, for example, after a plating solution containing copper sulfate or the like is brought into contact with the transparent electrode film 4 in the resist removing portion 6a, a direct current is applied to the transparent conductive film 4 to grow Cu plating. The conductor pattern 7 is preferably thinner than the patterned resist layer 6, for example, about 20 μm.
Next, as shown in FIG. 2B, the patterned resist layer 6 is removed by wet etching. In this way, a conductor pattern 7 that is patterned into a predetermined shape on the mask substrate 1 is obtained.

次に導体パターンを配線基板に移す工程について説明する。この工程では、まず図２Ｃに示すように、導体パターン７の上に配線基板８を重ね合わせる。配線基板８は、通常のガラスエポキシ板、フレキシブルプリント基板、セラミックス基板などを用いることができる。配線基板８の導体パターン７との突き合わせ面８ａには、配線基板８と導体パターン７との接着性を高めるために、予め接着剤等を塗布しておいてもよい。   Next, the process of transferring the conductor pattern to the wiring board will be described. In this step, first, as shown in FIG. 2C, the wiring board 8 is overlaid on the conductor pattern 7. As the wiring board 8, a normal glass epoxy board, a flexible printed board, a ceramic board, or the like can be used. In order to improve the adhesion between the wiring substrate 8 and the conductor pattern 7, an adhesive or the like may be applied in advance to the abutting surface 8 a of the wiring substrate 8 with the conductor pattern 7.

次に図２Ｄに示すように、マスク基板３から配線基板８をゆっくり引き離して導体パターン７を配線基板８ごとマスク基板３から剥離させる。このようにして導体パターン７を配線基板８に移すことができる。なおこのとき、透明導電膜４をウエットエッチングして除去してから導体パターン７を剥離させることが、導体パターン７を傷つけずに剥離できる点で好ましい。透明導電膜４がアモルファス状態のＩＴＯ膜である場合には、エッチャント液としてシュウ酸水溶液を用いることができる。
また、透明導電膜４をエッチングせずに導体パターン７を容易に剥離できる場合であっても、導体パターン７を剥離させてから透明導電膜４をウエットエッチングして除去しておくことが好ましい。 Next, as shown in FIG. 2D, the wiring substrate 8 is slowly pulled away from the mask substrate 3 to peel the conductor pattern 7 together with the wiring substrate 8 from the mask substrate 3. In this way, the conductor pattern 7 can be transferred to the wiring board 8. At this time, it is preferable that the conductive pattern 7 is peeled off after the transparent conductive film 4 is removed by wet etching because the conductive pattern 7 can be peeled off without being damaged. When the transparent conductive film 4 is an amorphous ITO film, an oxalic acid aqueous solution can be used as the etchant liquid.
Even when the conductive pattern 7 can be easily peeled without etching the transparent conductive film 4, it is preferable to remove the conductive film 7 by wet etching after the conductive pattern 7 is peeled off.

導体パターン７剥離後のマスク基板３は、次の導体パターン形成のマスク基板３として再利用できる。   The mask substrate 3 after the conductor pattern 7 is peeled off can be reused as the mask substrate 3 for the next conductor pattern formation.

以上説明したように、本実施形態の導体パターンの製造方法によれば、透明導電膜４を介してマスク基板３にレジスト層５を積層することによってマスク基板３とレジスト層５との間隔がほぼ一定に保たれるので、レジスト層の露光時に回折現象が起きる虞がなく、レジスト除去部６ａの壁面が垂直に形成される。これにより、導体パターン７の側壁面がマスク基板３に対してほぼ垂直に形成され、導体パターン７の導体幅が広がる恐れがなく、導体パターン７の厚みを従来よりも格段に高めることができる。こうすることで、アスペクト比が大きく低抵抗でしかも微細な配線構造を容易に形成することができる。   As described above, according to the conductor pattern manufacturing method of the present embodiment, the resist layer 5 is laminated on the mask substrate 3 via the transparent conductive film 4 so that the distance between the mask substrate 3 and the resist layer 5 is substantially reduced. Since it is kept constant, there is no possibility that a diffraction phenomenon will occur during exposure of the resist layer, and the wall surface of the resist removing portion 6a is formed vertically. Thereby, the side wall surface of the conductor pattern 7 is formed substantially perpendicular to the mask substrate 3, and there is no fear that the conductor width of the conductor pattern 7 is widened, and the thickness of the conductor pattern 7 can be remarkably increased as compared with the conventional case. By doing so, it is possible to easily form a fine wiring structure with a large aspect ratio and low resistance.

また、マスク部Ｍの全面に形成した透明導電膜４を導体パターン７のメッキ形成の際の電極として利用するので、ポジ型、ネガ型のいずれのレジスト層でも用いることができる。すなわち、ポジ型を用いた場合には露光された部分がレジスト除去部となってそこに導体パターン７が形成され、一方ネガ型を用いた場合は露光されない部分がレジスト除去部となってそこに導体パターン７が形成される。いずれの場合もレジスト除去部の底面から透明導電膜４が露出するので、この透明導電膜４をメッキの電極として利用することができる。   Further, since the transparent conductive film 4 formed on the entire surface of the mask portion M is used as an electrode when the conductor pattern 7 is formed by plating, it can be used for either positive type or negative type resist layers. That is, when the positive type is used, the exposed portion becomes the resist removal portion, and the conductor pattern 7 is formed there. On the other hand, when the negative type is used, the unexposed portion becomes the resist removal portion. Conductive pattern 7 is formed. In either case, since the transparent conductive film 4 is exposed from the bottom surface of the resist removal portion, this transparent conductive film 4 can be used as a plating electrode.

［第２の実施形態］
次に本発明の第２の実施形態を図３及び図４を参照して説明する。本実施形態の導体パターンの製造方法は、第１の実施形態と同様に、マスク基板に透明導電膜を形成する工程と、レジスト層を積層する工程と、パターン化レジスト層を形成する工程と、メッキ工程と、導体パターンを配線基板に移す工程と、から概略構成されている。本実施形態と第１の実施形態との相違点は、マスク基板の断面形状が異なる点である。なお、図３および図４に示す構成要素のうち、図１および図２に示す構成要素と同一の構成要素には、図１および図２に示した符号と同一の符号を付してその説明を省略、若しくは簡単に説明する。 [Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. As in the first embodiment, the conductor pattern manufacturing method of the present embodiment includes a step of forming a transparent conductive film on a mask substrate, a step of laminating a resist layer, a step of forming a patterned resist layer, It is roughly comprised from the plating process and the process of transferring a conductor pattern to a wiring board. The difference between the present embodiment and the first embodiment is that the cross-sectional shape of the mask substrate is different. Of the components shown in FIGS. 3 and 4, the same components as those shown in FIGS. 1 and 2 are designated by the same reference numerals as those shown in FIGS. Is omitted or briefly described.

まず、マスク基板に透明導電膜を形成する工程では、図３Ａに示すように、透明基板１１の一面１１ａ上に遮光膜２…が形成されてなるマスク基板１３を用意する。透明基板１１は、例えばガラス等の透明材料から構成され、その一面１１ａ上に断面視略台形状の凹部１１ｃが形成されている。遮光膜２は、図３Ａの手前側から奥側に向けて帯状に形成されている。また遮光膜２の一部が凹部１１ｃの全面に形成されている。遮光膜２の厚みは凹部１１ｃの深さよりも小さくされており、凹部１１ｃに形成された遮光膜２は凹部１１ｃの断面形状にほぼ沿った形状になる。遮光膜２…が形成された領域がマスク部Ｍである。   First, in the step of forming a transparent conductive film on the mask substrate, as shown in FIG. 3A, a mask substrate 13 is prepared in which a light shielding film 2 is formed on one surface 11a of the transparent substrate 11. The transparent substrate 11 is made of, for example, a transparent material such as glass, and a concave portion 11c having a substantially trapezoidal shape in cross section is formed on one surface 11a thereof. The light shielding film 2 is formed in a band shape from the near side to the far side in FIG. 3A. A part of the light shielding film 2 is formed on the entire surface of the recess 11c. The thickness of the light shielding film 2 is made smaller than the depth of the concave portion 11c, and the light shielding film 2 formed in the concave portion 11c has a shape substantially along the cross-sectional shape of the concave portion 11c. A region where the light shielding films 2 are formed is a mask portion M.

次に、図３Ｂに示すように、マスク部Ｍの全面にアモルファスのＩＴＯからなる透明導電膜４を成膜する。この場合も透明導電膜４の厚みが凹部１１ｃの深さよりも小さくされているため、凹部１１ｃに形成された透明導電膜４は凹部１１ｃの断面形状にほぼ沿った形状になる。   Next, as shown in FIG. 3B, a transparent conductive film 4 made of amorphous ITO is formed on the entire surface of the mask portion M. Also in this case, since the thickness of the transparent conductive film 4 is smaller than the depth of the concave portion 11c, the transparent conductive film 4 formed in the concave portion 11c has a shape substantially along the cross-sectional shape of the concave portion 11c.

次にレジスト層を積層する工程およびパターン化レジスト層を形成する工程について説明する。
レジスト層を積層する工程では、図３Ｃに示すように、透明導電膜４の全面にポジ型のレジスト層１５をスピンコート法等によって積層する。レジスト層１５は、凹部１１ｃを完全に埋めるとともにレジスト層１５の上面１５ａがほぼ平坦になるように形成することが好ましい。レジスト層１５の厚みは、凹部１１ｃの非形成箇所における厚みを１０μｍ以上１００μｍ以下の範囲に設定することが好ましく、３０μｍ程度にすることがより好ましい。またレジスト層１５はポジ型に限らず、ネガ型でもよい。
レジスト層１５を形成した後、透明基板１１の他面１１ｂ側から紫外光ＵＶを照射する。紫外光ＵＶは一部が遮光膜１２…により遮光され、別の一部は遮光膜１２…の間を通過してレジスト層１５を露光させる。
そして図３Ｄに示すように、レジスト層１５の露光された部分をウエットエッチングにより除去（現像）することにより、レジスト除去部１６ａを有するパターン化レジスト層１６を形成する。レジスト除去部１６ａの底面からは透明導電膜４が露出する。 Next, the process of laminating a resist layer and the process of forming a patterned resist layer will be described.
In the step of laminating the resist layer, as shown in FIG. 3C, a positive resist layer 15 is laminated on the entire surface of the transparent conductive film 4 by spin coating or the like. The resist layer 15 is preferably formed so that the recess 11c is completely filled and the upper surface 15a of the resist layer 15 is substantially flat. The thickness of the resist layer 15 is preferably set in the range of 10 μm or more and 100 μm or less, more preferably about 30 μm, at the portion where the recess 11 c is not formed. The resist layer 15 is not limited to a positive type, and may be a negative type.
After forming the resist layer 15, ultraviolet light UV is irradiated from the other surface 11 b side of the transparent substrate 11. A part of the ultraviolet light UV is shielded by the light shielding film 12 and the other part passes between the light shielding films 12 to expose the resist layer 15.
Then, as shown in FIG. 3D, the exposed portion of the resist layer 15 is removed (developed) by wet etching, thereby forming a patterned resist layer 16 having a resist removal portion 16a. The transparent conductive film 4 is exposed from the bottom surface of the resist removing portion 16a.

次にメッキ工程について説明する。図４Ａに示すように、透明導電膜４を電極とするメッキ法により、パターン化レジスト層１６のレジスト除去部１６ａにＣｕ等からなる導体パターン１７をメッキで形成する。このとき導体パターン１７は、透明導電膜４上でほぼ均一な厚みに形成される。このため、凹部１１ｃに形成される導体パターン１７ａは、凹部１１ａの断面形状に沿った形に形成される。これにより、導体パターン１７ａの上面にはパターン凹部１７ａ１が形成される。導体パターン１７の厚みはパターン化レジスト層１６の厚みよりも薄くすることが好ましく、例えば２０μｍ程度がよい。
次に図４Ｂに示すように、ウエットエッチングによりパターン化レジスト層１６を除去する。 Next, the plating process will be described. As shown in FIG. 4A, a conductor pattern 17 made of Cu or the like is formed by plating on the resist removal portion 16a of the patterned resist layer 16 by plating using the transparent conductive film 4 as an electrode. At this time, the conductor pattern 17 is formed on the transparent conductive film 4 with a substantially uniform thickness. For this reason, the conductor pattern 17a formed in the recessed part 11c is formed in the shape along the cross-sectional shape of the recessed part 11a. Thus, the upper surface of the conductive pattern 17a is patterned recess 17a 1 are formed. The conductor pattern 17 is preferably thinner than the patterned resist layer 16, for example, about 20 μm.
Next, as shown in FIG. 4B, the patterned resist layer 16 is removed by wet etching.

次に導体パターンを配線基板に移す工程では、第１の実施形態の場合と同様に、図４Ｃに示すように導体パターン１７の上に配線基板８を重ね合わせてから、図４Ｄに示すようにマスク基板１３から配線基板８をゆっくり引き離して導体パターン１７を配線基板８ごとマスク基板１３から剥離させる。このようにして導体パターン１７を配線基板８に移すことができる。
なお、上述したように、凹部１１ｃ上に形成された導体パターン１７ａにはパターン凹部１７ａ１が形成されており、導体パターン１７が配線基板８に移されたときに、このパターン凹部１７ａ１による空隙部１７ａ２が形成される。そこであらかじめ配線基板８の一面８ａ上に別の配線を形成しておき、この別の配線に空隙部１７ａ２を重ねるようにすれば、配線基板８上に立体配線構造を容易に形成することが可能になる。 Next, in the step of transferring the conductor pattern to the wiring board, as in the case of the first embodiment, as shown in FIG. 4D, the wiring board 8 is overlaid on the conductor pattern 17 as shown in FIG. 4C. The wiring substrate 8 is slowly pulled away from the mask substrate 13 to peel the conductor pattern 17 from the mask substrate 13 together with the wiring substrate 8. In this way, the conductor pattern 17 can be transferred to the wiring board 8.
As described above, the conductor pattern 17a formed on the concave portion 11c is formed with a pattern depression 17a 1, when the conductor pattern 17 is transferred to the wiring board 8, the air gap by the pattern recess 17a 1 Part 17a 2 is formed. Therefore previously formed another wiring on one surface 8a of the pre-wiring substrate 8, if to overlap the air gap 17a 2 on the different lines, it is possible to easily form a three-dimensional wiring structure on the wiring board 8 It becomes possible.

導体パターン１７の剥離後のマスク基板１３は、第１の実施形態と同様に、次の導体パターン形成のマスク基板１３として再利用できる。   The mask substrate 13 from which the conductor pattern 17 has been peeled can be reused as the mask substrate 13 for the next conductor pattern formation as in the first embodiment.

以上説明したように、本実施形態の導体パターンの製造方法によれば立体配線構造を容易に形成することができる。   As described above, according to the conductor pattern manufacturing method of the present embodiment, a three-dimensional wiring structure can be easily formed.

本発明の第１の実施形態である導体パターンの製造方法における製造工程を説明する断面模式図。The cross-sectional schematic diagram explaining the manufacturing process in the manufacturing method of the conductor pattern which is the 1st Embodiment of this invention. 本発明の第１の実施形態である導体パターンの製造方法における製造工程を説明する断面模式図。The cross-sectional schematic diagram explaining the manufacturing process in the manufacturing method of the conductor pattern which is the 1st Embodiment of this invention. 本発明の第２の実施形態である導体パターンの製造方法における製造工程を説明する断面模式図。The cross-sectional schematic diagram explaining the manufacturing process in the manufacturing method of the conductor pattern which is the 2nd Embodiment of this invention. 本発明の第２の実施形態である導体パターンの製造方法における製造工程を説明する断面模式図。The cross-sectional schematic diagram explaining the manufacturing process in the manufacturing method of the conductor pattern which is the 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１、１１…透明基板、１ａ、１１ａ…一面、１ｂ、１１ｂ…他面、２、１２…遮光膜、３、１３…マスク基板、４…透明導電膜、５、１５…レジスト層、６、１６…パターン化レジスト層、６ａ、１６ａ…レジスト除去部、７、１７…導体パターン、８…配線基板、Ｍ…マスク部

DESCRIPTION OF SYMBOLS 1, 11 ... Transparent substrate, 1a, 11a ... One side, 1b, 11b ... Other side, 2, 12 ... Light-shielding film, 3, 13 ... Mask substrate, 4 ... Transparent conductive film, 5, 15 ... Resist layer, 6, 16 ... Patterned resist layer, 6a, 16a ... Resist removal part, 7, 17 ... Conductor pattern, 8 ... Wiring board, M ... Mask part

Claims (5)

透明基板の一面側に遮光膜がパターン形成されてなるマスク部を有するマスク基板を用意し、該マスク部の全面に透明導電膜を形成する工程と、
前記透明導電膜の上にポジ型またはネガ型のレジスト層を積層する工程と、
前記マスク基板の他面側から光を照射して前記レジスト層を露光し、露光後のレジスト層を現像することにより、前記レジスト層を、前記遮光膜のパターンに対応して形成されたレジスト除去部を有するパターン化レジスト層とする工程と、
前記レジスト除去部の底面に露出した前記透明導電膜上に、導体パターンをメッキして形成する工程と、
形成された前記導体パターン上に配線基板を載置して前記導体パターンを前記配線基板に移す工程と、を具備してなることを特徴とする導体パターンの製造方法。 Preparing a mask substrate having a mask portion in which a light shielding film is patterned on one surface side of the transparent substrate, and forming a transparent conductive film on the entire surface of the mask portion;
Laminating a positive or negative resist layer on the transparent conductive film;
The resist layer is exposed to light from the other side of the mask substrate to expose the resist layer, and the resist layer after exposure is developed to remove the resist layer formed corresponding to the pattern of the light shielding film. Forming a patterned resist layer having a portion;
Forming a conductive pattern by plating on the transparent conductive film exposed on the bottom surface of the resist removal portion;
And a step of placing a wiring board on the formed conductive pattern and transferring the conductive pattern to the wiring board. 前記遮光膜をＣｒまたはＡｌにより形成することを特徴とする請求項１に記載の導体パターンの製造方法。   The method of manufacturing a conductor pattern according to claim 1, wherein the light shielding film is formed of Cr or Al. 前記配線基板に前記導体パターンを移す際に前記透明導電膜をエッチングして除去することを特徴とする請求項１に記載の導体パターンの製造方法。   The method for producing a conductor pattern according to claim 1, wherein the transparent conductive film is removed by etching when the conductor pattern is transferred to the wiring board. 前記透明導電膜がアモルファスのＩＴＯ膜であることを特徴とする請求項１または請求項３に記載の導体パターンの製造方法。   The method for producing a conductor pattern according to claim 1, wherein the transparent conductive film is an amorphous ITO film. 前記導体パターンを前記配線基板に移す前に、前記パターン化レジスト層を除去することを特徴とする請求項１に記載の導体パターン製造方法。

The conductor pattern manufacturing method according to claim 1, wherein the patterned resist layer is removed before the conductor pattern is transferred to the wiring board.

JP2004046179A 2004-02-23 2004-02-23 Method for forming conductor pattern Pending JP2005236188A (en)

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JP2013222752A (en) * 2012-04-13 2013-10-28 Lapis Semiconductor Co Ltd Semiconductor device manufacturing method
US9293402B2 (en) 2012-04-13 2016-03-22 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
US9721879B2 (en) 2012-04-13 2017-08-01 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
US10424537B2 (en) 2012-04-13 2019-09-24 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
US10957638B2 (en) 2012-04-13 2021-03-23 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components

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