TWI553864B - 半導體結構與其製法 - Google Patents

半導體結構與其製法 Download PDF

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TWI553864B
TWI553864B TW102127219A TW102127219A TWI553864B TW I553864 B TWI553864 B TW I553864B TW 102127219 A TW102127219 A TW 102127219A TW 102127219 A TW102127219 A TW 102127219A TW I553864 B TWI553864 B TW I553864B
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layer
metal layer
type metal
gate
dielectric layer
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TW201438234A (zh
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聶鑫譽
吳鐵將
廖偉明
黃瑞成
洪海涵
李秀春
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南亞科技股份有限公司
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Description

半導體結構與其製法
本發明係有關於一種半導體元件，且特別是有關於一種具有雙功函數金屬閘極之半導體元件與其製法。
半導體積體電路(integrated circuit,IC)發展的過程中，當IC幾何尺寸(亦即製程所能得到的最小元件(或線))逐漸縮小的同時，功能元件之密度(亦即每單位晶片面積中的內連線元件)隨之逐漸增加。
特別是當互補金屬氧化半導體(CMOS)元件的尺寸逐漸縮小的同時，短通道效應(short channel effect)變得明顯，進而造成閘極的臨界電壓(threshold voltage,Vth)變小。
習知提高臨界電壓(Vth)的方法，例如通道摻雜(channel doping)、源極/汲極摻雜降低(S/D doping reduction)、增加環型佈植(increase halo implatnt)等方式。然而，上述方法會導致其他的缺點，例如增加接面漏電流(junction leakage)、增加飽和源極電流(drain current saturation,IDs)、增加介面電容(junction capacitance)等。
另外，亦可使用功函數為4.6 eV附近的材料(如TiN、Ta、W等)，其費米能位(Fermi level)約在矽基板能隙中 間，一般稱為mid-gap金屬材料。然而，使用mid-gap金屬材料仍無法降低閘極引發汲極漏電流(gate-induced drain leakage,GIDL)的問題。
因此，業界亟需發展一種半導體元件，此元件不但能提高閘極之臨界電壓(Vth)，且能降低閘極引發汲極漏電流(GIDL)。
本發明提供一種半導體結構，包括：一基板；一U型閘極介電層形成於該基板之上；以及一雙功函數金屬閘極層形成於該U型閘極介電層之內側，其中雙功函數金屬閘極層包括一第一導電類型金屬層與一第二導電類型金屬層。
本發明亦提供一種半導體結構之製法，包括以下步驟：提供一基板；形成一虛設閘極(dummy gate)於該基板之上；形成層間介電層(inter-layer dielectric layer)於該虛設閘極與該基板之上；對該層間介電層進行一第一化學機械研磨製程(chemical mechanical polishing,CMP)，以暴露該虛設閘極之上表面；形成一金屬層於該虛設閘極上表面之上；移除該虛設閘極，以形成一溝槽(trench)於該層間介電層中；順應性形成一閘極介電層於該溝槽中；順應性形成一第一導電類型金屬層於該閘極介電層之上；移除位於該金屬層之上的該第一導電類型金屬層與該閘極介電層，以形成一縫隙(gap)於層間介電層中，其中該縫隙暴露該部份的閘極介電層；填充一第二導電類型金屬層於該縫隙中，其中該第二導電類型金屬層夾置於兩個第一導電類型金屬層之間，以形成一雙功函數金屬閘極層(dual work function metal gate)；以及對該第二導電類型金屬層與該金屬層進行一第二化學機械研磨製程(CMP)，以暴露雙功函數金屬閘極層之上表面。
100‧‧‧半導體元件
102‧‧‧基板
104‧‧‧虛設閘極
104a‧‧‧虛設閘極之上表面
106‧‧‧間隙壁
108‧‧‧層間介電層
110‧‧‧金屬層
120‧‧‧溝槽
122‧‧‧閘極介電層
122a‧‧‧閘極介電層之水平部份
122b‧‧‧閘極介電層之垂直部份
124‧‧‧第一導電類型金屬層
125‧‧‧縫隙
126‧‧‧第二導電類型金屬層
130‧‧‧雙功函數金屬閘極
D1‧‧‧第一寬度
D2‧‧‧第二寬度
第1A~1H圖為一系列剖面圖，用以說明本發明一較佳實施例之半導體元件之製法。
本發明提供一種半導體元件，其中半導體元件具有雙功函數金屬閘極(dual work function metal gate)。
第1A-1H圖顯示本發明之半導體元件100於各個製程階段的剖面圖。
請參見第1A圖，首先提供基板102，例如一矽基板。基板102可另外包括矽化鍺、砷化鎵、或其他適合的半導體材料。基板102尚可包括其他特徵，例如各種摻雜區域，如p型井或n型井，阻障層，及/或磊晶層。再者，基材102可以是半導體位於絕緣體之上，例如絕緣層上覆矽(silicon on insulator,SOI)。於另外的實施例中，基板102可包括一摻雜磊晶層，一梯度(gradient)半導體層，及/或尚可包括一半導體層位於另一不同類型之半導體層之上，例如矽層位於矽化鍺層之上。於其他實施例中，一化合物半導體基材可包括多層矽結構，或者是含有多層化合物半導體結構之矽基材。
此外，可形成絕緣結構(圖中未顯示)於基板102之中，例如淺溝隔離結構(shallow trench isolation,STI)，用以隔 離基板102之主動區域。隔離結構可由氧化矽，氮化矽，氮氧化矽，摻雜氟的矽酸鹽(FSG)，及/或本領域熟知之低介電常數(low k)材料所組成。
接著，形成虛設閘極(dummy gate)104於基板102之上，其中虛設閘極104可包括摻雜或未摻雜之多晶矽(doped or undoped poly-crystalline silicon)、金屬(如鉭、鈦、鉬、鎢、鉑、鋁、鉿、釕)、金屬矽化物(如矽化鈦、碳化矽、矽化鎳、矽化鉭)、金屬氮化物(如氮化鈦、氮化鉭)、其他導電材料或上述之組合。於一實施例中，虛設閘極104為多晶矽，虛設閘極104可由低壓化學沉積法(low-pressure chemical vapor deposition,LPCVD)所形成。
之後，形成層間介電層(inter-layer dielectric layer,ILD)108於虛設閘極104與基板102之上。層間介電層(ILD)108可藉由原子層沉積法(ALD)、物理氣相沉積法(PVD)、化學氣相沉積法(CVD)或其他沉積方法所形成。層間介電層(ILD)108可包括摻雜或未摻雜之氧化矽，雖然亦可使用其他材料，例如摻雜矽酸鹽玻璃之氮化矽、高介第電常數材料、上述之組合，或其他類似之材料。
此外，於形成形成層間介電層(ILD)108之前，尚可形成間隙壁106於基板102之上與虛設閘極104之側壁上。可藉由坦覆式沉積一或多層間隙壁層於基板102與虛設閘極104之側壁上。間隙壁106可包括氮化矽、氮氧化物、碳化矽、氮氧化矽、氧化物或其他材料。間隙壁106可藉由例如化學氣相沉積法(CVD)、電漿增強型氣相沉積法(plasma enhanced CVD)、 濺鍍(sputter)或其他熟知的沉積方法而形成。須注意的是，本發明雖顯示形成間隙壁106，然而，於其他實施例中，亦可不形成間隙壁。
此外，亦可形成源極/汲極區(未顯示於圖中)於基板102中虛設閘極104的相對兩側，因此，藉由源極/汲極區以定義出一通道區域(channel region)位於虛設閘極104下方。
請再次參見第1A圖，接著對層間介電層108進行第一化學機械研磨製程(chemical mechanical polishing,CMP)，以暴露虛設閘極104之上表面104a。
請參見第1B圖，形成金屬層110於虛設閘極104之上表面104a之上。金屬層110可以是p+型金屬或n+型金屬。金屬層110可藉由原子層沉積法(ALD)、物理氣相沉積法(PVD)、化學氣相沉積法(CVD)或其他沉積方法而形成。
於一實施例中，當半導體元件為PMOS時，金屬層110為n+型金屬層。於另一實施例中，當半導體元件為NMOS時，金屬層110為p+型金屬層。
請參見第1C圖，移除虛設閘極104，以形成於溝槽(trench)120於層間介電層108中，其中溝槽120具有第一寬度D1。
請參見第1D圖，順應性地形成閘極介電層122於溝槽120中。閘極介電層122可藉由原子層沉積法(atomic layer deposition,ALD)、化學氣相沉積法(chemical vapor deposition,CVD)或其他適合的方法形成。閘極介電層122之厚度可為約5埃~70埃，較佳為約5-50埃。
另外，閘極介電層122之材料包括高介電常數材料層，例如氧化鉿(HfO2)、氧化鋯(ZrO2)、氧化鈦(TiO2)、氧化鋁(Al2O3)、氧矽化鉿(HfSiO)、氮氧矽化鉿(HfSiON)、氧鉭化鉿(HfTaO)、氧鈦化鉿(HfTiO)、氧鋯化鉿(HfZrO)或上述之組合。
請參見第1E圖，順應性地形成第一導電類型金屬層124於閘極介電層122之上。第一導電類型金屬層124可藉由原子層沉積法(atomic layer deposition,ALD)、化學氣相沉積法(chemical vapor deposition,CVD)或其他適合的方法形成。第一導電類型金屬層124之厚度可為約4 nm~20 nm。
於一實施例中，當半導體元件為PMOS時，第一導電類型金屬層124為n+型金屬層。
於另一實施例中，當半導體元件為NMOS時，第一導電類型金屬層124為p+型金屬層。
上述之n+型金屬層之功函數介於4.1-4.9，n+型金屬層包括鈧(scandium,Sc)、鋯(zirconium,Zr)、鉿(hafnium,Hf)、鋁(aluminum,Al)、鈦(titanium,Ti)、鉭(tantalum,Ta)或鈮(niobium,Nb)。
上述之p+型金屬層之功函數介於4.7-5.0。p+型金屬層包括鎢(tungsten,W)、鉑(platinum,Pt)、釕(ruthenium,Ru)、鉬(molybdenum,Mo)、碳化鈦(titanium carbide,TiC)、碳化鋯(zirconium arbide,ZrC)、碳化鉭(tantalum carbide,TaC)、碳化鎢(tungsten carbide,WC)、氮化鈦(titanium nitride,TiN)、氮化鉭(tantalum nitride,TaN)或氧化釕(ruthenium oxide,RuO)。
請參見第1F圖，移除位於金屬層110之上的第一導 電類型金屬層124與閘極介電層122，以形成縫隙(gap)125於層間介電層108中並暴露部份的閘極介電層122。
此外，須注意的是，於移除步驟之後，閘極介電層122具有U型結構，且U型結構具有一水平部份122a與兩垂直部份122b，且兩垂直部份122b位於水平部份122a的相對末端(vertical portion is located at opposite ends of the horizontal portion)，且第一導電類型金屬層124相鄰於U型閘極介電層122之垂直部份122b。
可藉由對第一導電類型金屬層124進行一蝕刻製程，如乾式蝕刻製程(例如非等向性蝕刻)，以使第一導電類型金屬層124之一部分留在閘極介電層122之垂直部份122b之側壁。
此外，縫隙125具有第二寬度D2，其中溝槽120之第一寬度D1大於縫隙125之第二寬度D2。
請參見第1G圖，填充第二導電類型金屬層126於縫隙125中，其中第二導電類型金屬層126夾置於兩個第一導電類型金屬層124之間，以形成雙功函數金屬閘極層(dual work function metal gate)130。
於一實施例中，當半導體元件為PMOS時，第一導電類型金屬層124為n+型金屬層，而第二導電類型金屬層126為p+型金屬層。
於另一實施例中，於當半導體元件為NMOS時，第一導電類型金屬層124為p+型金屬層，第二導電類型金屬層126為n+型金屬層。
請參見第1H圖，對第二導電類型金屬層126與金屬層110進行第二化學機械研磨製程(CMP)，以暴露雙功函數金屬閘極層130之上表面，以形成本發明之半導體元件100。
本發明另外提供一種半導體元件100，請參見第1H圖，半導體元件100包括：基板102；U型閘極介電層122形成於基板102之上；雙功函數金屬閘極層130形成於U型閘極介電層122之內側，其中雙功函數金屬閘極層130包括第一導電類型金屬層124與第二導電類型金屬層126。
U型閘極介電層122具有水平部份122a與兩垂直部份122b，且兩垂直部份122b位於水平部份122a的相對末端。另外，雙功函數金屬閘極層130包括：兩個第一導電類型金屬層124相鄰於U型閘極介電層122之垂直部份122b；以及第二導電類型金屬層126夾置於兩個第一導電類型金屬層124之間。
舉例而言，當半導體元件為PMOS時，第一導電類型金屬層124為n+金屬層，第二導電類型金屬層126為p+金屬層，亦即p+金屬層夾置於n+金屬層。由於位於中間的p+金屬層具有較高的功函數，因此對於在p+金屬層下方的P-通道(p-channel)，雙功函數金屬閘極層具有較高的臨界電壓(Vth)，而位於兩側的n+金屬層因為具有較低的功函數，因此可幫助降低n+金屬層與汲極之間的閘極引發汲極漏電流(GIDL)。
綜上所述，相較於習知的單一功函數金屬閘極結構，本發明之雙功函數金屬閘極層中具有兩種不同功函數之金屬層，不但可提高臨界電壓(Vth)，亦可降低閘極引發汲極漏電流(GIDL)。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體元件
102‧‧‧基板
106‧‧‧間隙壁
108‧‧‧層間介電層
122‧‧‧閘極介電層
122a‧‧‧閘極介電層之水平部份
122b‧‧‧閘極介電層之垂直部份
124‧‧‧第一導電類型金屬層
126‧‧‧第二導電類型金屬層
130‧‧‧雙功函數金屬閘極

Claims (18)

  1. 一種半導體結構，包括：一基板；一U型閘極介電層形成於該基板之上；以及一雙功函數金屬閘極層形成於該U型閘極介電層之內側，其中雙功函數金屬閘極層包括兩個第一導電類型金屬層與一第二導電類型金屬層，其中該兩個第一導電類型金屬層與該第二導電類型金屬層皆直接接觸該U型閘極介電層，該第二導電類型金屬層夾置於該兩個第一導電類型金屬層之間，且該第一導電類型金屬層為n+型金屬層，該第二導電類型金屬層為p+型金屬層。
  2. 如申請專利範圍第1項所述之半導體結構，其中該U型閘極介電層具有一水平部份與兩垂直部份，且兩垂直部份位於該水平部份的相對末端。
  3. 如申請專利範圍第2項所述之半導體結構，其中該兩個第一導電類型金屬層相鄰於該U型閘極介電層之垂直部份。
  4. 如申請專利範圍第1項所述之半導體結構，其中該n+型金屬層之功函數介於4.1-4.9。
  5. 如申請專利範圍第1項所述之半導體結構，其中該n+型金屬層包括鈧(scandium,Sc)、鋯(zirconium,Zr)、鉿(hafnium,Hf)、鋁(aluminum,Al)、鈦(titanium,Ti)、鉭(tantalum,Ta)或鈮(niobium,Nb)。
  6. 如申請專利範圍第1項所述之半導體結構，其中該p+型金屬層之功函數介於4.7-5.0。
  7. 如申請專利範圍第1項所述之半導體結構，其中該p+型金屬層包括鎢(tungsten,W)、鉑(platinum,Pt)、釕(ruthenium,Ru)、鉬(molybdenum,Mo)、碳化鈦(titanium carbide,TiC)、碳化鋯(zirconium arbide,ZrC)、碳化鉭(tantalum carbide,TaC)、碳化鎢(tungsten carbide,WC)、氮化鈦(titanium nitride,TiN)、氮化鉭(tantalum nitride,TaN)或氧化釕(ruthenium oxide,RuO)。
  8. 如申請專利範圍第1項所述之半導體結構，其中該U型閘極介電層包括高介電常數材料(high-k dielectric material)。
  9. 如申請專利範圍第8項所述之半導體結構，其中該高介電常數材料(high-k)包括氧化鉿(HfO2)、氧化鋯(ZrO2)、氧化鈦(TiO2)、氧化鋁(Al2O3)、氧矽化鉿(HfSiO)、氮氧矽化鉿(HfSiON)、氧鉭化鉿(HfTaO)、氧鈦化鉿(HfTiO)、氧鋯化鉿(HfZrO)或上述之組合。
  10. 如申請專利範圍第1項所述之半導體結構，尚包括：一層間介電層(inter-layer dielectric layer)，形成於該基板之上與該U型閘極介電層之側壁上。
  11. 如申請專利範圍第10項所述之半導體結構，尚包括：一間隙壁，形成於該基板之上，其中該間隙壁(spacer)介於該層間介電層與該雙功函數金屬閘極層之間。
  12. 一種半導體結構之製法，包括以下步驟：提供一基板；形成一虛設閘極(dummy gate)於該基板之上；形成層間介電層(inter-layer dielectric layer)於該虛設閘 極與該基板之上；對該層間介電層進行一第一化學機械研磨製程(chemical mechanical polishing,CMP)，以暴露該虛設閘極之上表面；形成一金屬層於該虛設閘極上表面之上；移除該虛設閘極，以形成一溝槽(trench)於該層間介電層中；順應性形成一閘極介電層於該溝槽中；順應性形成一第一導電類型金屬層於該閘極介電層之上，且該第一導電類型金屬層為n+型金屬層；移除位於該金屬層之上的該第一導電類型金屬層與該閘極介電層，以形成一縫隙(gap)於層間介電層中，其中該縫隙暴露該部份的閘極介電層；填充一第二導電類型金屬層於該縫隙中，且該第二導電類型金屬層為p+型金屬層，其中該第二導電類型金屬層夾置於兩個第一導電類型金屬層之間，以形成一雙功函數金屬閘極層(dual work function metal gate)，其中該兩個第一導電類型金屬層與該第二導電類型金屬層皆直接接觸該U型閘極介電層；以及對該第二導電類型金屬層與該金屬層進行一第二化學機械研磨製程(CMP)，以暴露雙功函數金屬閘極層之上表面。
  13. 如申請專利範圍第12項所述之半導體結構之製法，其中該形成層間介電層(inter-layer dielectric layer)之前，尚包括：形成間隙壁(spacer)於該虛設閘極之側壁(sidewall)。
  14. 如申請專利範圍第12項所述之半導體結構之製法，其中該金屬層為p+型金屬層或n+型金屬層。
  15. 如申請專利範圍第12項所述之半導體結構之製法，於移除位於該金屬層之上的該第一導電類型金屬層與該閘極介電層之後，其中該閘極介電層具有一U型結構，且該U型結構具有一水平部份與兩垂直部份，且兩垂直部份位於該水平部份的相對末端。
  16. 如申請專利範圍第15項所述之半導體結構之製法，其中該兩個第一導電類型金屬層相鄰於該U型結構之垂直部份。
  17. 如申請專利範圍第12項所述之半導體結構之製法，其中該閘極介電層包括高介電常數材料(high-k)。
  18. 如申請專利範圍第12項所述之半導體結構之製法，其中該溝槽之寬度大於該縫隙之寬度。
TW102127219A 2013-03-18 2013-07-30 半導體結構與其製法 TWI553864B (zh)

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