TWI549267B - Active devices array substrate - Google Patents

Description

Active device array substrate

The present disclosure relates to an active device array substrate.

With the continuous development of display technology, flat-panel displays have gradually replaced traditional displays in response to the needs of future displays, including thin, sturdy, portable, easy-to-read information and multi-functional integration. Combined with the future life situation, the smart lifestyle will emphasize interaction and connection, personalization and accessibility of information. Flat-panel display products such as notebook computers, monitors, monitors, televisions and e-books will More and more widely appearing beside you and me.

In a general flat panel display, the material of the flat layer is mostly an organic material, which has the characteristics of water absorption, so that moisture is transmitted into the display area through the flat layer, and the internal metal component is deteriorated. To overcome this problem, some manufacturers create grooves in the flat layer to prevent moisture from entering the display area through the flat layer. However, due to the large height difference between the trench and the flat layer, in the subsequent process, there may be metal remaining at the boundary between the flat layer and the trench, and these residual metals may be associated with other electrons. The line is electrically coupled, which in turn causes problems with resistive and capacitive loads. (Resistance-Capacitance loading; RC loading).

Therefore, how to effectively block the entry of moisture into the display area without affecting the electrical characteristics of the components is one of the most important topics in the flat panel display industry where there is still room for growth.

One aspect of the present invention is to provide an active device array substrate having a truncated structure disposed on at least one side of the flat layer adjacent to the trench, thereby truncating the conductor pattern that may be present to avoid an electrical problem that cannot be ignored.

According to one or more embodiments of the present invention, an active device array substrate includes a substrate body, a pixel circuit, a flat layer, and a conductor pattern. The pixel circuit is located on the substrate body. The planar layer is on the substrate body and at least partially overlaps the pixel circuit. The flat layer has a groove. The trench is located in a peripheral region of the substrate body and surrounds the pixel circuit. The flat layer has a truncated structure adjacent at least one side of the trench. The conductor pattern is located at least in the partial trench adjacent to the at least one side of the planar layer, and the conductor pattern has a plurality of discontinuous segments, and a gap exists between the two adjacent segments, the gap corresponding to the truncated structure of the planar layer.

In one or more embodiments of the invention, the truncated structure has a widest bottom and a narrowest end. The width of the truncated structure is reduced from the bottom to the end.

In one or more embodiments of the invention, the truncated structure has a widest bottom and a narrowest end. The distance from the bottom to the end of the truncated structure is greater than or equal to twice the width of the bottom.

In one or more embodiments of the present invention, the truncated junction described above A gap formed as a flat layer.

In one or more embodiments of the present invention, the above-described cut-off structure is a convex structure of a flat layer.

In one or more embodiments of the present invention, the protruding structure connects the flat layers on both sides of the groove such that the grooves are discontinuous, and the protruding structure includes at least one hole.

In one or more embodiments of the present invention, the trench includes a plurality of main holes and at least one reinforcing hole. The main holes are separated from each other such that there is a truncated structure between the two adjacent main holes. The reinforcing hole is separated from the main hole, but at least partially opposite to the truncated structure, wherein the protruding structure is at least partially between the main hole and the reinforcing hole.

In one or more embodiments of the present invention, the above-described cut-off structure has a serrated side surface.

In one or more embodiments of the present invention, the active device array substrate further includes a lead. The lead is electrically connected to the pixel circuit and at least partially between the flat layer and the substrate body. The orthographic projection of the lead on the substrate body at least partially overlaps the orthographic projection of the conductor pattern on the substrate body.

In one or more embodiments of the present invention, the pixel circuit includes a scan line, a data line, a thin film transistor, and a pixel electrode. The scan lines are electrically connected to the leads. The gate of the thin film transistor is electrically connected to the scan line. The source of the thin film transistor is electrically connected to the data line. The pixel electrode is electrically connected to the drain of the thin film transistor.

In one or more embodiments of the present invention, the pixel circuit includes a scan line, a data line, a thin film transistor, and a pixel electrode. Data line Sex connection leads. The gate of the thin film transistor is electrically connected to the scan line. The source of the thin film transistor is electrically connected to the data line. The pixel electrode is electrically connected to the drain of the thin film transistor.

In one or more embodiments of the invention, the trenches are located in the planar layer such that the planar layers have opposite sides of the adjacent trenches. The number of the truncated structures is plural, and the truncated structures are respectively located on opposite sides of the flat layer adjacent to the grooves.

According to one or more embodiments of the present invention, an active device array substrate includes a substrate body, a pixel circuit, and a planar layer. The substrate body has a display area and a peripheral area surrounding the display area. The pixel circuit is located on the display area of the substrate body. The planar layer is on the substrate body and at least partially overlaps the pixel circuit. The planar layer has a trench located in a peripheral region of the substrate body and surrounding the pixel circuit. The flat layer has a truncated structure adjacent at least one side of the trench. The truncated structure has the widest bottom and the narrowest end. The width of the truncated structure is reduced from the bottom to the end, and the distance of the truncated structure from the bottom to the end is greater than or equal to twice the width of the bottom.

In one or more embodiments of the present invention, the above-described cut-off structure is a notch of a flat layer.

In one or more embodiments of the present invention, the above-mentioned cut-off structure is a convex structure in which a flat layer protrudes toward the groove.

In one or more embodiments of the present invention, the above-described cut-off structure has a serrated side surface.

In one or more embodiments of the invention, the trenches are located in the planar layer such that the planar layers have opposite sides of the adjacent trenches. Truncated knot The number of structures is plural, and the truncated structures are respectively located on opposite sides of the flat layer adjacent to the grooves.

2-2‧‧‧ segments

3-3‧‧‧ segments

4‧‧‧Area

8-8‧‧‧ segments

100‧‧‧Active component array substrate

110‧‧‧Substrate body

120‧‧‧pixel circuit

122‧‧‧ scan line

124‧‧‧Information line

126‧‧‧film transistor

128‧‧‧ pixel electrodes

130‧‧‧flat layer

132‧‧‧ trench

133‧‧‧ holes

133M‧‧‧ main hole

133S‧‧‧Reinforced holes

134‧‧‧Truncate structure

135‧‧ ‧ protective layer

136‧‧‧ side

138‧‧‧ truncated structure

140‧‧‧ conductor pattern

142‧‧‧frag

150‧‧‧ lead

160‧‧‧ lead

170‧‧‧ shading metal layer

AR‧‧‧ display area

B‧‧‧ bottom

BW‧‧‧Width

C‧‧‧Channel area

D‧‧‧汲

E‧‧‧ distance

G‧‧‧ gate

GD‧‧ ‧ gate driver

GI‧‧‧ gate dielectric layer

PR‧‧‧ surrounding area

S‧‧‧ source

SD‧‧‧Source Driver

T‧‧‧ end

TH‧‧‧Tongkong

1 is a top plan view of an active device array substrate in accordance with an embodiment of the present invention.

Figure 2 is a cross-sectional view taken along line 2-2 of Figure 1.

Figure 3 is a cross-sectional view along line 3-3 of Figure 1.

Fig. 4 is an enlarged view of a region 4-4 of Fig. 1.

FIG. 5 is an enlarged view of a region of an active device array substrate according to another embodiment of the present invention.

FIG. 6 is an enlarged view of an area of an active device array substrate according to still another embodiment of the present invention.

Figure 7 is a plan view showing the single pixel circuit of Figure 1.

Figure 8 is a cross-sectional view taken along line 8-8 of Figure 7.

FIG. 9 is an enlarged view of a region of an active device array substrate according to another embodiment of the present invention.

FIG. 10 is an enlarged view of an area of an active device array substrate according to still another embodiment of the present invention.

In the following, a plurality of embodiments of the present invention will be disclosed in the drawings. For the sake of clarity, many practical details will be described in the following description. Bright. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

When an element is referred to as being "an" or "an" or "an" In contrast, when an element is referred to as being "directly on" another element, it is meant that no other element exists between the two.

FIG. 1 is a plan view of an active device array substrate 100 in accordance with an embodiment of the present invention. As shown in FIG. 1, the active device array substrate 100 includes a substrate body 110, a pixel circuit 120, and a flat layer 130. The pixel circuit 120 is located on the substrate body 110. The planarization layer 130 is located on the substrate body 110 and at least partially overlaps the pixel circuit 120.

Since the material of the flat layer 130 may be an organic material having the characteristics of water absorption, in the present embodiment, the flat layer 130 may have the trench 132 surrounding the pixel circuit 120. By the presence of the grooves 132, moisture can be blocked from entering and corroding the pixel circuit 120. In the present embodiment, the substrate body 110 described above can be divided into a display area AR and a peripheral area PR. The pixel circuit 120 is located in the display area AR. The trench 132 is located in the peripheral region PR and surrounds the display region AR where the pixel circuit 120 is located to block the entry of moisture into the pixel circuit 120.

However, since the thickness of the flat layer 130 is thick, a large height difference is generated between the flat layer 130 adjacent to the boundary of the trench 132. If it is desired to form another conductor pattern layer, for example, at a position overlapping the pixel circuit 120 In order to form a light-shielding metal layer, the associated lithography process may accumulate a thick photoresist on the flat layer 130 adjacent to at least one side of the trench 132, so that the subsequent etching process cannot completely remove the conductor here, but the conductor pattern Remains here. Once the residual conductor pattern is connected to a certain length, it may cause an electrical problem that cannot be ignored.

Figure 2 is a cross-sectional view taken along line 2-2 of Figure 1. As shown in FIG. 2, since the conductor pattern 140 may remain and at least partially overlap with the lead 150 located under the flat layer 130, if the conductor pattern 140 is connected in series for a certain length or even in a ring shape, it may result in The electrical coupling with the lower lead 150 increases the resistance-capacitance loading (RC loading) and affects the operation of the pixel circuit 120. In the first and second figures, the lead 150 under the flat layer 130 may be a lead electrically connected to the scan line of the pixel circuit 120 and the gate driver GD. That is, the leads 150 of FIGS. 1 and 2 may belong to the same patterned metal layer as the scan lines of the pixel circuit 120, such as the first metal layer. However, at other locations, the leads under the planar layer 130 may also be leads that are electrically connected to the data lines of the pixel circuit 120. For example, FIG. 3 is a cross-sectional view taken along line 3-3 of FIG. 1. The leads 160 under the flat layer 130 shown in FIGS. 1 and 3 are electrically connected to the data lines of the pixel circuit 120 and the leads of the source driver SD. That is, the leads 160 of FIGS. 1 and 3 may belong to the same patterned metal layer as the data lines of the pixel circuit 120, such as the second metal layer.

More specifically, the orthographic projection of the leads 150, 160 described above on the substrate body 110 can at least partially overlap the orthographic projection of the conductor pattern 140 on the substrate body 110. In addition, the above-mentioned leads 150, 160 can be at least partially The portion is located between the flat layer 130 and the substrate body 110. Since the leads 150 and 160 and the conductor pattern 140 at least partially overlap, if the conductor pattern 140 reaches a certain size, the resistance-capacitance load of the leads 150 and 160 may increase, which may affect the operation of the pixel circuit 120.

In order to improve the above phenomenon, the present embodiment is provided with a cut-off structure in the flat layer 130 adjacent to the sidewall of the trench 132. Fig. 4 is an enlarged view of a region 4 of Fig. 1. As shown in FIG. 4, in the present embodiment, a truncation structure 134 is provided on the side wall of the flat layer 130 adjacent to the trench 132. By the presence of the truncation structure 134, even if the conductor pattern 140 remains in the flat layer 130 adjacent to the sidewall of the trench 132, the truncated structure 134 is broken, without being connected in series for a certain length, resulting in negligible electrical properties. problem.

More specifically, the above-described cut-off structure 134 has the widest bottom B and the narrowest end T. The width of the truncated structure 134 is reduced from the bottom B to the end T, and the distance E of the truncated structure 134 from the bottom B to the end T is greater than or equal to twice the width BW of the bottom B. Since the conductor pattern 140 is at least not easily left at the end portion T of the cut structure 134, even if the conductor pattern 140 is present, the conductor pattern 140 is at least broken at the cut structure 134 without being connected in series for a certain length, resulting in negligible Electrical problems.

That is, the conductor pattern 140 is broken into a plurality of discrete segments 142. There is a gap between the two adjacent segments 142 that corresponds to at least the truncated structure 134. By breaking the conductor pattern 140 into a plurality of discontinuous segments 142 by the truncation structure 134, in addition to reducing the RC load of the leads 150, 160, the electrostatic charge can be reduced through the conductor pattern 140, which can damage the internal wiring.

In the present embodiment, the trenches 132 are located in the planarization layer 130 such that the planarization layer 130 has adjacent sides of the trenches 132. The number of the truncated structures 134 described above is plural. These truncation structures 134 can be located on opposite sides of the planar layer 130 adjacent the trenches 132, respectively. It should be understood that the configuration of the above-described truncated structure 134 is merely illustrative and not intended to limit the present invention. If the actual conditions permit, the number of the truncated structures 134 may also be one, or only one of the flat layers 130 adjacent to the trenches 132. side. Those having ordinary knowledge in the technical field to which the present invention pertains should flexibly select the configuration of the truncation structure 134 as needed.

Although FIG. 4 illustrates the truncated structure 134 as a notch of the planar layer 130, this does not limit the invention. In another embodiment of the present invention, the above-mentioned cut-off structure 134 may also be a protruding structure in which the flat layer 130 protrudes toward the groove 132 (as shown in FIG. 5). Those having ordinary knowledge in the technical field to which the present invention pertains should flexibly select a specific embodiment of the truncation structure 134 according to actual needs.

Further, although FIGS. 4 and 5 each show the side of the cut-off structure 134 as a plane, this does not limit the present invention. In still another embodiment of the present invention, the above-described cut-off structure 134 may also have a serrated side surface 136 (as shown in FIG. 6). Those having ordinary knowledge in the technical field to which the present invention pertains should flexibly select the shape of the side surface of the cut structure 134 as needed.

FIG. 7 is a plan view showing the single pixel circuit 120 of FIG. 1. Figure 8 is a cross-sectional view taken along line 8-8 of Figure 7. As shown in FIGS. 7-8, the pixel circuit 120 includes a scanning line 122, a data line 124, a thin film transistor 126, and a pixel electrode 128. Scan line 122 is interleaved with data line 124. The thin film transistor 126 includes a gate G, a gate dielectric layer GI, a channel region C, a source S, and a gate Extreme D. The gate G is electrically connected to the scan line 122. The gate dielectric layer GI is at least between the channel region C and the gate G. The source S and the drain D are located on both sides of the channel region C. The source S is electrically connected to the data line 124. The flat layer 130 covers the thin film transistor 126 and has a through hole TH exposing the drain D. The pixel electrode 128 is at least partially located on the flat layer 130 and electrically connected to the drain D through the through hole TH.

In the present embodiment, the light shielding metal layer 170 may be provided between the flat layer 130 and the pixel electrode 128. The light-shielding metal layer 170 can shield the channel region C of the thin film transistor 126 to prevent the channel region C of the thin film transistor 126 from being exposed to ambient light to generate a photo-leakage current. The conductor pattern 140 of FIGS. 2 and 3 may belong to the same patterned metal layer as the light shielding metal layer 170, such as a third metal layer. However, this does not limit the invention, and the conductor pattern 140 may belong to the same patterned conductor layer as any of the conductor layers formed after the planarization layer 130. In another embodiment, when there is no light shielding metal layer 170 between the flat layer 130 and the pixel electrode 128, the conductor pattern 140 may belong to the same patterned conductor layer as the pixel electrode 128.

In the present embodiment, the protective layer 135 may be selectively provided between the flat layer 130 and the thin film transistor 126. The protective layer 135 can cover the data line 124, the source S, the drain D, the channel region C and the lead 160 depicted in FIG. 3 to prevent these components from being affected or contaminated by environmental factors. The material of the protective layer 135 may be an inorganic dielectric material such as tantalum nitride, cerium oxide, cerium oxynitride or any combination thereof.

The first metal layer (eg, scan line 122, gate G and lead 150), second metal layer (eg, source S, drain D, data line 124 and lead 160) and third metal layer (eg, : shading metal layer 170 and conductor pattern The material of the case 140) may be any metal such as titanium, molybdenum, chromium, niobium, aluminum, copper, silver, gold or any combination thereof, which may be formed by a film, a lithography and an etching process. More specifically, the thin film process described in this paragraph may be a physical vapor deposition method such as sputtering.

The material of the gate dielectric layer GI may be any dielectric material such as tantalum nitride, hafnium oxide, hafnium oxynitride, graphene oxide, graphene nitride, graphene oxide, polymer material or any of the above. The combination can be formed by a film, a lithography, and an etching process.

The material of the channel region C may be any semiconductor material, such as amorphous germanium, polycrystalline germanium, single crystal germanium, oxide semiconductor, graphene or any combination thereof, which may be formed into a film, Photolithography and etching processes.

The material of the pixel electrode 128 may be any conductive material, such as indium tin oxide, indium zinc oxide, zinc aluminum oxide, graphene, carbon nanotubes or any combination thereof, which may be formed by film or lithography. And etching process.

The material of the flat layer 130 described above may be an organic material, for example, an acrylic polymer, which may be formed by, for example, a spin coating method.

FIG. 9 is an enlarged view of a region of an active device array substrate according to another embodiment of the present invention. In FIG. 9, the flat layer 130 has a truncated structure 138. More specifically, the truncated structure 138 is a convex structure and connects the flat layers 130 on both sides of the trench 132, so that the trench 132 becomes a discontinuous trench, and the truncated structure 138 may include at least one hole 133, and the hole 133 Do not It is in communication with the groove 132.

In the present embodiment, although the conductor pattern 140 may remain in the trench 132 and/or the hole 133, since the trench 132 and/or the hole 133 are separated by the cut structure 138, the trench 132 and/or the hole 133 The conductor pattern 140 in the middle will not be able to be connected in series to a certain size. In the present embodiment, the conductor pattern 140 located in the trench 132 and/or the hole 133 can be considered as a discontinuous segment 142. There is a gap between the two adjacent segments 142, and the gap will be related to the truncated structure 138. correspond. In the present embodiment, the hole 133 can prevent the moisture from entering the display area where the pixel circuit is located from the cut structure 138 on both sides of the connection groove 132, and corrode the pixel circuit.

In other embodiments, as shown in FIG. 10, the groove 132 includes a plurality of main holes 133M and a plurality of reinforcing holes 133S, which are successively arranged or staggered but not connected, and have a truncation between any two successively arranged main holes 133M. The structure 138, and the two main rows of the main holes 133M are arranged in a staggered arrangement such that the truncated structure 138 of any two rows becomes a non-linear structure, and the reinforcing holes 133S are further disposed corresponding to the truncating structure 138 for blocking the direct entry of moisture into the pixel circuit. The conductor pattern 140 may be prevented from forming a large conductive pattern in series to affect the pixel circuit, wherein the width of the main hole 133M is substantially equal to the width of the reinforcing hole 133S, and the length of the main hole 133M is greater than the length of the reinforcing hole 133S. Those having ordinary knowledge in the technical field to which the present invention pertains should flexibly select a specific embodiment of the main hole 133M and the reinforcing hole 133S according to actual needs.

The active device array substrate 100 provided by the above embodiments may be applied to various displays including, but not limited to, an electrophoretic display. (Electro-Phoretic Display; EPD), Liquid Crystal Display (LCD) and Active-Matrix Organic Light-Emitting Diode Display (AMOLED Display). It should be understood that the application range of the active device array substrate 100 is merely illustrative and is not intended to limit the present invention. Those skilled in the art to which the present invention pertains should flexibly select the active device array substrate 100 according to actual needs. Application method.

As described above, the flat layer of the above-described embodiment of the present invention is provided with a cut-off structure on the side adjacent to the groove, so that electrical problems due to residual metal can be avoided. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and it is to be understood by those skilled in the art that the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.

130‧‧‧flat layer

132‧‧‧ trench

134‧‧‧Truncate structure

140‧‧‧ conductor pattern

142‧‧‧frag

B‧‧‧ bottom

BW‧‧‧Width

E‧‧‧ distance

T‧‧‧ end

Claims (17)

An active device array substrate comprising: a substrate body; at least one pixel circuit on the substrate body; at least one flat layer on the substrate body and at least partially overlapping the pixel circuit, the flat layer having a a trench located in a peripheral region of the substrate body and surrounding the at least one pixel circuit, the planar layer having at least one truncated structure adjacent to at least one side of the trench; and a conductor pattern at least partially located in the trench And adjacent to the at least one side of the planar layer, and the conductor pattern comprises a plurality of discontinuous segments, and a gap exists between the two adjacent segments, the gap corresponding to the truncated structure of the planar layer. The active device array substrate of claim 1, wherein the truncated structure has one of the widest widths and one of the narrowest ends, and the width of the truncated structure is reduced from the bottom to the end. The active device array substrate according to claim 1, wherein the truncated structure has one of the widest widths and one of the narrowest ends, wherein the distance from the bottom to the end of the truncated structure is greater than Or equal to twice the width of the bottom. The active device array substrate of claim 1, wherein the truncated structure is at least one notch of the flat layer. The active device array substrate according to claim 1, wherein the cut structure is at least one protruding structure of the flat layer. The active device array substrate according to claim 5, wherein the protruding structure connects the flat layer on both sides of the groove such that the groove is discontinuous, and the protruding structure comprises at least one hole. The active device array substrate of claim 5, wherein the trench comprises: a plurality of main holes, the main holes being separated from each other such that the truncated structure exists between the two adjacent main holes; At least one reinforcing hole is spaced apart from the main holes, but at least partially opposite the cutting structure, wherein the protruding structure is at least partially interposed between the main holes and the reinforcing holes. The active device array substrate of claim 1, wherein the truncated structure has at least one serrated side surface. The active device array substrate according to claim 1, further comprising: at least one lead electrically connected to the pixel circuit, the lead being at least partially located between the flat layer and the substrate body, the lead being on the substrate The orthographic projection on the body at least partially overlaps the orthographic projection of the conductor pattern on the substrate body. The active device array substrate according to claim 9, wherein the pixel circuit comprises: at least one scan line electrically connected to the lead; at least one data line; at least one thin film transistor, the gate of the thin film transistor The scan line is electrically connected, the source of the thin film transistor is electrically connected to the data line, and at least one pixel electrode is electrically connected to the drain of the thin film transistor. The active device array substrate according to claim 9, wherein the pixel circuit comprises: at least one scan line; at least one data line electrically connected to the lead; at least one thin film transistor, the gate of the thin film transistor The scan line is electrically connected, the source of the thin film transistor is electrically connected to the data line, and at least one pixel electrode is electrically connected to the drain of the thin film transistor. The active device array substrate according to claim 1, wherein the groove is located in the flat layer such that the flat layer has opposite sides of the groove, and the number of the cut structures is plural. The truncated structures are respectively located on the opposite sides of the flat layer adjacent to the trench. An active device array substrate comprising: a substrate body having a display area and surrounding one of the display areas At least one pixel circuit on the display area of the substrate body; at least one flat layer on the substrate body and at least partially overlapping the pixel circuit, the flat layer having at least one trench located at the The peripheral region of the substrate body surrounds the at least one pixel circuit, the planar layer having at least one truncated structure adjacent to at least one side of the trench, the truncated structure having one of the widest widths and one of the narrowest ends The width of the truncation structure is reduced from the bottom portion to the end portion, and the distance from the bottom portion to the end portion of the truncation structure is greater than or equal to twice the width of the bottom portion. The active device array substrate of claim 13, wherein the truncated structure is at least one notch of the flat layer. The active device array substrate according to claim 13, wherein the cutting structure is at least one protruding structure in which the flat layer protrudes toward the groove. The active device array substrate of claim 13, wherein the truncated structure has at least one serrated side surface. The active device array substrate according to claim 13, wherein the groove is located in the flat layer such that the flat layer has opposite sides of the groove, and the number of the cut structures is plural. The truncated structures are respectively located on the opposite sides of the flat layer adjacent to the trench.