CN108389868A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN108389868A CN108389868A CN201810163131.XA CN201810163131A CN108389868A CN 108389868 A CN108389868 A CN 108389868A CN 201810163131 A CN201810163131 A CN 201810163131A CN 108389868 A CN108389868 A CN 108389868A
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- 239000000758 substrate Substances 0.000 title claims abstract description 98
- 238000005520 cutting process Methods 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims description 83
- 229910052751 metal Inorganic materials 0.000 claims description 83
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the invention discloses a kind of array substrates, including：Underlay substrate；Multiple connection terminals are located at the boundary on underlay substrate and close to underlay substrate and are arranged, and the connection terminal with flexible PCB for being electrically connected；Flatness layer is located on underlay substrate, and the first side circle of the flatness layer is located at the outside of connection terminal；Multiple pixel electrodes are located on flatness layer；Wherein, the first side circle at least partly region of the flatness layer is recessed inwardly to form multiple recessed portions, for by cutting the planar portions formed between two neighboring recessed portion.The embodiment of the invention also discloses a kind of display panels.Using the present invention, have the advantages that reduce short-circuit caused by kish.
Description
Technical field
The present invention relates to display technology fields, more particularly to a kind of array substrate and display panel.
Background technology
Display panel generally comprises array substrate, colored filter substrate and flexible PCB, the array substrate and coloured silk
Colo(u)r filter substrate mounting is together.Refer to Fig. 1, the array substrate include underlay substrate 110, multiple connection terminals 130,
Flatness layer 120, pixel electrode (not shown) etc., multiple connection terminals 130, flatness layer 120 are formed in underlay substrate
On 110, the pixel electrode is formed on flatness layer 120, and multiple connection terminals 130 pass through conducting resinl and the flexible electrical
Road plate electrical connection.Particularly, the flexible PCB is equipped with multiple signal terminals, and the signal terminal passes through conducting resinl point
It is not electrically connected with the corresponding connection terminal 130.
However, when forming pixel electrode, need the metal layer for depositing a flood first on flatness layer 120 and array base
On other regions of plate, the material of the metal layer is, for example, ITO, is then etched, developing forms pixel electrode, due to flat
There are bigger differences in height at the first side circle 150 of connection terminal 130 for layer 120, and flatness layer 120 is close to connection terminal
130 150 outside etching metal layer of first side circle may may have kish 140, to lead not enough completely
When signal terminal being caused to be electrically connected by conducting resinl with connection terminal 130, kish 140 can lead to the conducting particles in conducting resinl
Short circuit, or lead to adjacent two signal terminals short circuit, so as to cause high current exception, cause display screen to occur in display different
Often, the power consumption severely subnormal and when putting out screen.
Invention content
Technical problem to be solved of the embodiment of the present invention is, provides a kind of array substrate and display panel.It can mitigate
It is short-circuit caused by kish.
In order to solve the above-mentioned technical problem, first aspect present invention embodiment provides a kind of array substrate, including：
Underlay substrate；
Multiple connection terminals are located at the boundary on underlay substrate and close to underlay substrate and are arranged, multiple connecting pins
Son with flexible PCB for being electrically connected；
Flatness layer is located on underlay substrate, and the first side circle of the flatness layer is located at the outside of connection terminal；
Multiple pixel electrodes are located on flatness layer；
Wherein, the first side circle at least partly region of the flatness layer is recessed inwardly to form multiple recessed portions, and adjacent two
For by cutting the planar portions formed between a recessed portion.
In one embodiment of first aspect present invention, at least provided with a plane between two connection terminals of arbitrary neighborhood
Portion.
In one embodiment of first aspect present invention, the connection terminal includes lower metal layer and upper metal layer, under described
Metal layer is located at the lower section of the flatness layer, and the position digging that the flatness layer corresponds to the lower metal layer has first through hole, described
Upper metal layer is electrically connected across first through hole with the lower metal layer, and the upper metal layer with the flexible PCB for being electrically connected
It connects.
In one embodiment of first aspect present invention, the array substrate further includes gate insulating layer, the lower metal layer
On the gate insulating layer.
In one embodiment of first aspect present invention, the array substrate further includes gate insulating layer, the lower metal layer
Positioned at the lower section of the gate insulating layer, the position digging that the gate insulating layer corresponds to the lower metal layer has the second through-hole, institute
Metal layer is stated to be electrically connected with the lower metal layer across first through hole, the second through-hole.
In one embodiment of first aspect present invention, the array substrate includes viewing area and non-display area, the pixel
Electrode is located at the viewing area, and the non-display area is equipped with binding area, the connection terminal, the flatness layer first side circle
Positioned at the binding area.
Second aspect of the present invention embodiment provides a kind of display panel, including：
Array substrate comprising：
Underlay substrate；
Multiple connection terminals are located at the boundary on underlay substrate and close to underlay substrate and are arranged；
Flatness layer is located on underlay substrate, and the first side circle of the flatness layer is located at the outside of the connection terminal,
The first side circle at least partly region is recessed inwardly to form multiple recessed portions, is to pass through cutting between two neighboring recessed portion
The planar portions of formation；
Multiple pixel electrodes are located on flatness layer；
Flexible PCB is electrically connected with the array substrate by conducting resinl, and the flexible PCB is close to array base
Plate side includes multiple signal terminals, signal terminal electrical connection corresponding with the connection terminal.
In one embodiment of second aspect of the present invention, at least provided with a plane between two connection terminals of arbitrary neighborhood
Portion.
In one embodiment of second aspect of the present invention, the conducting resinl is anisotropic conductive adhesive paste.
In one embodiment of second aspect of the present invention, the connection terminal includes lower metal layer and upper metal layer, under described
Metal layer is located at the lower section of the flatness layer, and the position digging that the flatness layer corresponds to the lower metal layer has first through hole, described
Upper metal layer is electrically connected across first through hole with the lower metal layer, and the upper metal layer passes through conduction with the flexible PCB
Glue is electrically connected.
Implement the embodiment of the present invention, has the advantages that：
It is two neighboring since the first side circle at least partly region of the flatness layer is recessed inwardly to form multiple recessed portions
It is the planar portions formed by cutting between recessed portion, to which the kish in the outside of planar portions can also be cut away, plane
There is no kish in the outside in portion, lead to the possibility of flexible PCB short circuit so as to mitigate kish, can be with
High current is abnormal caused by preventing short circuit, and array substrate is all not in exception when showing and putting out screen.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of schematic diagram of array substrate of the prior art；
Fig. 2 is the schematic diagram after one embodiment of the invention array substrate is cut；
Fig. 3 is the enlarged drawing in circular dashed line region in Fig. 2；
Fig. 4 is the sectional view of one embodiment of the invention array substrate；
Fig. 5 is the schematic diagram before one embodiment of the invention array substrate is cut；
Shown by reference numeral：
110,310- underlay substrates；120,320- flatness layers；130,330- connection terminals；140,340- kish；
150, the first sides 350- circle；331- first through hole；332- lower metal layers；The upper metal layers of 333-；351- planar portions；352- indents
Concave portion；The outer recessed portions of 353-；360- gate insulating layers；The second through-holes of 361-；370- pixel electrodes；380- conducting resinls；410- is aobvious
Show area；420- non-display areas；421- binds area；500- flexible PCBs；510- signal terminals.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment shall fall within the protection scope of the present invention.
The term " comprising " and " having " occurred in present specification, claims and attached drawing and their any changes
Shape, it is intended that cover and non-exclusive include.Such as contain the process of series of steps or unit, method, system, product or
Equipment is not limited to the step of having listed or unit, but further includes the steps that optionally not listing or unit or optional
Ground further includes for the intrinsic other steps of these processes, method, product or equipment or unit.In addition, term " first ", " the
Two " and " third " etc. are and to be not intended to describe specific sequence for distinguishing different objects.
The embodiment of the present invention provides a kind of array substrate, refers to Fig. 2-Fig. 4, the array substrate includes underlay substrate
310, multiple connection terminals 330, flatness layer 320 and pixel electrode 370.
In the present embodiment, the underlay substrate 310 can be the transparent substrates such as glass substrate, plastic base, described
Underlay substrate 310 can be flexible base board, can also be non-flexible substrate.
In the present embodiment, multiple connection terminals 330 are formed on the underlay substrate 310 and close to underlay substrates
310 boundary setting, here it is the right side boundary setting close to underlay substrate 310, multiple connection terminals 330 are only each other
It stands and is arranged parallel to each other.In the present embodiment, the connection terminal 330 is elongated, and each connection terminal 330 transversely prolongs
It stretches, multiple connection terminals 330 are whole to be extended longitudinally.In the present embodiment, multiple connection terminals 330 respectively with battle array
The driving circuits such as gate drivers, data driver on row substrate are electrically connected, and the connection terminal 330 is for receiving driving letter
Number equal signals are simultaneously conveyed to corresponding driving circuit.
In the present embodiment, multiple connection terminals 330 with flexible PCB 500 for being electrically connected, the flexible electrical
500 one end of road plate be equipped with multiple signal terminals 510 (referring to Fig. 4), generally the quantity of the signal terminal 510 with it is described
The quantity of connection terminal 330 is equal, the electrical connection corresponding with connection terminal 330 of the signal terminal 510, the flexible PCB
500 other end is electrically connected with chip, and the chip sends out the signals such as drive signal and is conveyed to connection via flexible PCB 500
Terminal 330.In addition, in other embodiments of the invention, the chip can also be set up directly on flexible PCB, at this time
The chip is electrically connected by conducting wire with the signal terminal.
In the present embodiment, the flatness layer 320 is located on underlay substrate 310, the first side circle of the flatness layer 320
350 are located at the outside of connection terminal 330, and outside here refers to that side far from 310 center of underlay substrate, specifically
Come, refers to Fig. 2, the first side circle 350 of the flatness layer 320 is located at the right side of 330 right end of connection terminal.
In the present embodiment, multiple pixel electrodes 370 (referring to Fig. 4) are formed on the flatness layer 320, it is formed here
The material of the pixel electrode 370 is ITO.
Before array substrate is cut, Fig. 5 is referred to, in Figure 5, LL lines are cutting line.In the present embodiment, institute
At least partly region of first side circle 350 for stating flatness layer 320 is recessed inwardly to form multiple indent concave portions 352, while adjacent two
Recess forms multiple outer recessed portions 353 namely indent concave portion 352 and outer recessed portion outward in region between a indent concave portion 352
353 are alternatively formed.Particularly, Fig. 5 is referred to, in the present embodiment, the indent concave portion 352 and the formation of outer recessed portion 353
Shape be zigzag.Certainly, in other embodiments of the invention, the shape of the indent concave portion 352 and outer recessed portion 353
It does not limit, such as can also be the shapes such as semicircle, oval, rectangular.In the present embodiment, the of the flatness layer 320
350 whole region of side boundary is made of indent concave portion 352 and outer recessed portion 353, however, the present invention is not limited thereto, the present invention's
In other embodiment, it can also be that the first side circle subregion of flatness layer is made of indent concave portion and outer recessed portion.
Thereafter, array substrate is needed to be cut, the shape of the array substrate after cutting refers to Fig. 2, in this implementation
In example, flatness layer 320 and underlay substrate 310 can be cut to along cutting line LL cuttings, in the present embodiment, after cutting, institute
Stating indent concave portion 352, there is also the outer recessed portion 353 is at least partly cut away, to the array base formed after dicing
On plate, indent concave portion 352 is can only see, the outer recessed portion 353 cannot be clear that, in the present embodiment, described outer recessed
Concave portion 353 is at least cut away part, forms planar portions 351, by cutting the planar portions 351 formed positioned at two neighboring
Between recessed portion.In addition, in other embodiments of the invention, the planar portions, which can also be, cuts away whole outer recessed portions
It is formed with the indent concave portion of part.
In the present embodiment, since at least partly region of first side circle 350 of the flatness layer 320 before cutting is by interior
Recessed portion 352 and outer recessed portion 353 are constituted, if thus on first side circle 350 during forming pixel electrode 370
There are kish 340, those kish 340 also can be along the boundary of indent concave portion 352 and outer recessed portion 353 approximation for outside
Linear array, after being cut, the part flatness layer is cut away, and specifically here it is the outer recessed portions 353 by extremely
Part is cut away less, and planar portions 351 are formed after cutting, since planar portions 351 are to cut away the formation of part flatness layer 320, to
There is no kish 340 in the outside of planar portions 351, can also make the kish 340 of previous linearly connected in plane
It is disconnected at portion 351, leads to the line short on flexible PCB 500 or conducting resinl 380 so as to mitigate kish 340
The possibility of interior conducting particles short circuit, so as to prevent high current exception caused by short circuit, array substrate from showing and putting out
It is all not in exception when screen.
In the present embodiment, it is corresponding with the connection terminal 330 due to the signal terminal 510 on flexible PCB 500
It is arranged, in order to reduce the possibility of short circuit to the greatest extent, in the present embodiment, between two connection terminals 330 of arbitrary neighborhood
At least provided with a planar portions 351, since the planar portions 351 are to be cut away the part outer recessed portion 353, to, when
There are one being set between two connection terminals 330 of arbitrary neighborhood when planar portions 351, to two connecting pins of corresponding arbitrary neighborhood
The signal terminal 510 or the conducting particles in conducting resinl 380 of son 330 will not cause short circuit by kish 340, so as to
Prevent short-circuit generation.
In the present embodiment, Fig. 4 is referred to, the connection terminal 330 includes lower metal layer 332 and upper metal layer 333,
In, the lower metal layer 332 is located at the lower section of the flatness layer 320, and the flatness layer 320 corresponds to the lower metal layer 332
Position, which is dug, has first through hole 331, the upper metal layer 333 to be electrically connected with the lower metal layer 332 across first through hole 331,
In the present embodiment, the material identical of the material and pixel electrode 370 of the upper metal layer 333, to pass through same layer metal material
Formed, the upper metal layer 333 and the pixel electrode 370 by with along with light shield formed.
In the present embodiment, the lower metal layer 332 is located on underlay substrate 310, and the lower metal layer 332 is brilliant with film
The grid (not shown) of body pipe is formed together, and the material of the lower metal layer 332 is, for example, Mo/Al/Mo, the array base
Plate further includes gate insulating layer 360, and the gate insulating layer 360 is located at the grid of the lower metal layer 332, thin film transistor (TFT)
Top, the position digging that the gate insulating layer 360 corresponds to the lower metal layer 332 have the second through-hole 361, the upper metal layer
333 pass through first through hole 331, the second through-hole 361 to be electrically connected with the lower metal layer 332.In the present embodiment, the lower metal
Layer 332 is the however, the present invention is not limited thereto on underlay substrate 310, in other embodiments of the invention, the lower gold
Belong to and is additionally provided with buffer insulation layer between layer and the underlay substrate.
In addition, in other embodiments of the invention, the lower metal layer may be located on the gate insulating layer,
Herein, the source electrode of the lower metal layer and thin film transistor (TFT), drain electrode are that same metal material is constituted, and pass through same layer metal material
Material is formed, the source electrode of the lower metal layer and thin film transistor (TFT), drain electrode by with along with light shield formed.
In addition, in other embodiments of the invention, the connection terminal can also be on the flatness layer.
In the present embodiment, from the point of view of overlooking, Fig. 2 is referred to, the array substrate includes viewing area 410 and non-display area
420, the viewing area 410 is for showing, in the present embodiment, the pixel electrode 370 is located at the viewing area 410, part institute
It states flatness layer 320 and is located at the viewing area 410, the non-display area 420 is for cabling, arrangement driving circuit, connection etc.
Function, in the present embodiment, the non-display area 420 are equipped with binding area 421, and the binding area 421 is used for and flexible PCB
500 electrical connections.In the present embodiment, multiple connection terminals 330, the part flatness layer 320, the flatness layer 320
First side circle 350 is located at the binding area 421, and when there are metal residual, kish 340 is also in the binding area
421。
The embodiment of the present invention also provides a kind of display panel, and the display panel includes array substrate and flexible PCB
500, continuing with referring to Fig. 2-Fig. 4, the array substrate includes underlay substrate 310, multiple connection terminals 330,320 and of flatness layer
Multiple pixel electrodes 370；Wherein, multiple connection terminals 330 are located on underlay substrate 310 and close to underlay substrate 310
Boundary is arranged；The flatness layer 320 is located on underlay substrate 310, and the first side circle 350 of the flatness layer 320 is located at connection
At least partly region of first side circle 350 in the outside of terminal 330, the flatness layer 320 is recessed inwardly to form multiple recessed portions,
For by cutting the planar portions 351 formed between two neighboring recessed portion；Multiple pixel electrodes 370 are located on flatness layer 320.
In the present embodiment, the flexible PCB 500 is electrically connected with the array substrate by conducting resinl 380, described
Flexible PCB 500 includes multiple signal terminals 510 close to array substrate side, the quantity of the signal terminal 510 with it is described
The quantity of connection terminal 330 is identical, the electrical connection corresponding with the connection terminal 330 of the signal terminal 510, specifically by leading
Electric glue 380 corresponds to electrical connection.In the present embodiment, the conducting resinl 380 is anisotropic conductive adhesive paste 380 (ACF, anisotropic
Conductive adhesive film), the anisotropic conductive adhesive paste 380 includes conducting particles.
In the present embodiment, at least provided with a planar portions 351 between two connection terminals 330 of arbitrary neighborhood.
In the present embodiment, the connection terminal 330 includes lower metal layer 332 and upper metal layer 333, wherein under described
Metal layer 332 is located at the lower section of the flatness layer 320, and the position that the flatness layer 320 corresponds to the lower metal layer 332 is dug and has the
One through-hole 331, the upper metal layer 333 are electrically connected across first through hole 331 with the lower metal layer 332, in the present embodiment,
The material identical of the material and pixel electrode 370 of the upper metal layer 333, the upper metal layer 333 and the pixel electrode 370
By with along with light shield formed.
In the present embodiment, the lower metal layer 332 is located on underlay substrate 310, and the lower metal layer 332 is brilliant with film
The grid of body pipe is formed together, and the material of the lower metal layer 332 is, for example, Mo/Al/Mo, and the array substrate further includes grid
Insulating layer 360, the gate insulating layer 360 be located at the lower metal layer 332, thin film transistor (TFT) grid top, the grid
The position digging that pole insulating layer 360 corresponds to the lower metal layer 332 has the second through-hole 361, the upper metal layer 333 to pass through first to lead to
Hole 331, the second through-hole 361 are electrically connected with the lower metal layer 332.In the present embodiment, the lower metal layer 332 is direct position
In on underlay substrate 310, however, the present invention is not limited thereto, in other embodiments of the invention, the lower metal layer 332 with it is described
It is additionally provided with buffer insulation layer between underlay substrate 310.
In addition, in other embodiments of the invention, the lower metal layer is located on the gate insulating layer, here,
The source electrode of the lower metal layer and thin film transistor (TFT), drain electrode are same metal material, the lower metal layer and thin film transistor (TFT)
Source electrode, drain electrode by with along with light shield formed.
In addition, in other embodiments of the invention, the connection terminal can also be on the flatness layer.
In the present embodiment, in terms of vertical view, the array substrate includes viewing area 410 and non-display area 420, described aobvious
Show area 410 for showing, in the present embodiment, the pixel electrode 370 is located at the viewing area 410, the part flatness layer 320
Positioned at the viewing area 410, the non-display area 420 is for functions such as cabling, arrangement driving circuit, connections, in this reality
It applies in example, the non-display area 420 is equipped with binding area 421, and the binding area 421 with flexible PCB 500 for being electrically connected.
In the present embodiment, multiple connection terminals 330, the part flatness layer 320, the flatness layer 320 first side circle 350
Positioned at the binding area 421, when storing metal residual, the remaining metal is also in the binding area 421.
In the present embodiment, the display panel further includes colored filter substrate, the array substrate and the colour
Liquid crystal layer is accompanied between filter sheet base plate, the array substrate is bigger than the colored filter substrate area, in the present embodiment
In, the binding area 421 is located at the region that the array substrate exceeds colored filter substrate.
It should be noted that each embodiment in this specification is described in a progressive manner, each embodiment weight
What point illustrated is all the difference with other embodiments, and the same or similar parts between the embodiments can be referred to each other.
For device embodiments, since it is basically similar to the method embodiment, thus description it is fairly simple, related place referring to
The part of embodiment of the method illustrates.
The above disclosure is only the preferred embodiments of the present invention, cannot limit the right model of the present invention with this certainly
It encloses, therefore equivalent changes made in accordance with the claims of the present invention, is still within the scope of the present invention.
Claims (10)
1. a kind of array substrate, which is characterized in that including：
Underlay substrate；
Multiple connection terminals, be located at underlay substrate on and close to underlay substrate boundary be arranged, the connection terminal be used for
Flexible PCB is electrically connected；
Flatness layer is located on underlay substrate, and the first side circle of the flatness layer is located at the outside of connection terminal；
Multiple pixel electrodes are located on flatness layer；
Wherein, the first side circle at least partly region of the flatness layer is recessed inwardly to form multiple recessed portions, two neighboring recessed
For by cutting the planar portions formed between concave portion.
2. array substrate as described in claim 1, which is characterized in that at least provided with one between two connection terminals of arbitrary neighborhood
A planar portions.
3. array substrate as claimed in claim 1 or 2, which is characterized in that the connection terminal includes lower metal layer and upper gold
Belong to layer, the lower metal layer is located at the lower section of the flatness layer, and the position digging that the flatness layer corresponds to the lower metal layer has the
One through-hole, the upper metal layer are electrically connected across first through hole with the lower metal layer, the upper metal layer be used for it is described soft
Property circuit board electrical connection.
4. array substrate as claimed in claim 3, which is characterized in that the array substrate further includes gate insulating layer, described
Lower metal layer is located on the gate insulating layer.
5. array substrate as claimed in claim 3, which is characterized in that the array substrate further includes gate insulating layer, described
Lower metal layer is located at the lower section of the gate insulating layer, and the position digging that the gate insulating layer corresponds to the lower metal layer has second
Through-hole, the upper metal layer pass through first through hole, the second through-hole to be electrically connected with the lower metal layer.
6. array substrate as claimed in claim 1 or 2, which is characterized in that the array substrate includes viewing area and non-display
Area, the pixel electrode are located at the viewing area, and the non-display area is equipped with binding area, the connection terminal, the flatness layer
First side circle be located at the binding area.
7. a kind of display panel, which is characterized in that including：
Array substrate comprising：
Underlay substrate；
Multiple connection terminals are located at the boundary on underlay substrate and close to underlay substrate and are arranged；
Flatness layer is located on underlay substrate, and the first side circle of the flatness layer is located at the outside of the connection terminal, described
First side circle at least partly region is recessed inwardly to form multiple recessed portions, for by cutting formation between two neighboring recessed portion
Planar portions；
Multiple pixel electrodes are located on flatness layer；
Flexible PCB is electrically connected with the array substrate by conducting resinl, and the flexible PCB is close to array substrate one
Side includes multiple signal terminals, signal terminal electrical connection corresponding with the connection terminal.
8. display panel as claimed in claim 7, which is characterized in that at least provided with one between two connection terminals of arbitrary neighborhood
A planar portions.
9. display panel as claimed in claim 7 or 8, which is characterized in that the conducting resinl is anisotropic conductive adhesive paste.
10. display panel as claimed in claim 7 or 8, which is characterized in that the connection terminal includes lower metal layer and upper gold
Belong to layer, the lower metal layer is located at the lower section of the flatness layer, and the position digging that the flatness layer corresponds to the lower metal layer has the
One through-hole, the upper metal layer are electrically connected across first through hole with the lower metal layer, the upper metal layer and the flexible electrical
Road plate is electrically connected by conducting resinl.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810163131.XA CN108389868A (en) | 2018-02-26 | 2018-02-26 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810163131.XA CN108389868A (en) | 2018-02-26 | 2018-02-26 | Array substrate and display panel |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810163131.XA Pending CN108389868A (en) | 2018-02-26 | 2018-02-26 | Array substrate and display panel |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108957880A (en) * | 2018-08-01 | 2018-12-07 | 京东方科技集团股份有限公司 | Array substrate, display panel and preparation method thereof |
| CN109560086A (en) * | 2018-12-13 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| CN109637994A (en) * | 2018-11-26 | 2019-04-16 | 武汉华星光电半导体显示技术有限公司 | A kind of flexible display panels and flexible display apparatus |
| CN109884830A (en) * | 2019-02-28 | 2019-06-14 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device, mask plate |
| WO2020113681A1 (en) * | 2018-12-05 | 2020-06-11 | 惠科股份有限公司 | Array substrate fabrication method and array substrate and display panel |
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| WO2021159293A1 (en) * | 2020-02-12 | 2021-08-19 | 京东方科技集团股份有限公司 | Display panel, display device, and manufacturing method of display panel |
| CN113341622A (en) * | 2021-05-31 | 2021-09-03 | 长沙惠科光电有限公司 | Array substrate, processing technology of array substrate and display panel |
| WO2023142698A1 (en) * | 2022-01-27 | 2023-08-03 | 绵阳惠科光电科技有限公司 | Array substrate, preparation method therefor, display panel, and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1558272A (en) * | 2004-02-03 | 2004-12-29 | 友达光电股份有限公司 | Active element array baseplate and liquid crystal display panel possessing said baseplate |
| KR20050070975A (en) * | 2003-12-31 | 2005-07-07 | 엘지.필립스 엘시디 주식회사 | Array substrate for liquid crystal display device and fabrication method of the same |
| CN101231435A (en) * | 2007-01-24 | 2008-07-30 | 三星电子株式会社 | Thin film transistor array panel |
| CN104733471A (en) * | 2013-12-23 | 2015-06-24 | 昆山国显光电有限公司 | Array substrate of organic light-emitting displaying device and preparing method thereof |
| CN104952882A (en) * | 2015-03-26 | 2015-09-30 | 友达光电股份有限公司 | Active element array substrate |
| CN106298811A (en) * | 2016-09-28 | 2017-01-04 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN106449666A (en) * | 2016-12-02 | 2017-02-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
-
2018
- 2018-02-26 CN CN201810163131.XA patent/CN108389868A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050070975A (en) * | 2003-12-31 | 2005-07-07 | 엘지.필립스 엘시디 주식회사 | Array substrate for liquid crystal display device and fabrication method of the same |
| CN1558272A (en) * | 2004-02-03 | 2004-12-29 | 友达光电股份有限公司 | Active element array baseplate and liquid crystal display panel possessing said baseplate |
| CN101231435A (en) * | 2007-01-24 | 2008-07-30 | 三星电子株式会社 | Thin film transistor array panel |
| CN104733471A (en) * | 2013-12-23 | 2015-06-24 | 昆山国显光电有限公司 | Array substrate of organic light-emitting displaying device and preparing method thereof |
| CN104952882A (en) * | 2015-03-26 | 2015-09-30 | 友达光电股份有限公司 | Active element array substrate |
| CN106298811A (en) * | 2016-09-28 | 2017-01-04 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN106449666A (en) * | 2016-12-02 | 2017-02-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108957880B (en) * | 2018-08-01 | 2021-11-16 | 京东方科技集团股份有限公司 | Array substrate, display panel and manufacturing method thereof |
| US11699707B2 (en) | 2018-08-01 | 2023-07-11 | Boe Technology Group Co., Ltd. | Array substrate, display panel and manufacturing method thereof |
| CN108957880A (en) * | 2018-08-01 | 2018-12-07 | 京东方科技集团股份有限公司 | Array substrate, display panel and preparation method thereof |
| CN109637994A (en) * | 2018-11-26 | 2019-04-16 | 武汉华星光电半导体显示技术有限公司 | A kind of flexible display panels and flexible display apparatus |
| WO2020107749A1 (en) * | 2018-11-26 | 2020-06-04 | 武汉华星光电半导体显示技术有限公司 | Flexible display panel and flexible display device |
| WO2020113681A1 (en) * | 2018-12-05 | 2020-06-11 | 惠科股份有限公司 | Array substrate fabrication method and array substrate and display panel |
| US11289516B2 (en) | 2018-12-05 | 2022-03-29 | HKC Corporation Limited | Array substrate fabrication method, array substrate, and display panel |
| CN109560086A (en) * | 2018-12-13 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| WO2020124743A1 (en) * | 2018-12-18 | 2020-06-25 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method therefor |
| CN109884830A (en) * | 2019-02-28 | 2019-06-14 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device, mask plate |
| WO2021159293A1 (en) * | 2020-02-12 | 2021-08-19 | 京东方科技集团股份有限公司 | Display panel, display device, and manufacturing method of display panel |
| CN113341622A (en) * | 2021-05-31 | 2021-09-03 | 长沙惠科光电有限公司 | Array substrate, processing technology of array substrate and display panel |
| WO2023142698A1 (en) * | 2022-01-27 | 2023-08-03 | 绵阳惠科光电科技有限公司 | Array substrate, preparation method therefor, display panel, and display device |
| US11764230B2 (en) | 2022-01-27 | 2023-09-19 | Mianyang HKC Optoelectronics Technology Co., Ltd. | Array substrate, display panel, and display device |
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