TWI549253B - Esd protection circuit - Google Patents

Esd protection circuit Download PDF

Info

Publication number
TWI549253B
TWI549253B TW101146035A TW101146035A TWI549253B TW I549253 B TWI549253 B TW I549253B TW 101146035 A TW101146035 A TW 101146035A TW 101146035 A TW101146035 A TW 101146035A TW I549253 B TWI549253 B TW I549253B
Authority
TW
Taiwan
Prior art keywords
well
gate
region
drift
pole type
Prior art date
Application number
TW101146035A
Other languages
Chinese (zh)
Other versions
TW201338125A (en
Inventor
賴大偉
李明
柯壯謀
普拉克 拉吉 弗爾瑪
Original Assignee
格羅方德半導體私人有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 格羅方德半導體私人有限公司 filed Critical 格羅方德半導體私人有限公司
Publication of TW201338125A publication Critical patent/TW201338125A/en
Application granted granted Critical
Publication of TWI549253B publication Critical patent/TWI549253B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

靜電放電防護電路 Electrostatic discharge protection circuit

一般而言，本發明係有關於一種精密積體電路，尤指一種用以形成矽貫孔的結構及製造方法。 In general, the present invention relates to a precision integrated circuit, and more particularly to a structure and a manufacturing method for forming a through hole.

傳統n型橫向擴散金屬氧化物半導體(n-type lateral diffused metal oxide semiconductor；nLDMOS)存在一些固有缺點，例如，「驟回(snapback)柯克(kirk)效應或基極擴展」負面地影響或降低其ESD性能。該些缺點導致nLDMOS或靜電放電(Electrostatic Discharge；ESD)裝置不均勻導通。 The conventional n-type lateral diffused metal oxide semiconductor (nLDMOS) has some inherent disadvantages, for example, "snapback Kirk effect or base expansion" negatively affects or reduces Its ESD performance. These shortcomings lead to uneven conduction of nLDMOS or Electrostatic Discharge (ESD) devices.

本揭露旨在降低或防止驟回(snapback)或基極擴展現象，且提供具有改進ESD性能的電晶體。 The present disclosure is directed to reducing or preventing snapback or base expansion phenomena and providing a transistor with improved ESD performance.

本發明實施例通常涉及半導體裝置。在一實施例中，提供一種包括基板的裝置。該基板定義為具有靜電放電(Electrostatic Discharge；ESD)保護電路的裝置區，該ESD保護電路具有電晶體。該電晶體包括具有第一側及第二側的閘極。在鄰近該閘極的該第一側之該裝置區中設置第一擴散區，以及在離開該閘極的該第二側之該裝 置區中設置第二擴散區。該第一及第二擴散區包括第一極型摻雜物。在該閘極及該第二擴散區之間設置漂移隔離區。第一裝置井(well)包圍該裝置區，且在該第一裝置井內設置第二裝置井。在該第二擴散區下方及該第一裝置井內設置具有該第一極型摻雜物的汲極井。 Embodiments of the invention generally relate to semiconductor devices. In an embodiment, an apparatus comprising a substrate is provided. The substrate is defined as a device region having an Electrostatic Discharge (ESD) protection circuit having a transistor. The transistor includes a gate having a first side and a second side. Providing a first diffusion region in the device region adjacent to the first side of the gate, and the device on the second side exiting the gate A second diffusion zone is set in the set area. The first and second diffusion regions comprise a first pole type dopant. A drift isolation region is disposed between the gate and the second diffusion region. A first device well surrounds the device region and a second device well is disposed within the first device well. A bungee well having the first pole type dopant is disposed under the second diffusion region and in the first device well.

在另一實施例中，本發明揭露一種包括基板的裝置，該基板具有位於裝置區中的第一裝置井及第二裝置井。該第二裝置井設置於該第一裝置井內。在該裝置區中設置電晶體。該電晶體包括具有第一側及第二側的閘極。鄰近該閘極的該第一側設置第一擴散區，以及離開該閘極的該第二側設置第二擴散區。在該閘極及該第二擴散區之間設置漂移隔離區。在該第二擴散區下方及該第一裝置井內設置汲極井。 In another embodiment, the invention discloses a device comprising a substrate having a first device well and a second device well located in the device region. The second device well is disposed within the first device well. A transistor is placed in the device area. The transistor includes a gate having a first side and a second side. A first diffusion region is disposed on the first side adjacent to the gate, and a second diffusion region is disposed on the second side away from the gate. A drift isolation region is disposed between the gate and the second diffusion region. A bungee well is disposed below the second diffusion zone and within the first device well.

藉由參照以下的說明及附圖，本文所述實施例的上述及其他優點以及特徵將變得更加清楚。而且，應當理解，本文所述各種實施例的特徵並不相互排斥，而是可存在於各種組合及排列。 The above and other advantages and features of the embodiments described herein will become more apparent from the description and appended claims. Moreover, it should be understood that the features of the various embodiments described herein are not mutually exclusive, but may be in various combinations and arrangements.

100a、100b、100c、100d‧‧‧裝置 100a, 100b, 100c, 100d‧‧‧ devices

105‧‧‧基板 105‧‧‧Substrate

110‧‧‧裝置區 110‧‧‧Device area

115、215‧‧‧ESD保護電路 115, 215‧‧‧ESD protection circuit

115a‧‧‧第一橫向擴散電晶體 115a‧‧‧First lateral diffusion transistor

115b‧‧‧第二橫向擴散電晶體 115b‧‧‧Second lateral diffusion transistor

120‧‧‧閘極 120‧‧‧ gate

124‧‧‧閘極介電層 124‧‧‧ gate dielectric layer

126‧‧‧閘極電極 126‧‧‧gate electrode

130‧‧‧第一源極/汲極區 130‧‧‧First source/bungee area

134‧‧‧第一電極端 134‧‧‧first electrode end

140‧‧‧第二源極/汲極區 140‧‧‧Second source/drain region

144‧‧‧第二電極端 144‧‧‧second electrode end

160‧‧‧第一井 160‧‧‧First Well

162‧‧‧第一井接觸 162‧‧‧First well contact

165‧‧‧第二井 165‧‧‧ second well

167‧‧‧第二井接觸 167‧‧‧Second well contact

170‧‧‧第三井 170‧‧‧ third well

175‧‧‧第四井 175‧‧‧fourth well

180‧‧‧第五井 180‧‧‧ fifth well

190、194‧‧‧隔離區 190, 194‧‧ ‧ quarantine area

192‧‧‧漂移隔離區 192‧‧‧ Drift isolation zone

200a、200b、200c、200d‧‧‧裝置 200a, 200b, 200c, 200d‧‧‧ devices

於圖式中，類似的圖式標記通常代表不同視圖中之相同元件。另外，圖式不一定按比例繪製，而是重點說明本發明的原理。在以下的說明中，參照圖式描述本發明之各種實施例，其中：第1a圖至第1d圖係顯示裝置之不同實施例的剖視圖；以及 第2a圖至第2d圖係顯示裝置之其他不同實施例的剖視圖。 In the drawings, similar drawing marks generally represent the same elements in different views. In addition, the drawings are not necessarily to scale, In the following description, various embodiments of the invention are described with reference to the drawings, wherein: FIGS. 1a through 1d are cross-sectional views of different embodiments of display devices; Figures 2a through 2d are cross-sectional views of other different embodiments of the display device.

本發明實施例通常涉及半導體裝置。該些裝置設有靜電放電(Electrostatic Discharge；ESD)電路。例如，該些ESD電路可用於高電壓應用或裝置中。例如，可在ESD事件中啟動ESD電路，以釋放ESD電流。例如，該些裝置可為任意類型的半導體裝置如積體電路(IC)。例如，此類裝置可包含於獨立的裝置或積體電路中如微控制器或系統單晶片(System On Chip；SOC)。例如，該些裝置或積體電路可包含於如揚聲器、電腦、手機及個人數位助理(Personal Digitial Assistant；PDA)等電子產品中或與該些電子產品結合使用。 Embodiments of the invention generally relate to semiconductor devices. These devices are provided with an Electrostatic Discharge (ESD) circuit. For example, the ESD circuits can be used in high voltage applications or devices. For example, an ESD circuit can be initiated in an ESD event to release the ESD current. For example, the devices can be any type of semiconductor device such as an integrated circuit (IC). For example, such devices can be included in a stand-alone device or integrated circuit such as a microcontroller or a system on chip (SOC). For example, the devices or integrated circuits may be included in or used with electronic products such as speakers, computers, cell phones, and Personal Digitial Assistants (PDAs).

第1a圖係顯示裝置100a之一實施例的剖視圖。如圖所示，設置基板105。該基板為半導體基板如矽基板。在一實施例中，該基板可為p型摻雜基板。例如，該p型摻雜基板為p型輕摻雜基板。亦可使用其他類型的半導體基板，包括摻雜有其他類型摻雜物或濃度或不摻雜的半導體基板。例如，該基板可為矽鍺、鍺、砷化鎵或絕緣體上晶體(Crystal-On-Insulator；COI)如絕緣體上矽(Silicon-On-Insulator；SOI)。該基板可為摻雜基板。 Figure 1a is a cross-sectional view of one embodiment of display device 100a. As shown in the figure, the substrate 105 is provided. The substrate is a semiconductor substrate such as a germanium substrate. In an embodiment, the substrate can be a p-type doped substrate. For example, the p-type doped substrate is a p-type lightly doped substrate. Other types of semiconductor substrates can also be used, including semiconductor substrates doped with other types of dopants or with or without doping. For example, the substrate may be germanium, germanium, gallium arsenide or a crystal-on-insulator (COI) such as a Silicon-On-Insulator (SOI). The substrate can be a doped substrate.

該裝置可包括具有不同摻雜濃度的摻雜區或井。例如，該裝置可包括重摻雜區、中等摻雜區及輕摻雜區。該些摻雜區可由x-、x及x+表示，其中，x表示摻 雜的極性如p表示p型，或者n表示n型，以及：x-=輕摻雜；x=中等摻雜；以及x+=重摻雜。 The device can include doped regions or wells having different doping concentrations. For example, the device can include a heavily doped region, a moderately doped region, and a lightly doped region. The doped regions may be represented by x-, x, and x+, wherein x represents doping The polarity of the impurity such as p represents p-type, or n represents n-type, and: x-= lightly doped; x = moderately doped; and x+ = heavily doped.

輕摻雜區可具有約低於5E13/cm3的摻雜濃度。例如，輕摻雜區可具有約為1E11/cm3至5E13/cm3的摻雜濃度。中等摻雜區可具有約為5E13/cm3至5E15/cm3的摻雜濃度。重摻雜區可具有約大於5E15/cm3的摻雜濃度。例如，重摻雜區可具有約為5E15/cm3至9E15/cm3的摻雜濃度。亦可使用具有其他濃度之不同類型的摻雜區。p型摻雜物可包括硼(B)、鋁(Al)、銦(In)或其組合，而n型摻雜物可包括磷(P)、砷(As)、銻(Sb)或其組合。 The lightly doped region can have a doping concentration of less than about 5E13/cm 3 . For example, the lightly doped region may have a doping concentration of about 1E11/cm 3 to 5E13/cm 3 . The medium doped region may have a doping concentration of about 5E13/cm 3 to 5E15/cm 3 . The heavily doped region can have a doping concentration greater than about 5E15/cm 3 . For example, the heavily doped region can have a doping concentration of about 5E15/cm 3 to 9E15/cm 3 . Different types of doped regions with other concentrations can also be used. The p-type dopant may include boron (B), aluminum (Al), indium (In), or a combination thereof, and the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. .

如圖所示，該裝置包括定義於該基板上的裝置區110。可設置裝置隔離區190用以將該裝置區與該基板上的其他裝置區隔離或分離。在一實施例中，該裝置隔離區圍繞該裝置區。例如，該隔離區為淺溝槽隔離(shallow trench isolation；STI)區。亦可使用其他類型的隔離區。例如，該隔離區可為深溝槽隔離(deep trench isolation；DTI)區。例如，對於淺溝槽隔離區，該隔離區延伸至約4000埃(Å)的深度。亦可設置延伸至其他深度的隔離區，例如，對於深溝槽隔離區，延伸至0.5至10微米(μm)的深度。在一實施例中，該隔離區的寬度約為0.3μm。亦可使用具有不同深度及寬度的隔離區。例如，隔離區的尺寸可取決於隔離要求。 As shown, the device includes a device region 110 defined on the substrate. A device isolation region 190 can be provided to isolate or separate the device region from other device regions on the substrate. In an embodiment, the device isolation region surrounds the device region. For example, the isolation region is a shallow trench isolation (STI) region. Other types of isolation zones can also be used. For example, the isolation region can be a deep trench isolation (DTI) region. For example, for shallow trench isolation regions, the isolation regions extend to a depth of about 4000 angstroms (Å). It is also possible to provide an isolation region that extends to other depths, for example, to a deep trench isolation region that extends to a depth of 0.5 to 10 micrometers (μm). In one embodiment, the isolation region has a width of about 0.3 [mu]m. Isolation areas with different depths and widths can also be used. For example, the size of the isolation zone may depend on the isolation requirements.

該裝置區包括ESD保護電路115。在一實施例中，該ESD保護電路為橫向擴散(lateral diffused；LD)電晶體。例如，該ESD保護電路為橫向擴散金屬氧化物半導體(LDMOS)電晶體。 The device area includes an ESD protection circuit 115. In an embodiment, the ESD protection circuit is a lateral diffused (LD) transistor. For example, the ESD protection circuit is a laterally diffused metal oxide semiconductor (LDMOS) transistor.

在一實施例中，在該裝置區之該基板中設置第一摻雜井160。如圖所示，該第一摻雜井包圍該全部裝置區。例如，該第一摻雜井作為第一裝置井，該第一裝置井設於大約自該裝置隔離區的內側邊緣起之該基板中。該第一摻雜井亦可延伸自該隔離區的內側邊緣及外側邊緣之間該隔離區的底部。在一實施例中，該第一井作為隔離井。例如，該第一井將該ESD保護電路與該基板隔離。為了作為隔離井，該第一井應當足夠深。 In one embodiment, a first doping well 160 is disposed in the substrate of the device region. As shown, the first doping well surrounds the entire device area. For example, the first doped well is the first device well and the first device well is disposed in the substrate from approximately the inner edge of the device isolation region. The first doping well may also extend from the bottom of the isolation region between the inner edge and the outer edge of the isolation region. In an embodiment, the first well acts as an isolation well. For example, the first well isolates the ESD protection circuit from the substrate. In order to be an isolated well, the first well should be deep enough.

該第一井包括第一極型摻雜物。在一實施例中，該第一井以第一極型摻雜物輕摻雜。例如，該第一井的摻雜濃度可約為1E11/cm3至5E13/cm3。亦可設置具有其他摻雜濃度的第一井。在一實施例中，該第一極型為n型。例如，該第一井可為針對n型裝置的n-井。該第一極型亦可為p型。例如，可使用針對p型裝置的p-井。 The first well includes a first pole type dopant. In an embodiment, the first well is lightly doped with a first pole type dopant. For example, the first well may have a doping concentration of about 1E11/cm 3 to 5E13/cm 3 . A first well having other doping concentrations can also be provided. In an embodiment, the first pole type is an n-type. For example, the first well can be an n-well for an n-type device. The first pole type can also be p-type. For example, a p-well for a p-type device can be used.

在該裝置區中的該基板表面上設置該電晶體的閘極120，該閘極包括設於閘極介電層124上方的閘極電極126，該閘極電極可為多晶矽，亦可使用其他材料。該閘極介電層可為氧化矽，亦可使用其他閘極介電材料。在一實施例中，該閘極類似核心裝置所使用的閘極。亦可使用其他配置的閘極。 A gate 120 of the transistor is disposed on the surface of the substrate in the device region, and the gate includes a gate electrode 126 disposed above the gate dielectric layer 124. The gate electrode may be polysilicon or may use other material. The gate dielectric layer can be tantalum oxide, and other gate dielectric materials can also be used. In one embodiment, the gate is similar to the gate used by the core device. Other configurations of gates can also be used.

該閘極可為閘極導體，係構成多個電晶體的閘極。例如，該閘極導體可橫跨被隔離區分離的多個裝置區。該多個電晶體具有由該閘極導體構成的共同閘極。亦可使用其他配置的閘極導體。 The gate may be a gate conductor and constitute a gate of a plurality of transistors. For example, the gate conductor can span a plurality of device regions separated by an isolation region. The plurality of transistors have a common gate formed by the gate conductors. Other configurations of gate conductors can also be used.

該閘極設置於第一及第二源極/汲極(S/D)區130、140之間。該些源/汲極為設置於該基板中的第一極型摻雜區。例如，該些源/汲極為第一極型重摻雜區。例如，該些源/汲極可具有約0.1至0.4μm的深度。亦可使用其他深度。該些源/汲極可類似該裝置之其他電晶體的源/汲極。在一實施例中，該第一源極/汲極為該電晶體的源極區，該第二源極/汲極為該電晶體的汲極區。 The gate is disposed between the first and second source/drain (S/D) regions 130, 140. The sources/germans are disposed substantially in the first pole doped region in the substrate. For example, the sources/汲 are extremely first heavily doped regions. For example, the sources/drains may have a depth of about 0.1 to 0.4 [mu]m. Other depths can also be used. The source/drain electrodes can be similar to the source/drain of other transistors of the device. In one embodiment, the first source/german is substantially the source region of the transistor, and the second source/german is substantially the drain region of the transistor.

該第一源極/汲極鄰近該閘極的第一側。在一實施例中，該閘極重疊(overlap)該第一源極/汲極。例如，該閘極的該第一側重疊該第一源極/汲極。重疊量應當足以使該第一源極/汲極與該閘極下方的該電晶體的通道連接。例如，重疊量約為0.1至0.5μm。亦可以其他數量重疊該第一源極/汲極。在一實施例中，該閘極重疊該第一源極/汲極的輕摻雜區。該第一源極/汲極亦可具有其他配置。該第二源極/汲極離開該閘極的第二側。例如，其位移可為漂移距離。 The first source/drain is adjacent to the first side of the gate. In an embodiment, the gate overlaps the first source/drain. For example, the first side of the gate overlaps the first source/drain. The amount of overlap should be sufficient to connect the first source/drain to the channel of the transistor below the gate. For example, the amount of overlap is about 0.1 to 0.5 μm. The first source/drain may also be overlapped by other numbers. In one embodiment, the gate overlaps the lightly doped region of the first source/drain. The first source/drain may also have other configurations. The second source/drain exits the second side of the gate. For example, its displacement can be a drift distance.

在一實施例中，在該閘極與該第二源極/汲極之間設置漂移隔離區192。例如，該漂移隔離區為淺溝槽隔離。亦可使用其他類型的漂移隔離區。如圖所示，該閘極重疊該漂移隔離區。該漂移隔離區可用於增加有效的 漂移距離。例如，可將該漂移距離增加至與該漂移隔離區的分布(profile)相等。 In an embodiment, a drift isolation region 192 is disposed between the gate and the second source/drain. For example, the drift isolation region is shallow trench isolation. Other types of drift isolation regions can also be used. As shown, the gate overlaps the drift isolation region. The drift isolation region can be used to increase effective Drift distance. For example, the drift distance can be increased to be equal to the profile of the drift isolation region.

該閘極的側壁可設有介電間隔件(dielectric spacer)(未圖示)。例如，該些介電間隔件可為氧化矽間隔件。亦可使用其他介電材料如氮化矽或介電材料或層的組合。例如，該些間隔件可為複合間隔件。該些間隔件可幫助形成該輕摻雜區及源/汲極。例如，在形成間隔件之前形成該輕摻雜區，而在形成間隔件後形成該第一源極/汲極。亦可使用其他配置的間隔件。例如，該間隔件可為單個間隔件。在一些情況下，該電晶體亦可包括環狀(halo)區。該環狀區為第二極型摻雜區，鄰接該閘極下方之該輕摻雜區及第一源極/汲極。 The sidewall of the gate may be provided with a dielectric spacer (not shown). For example, the dielectric spacers can be yttria spacers. Other dielectric materials such as tantalum nitride or dielectric materials or combinations of layers may also be used. For example, the spacers can be composite spacers. The spacers can help form the lightly doped region and the source/drain. For example, the lightly doped region is formed prior to forming the spacer, and the first source/drain is formed after the spacer is formed. Other configurations of spacers are also available. For example, the spacer can be a single spacer. In some cases, the transistor may also include a halo region. The annular region is a second pole doped region adjacent to the lightly doped region under the gate and the first source/drain.

在一些實施例中，在該些電晶體上方形成介電蝕刻停止層(未圖示)。例如，該蝕刻停止層為氮化矽蝕刻停止層。亦可使用其他類型的蝕刻停止層。該蝕刻停止層應當具有可自上方的介電層選擇性移除的材料。該蝕刻停止層幫助形成接觸該電晶體的區域(例如，該閘極電極及摻雜區)的接觸塞(contact plug)。在一些實施例中，該蝕刻停止層亦可作為應力層，以施加應力於該閘極下方之該電晶體的通道上，從而提升性能。 In some embodiments, a dielectric etch stop layer (not shown) is formed over the plurality of transistors. For example, the etch stop layer is a tantalum nitride etch stop layer. Other types of etch stop layers can also be used. The etch stop layer should have a material that is selectively removable from the upper dielectric layer. The etch stop layer helps form a contact plug that contacts a region of the transistor (eg, the gate electrode and the doped region). In some embodiments, the etch stop layer can also act as a stressor layer to apply stress to the via of the transistor below the gate to improve performance.

在該基板中設置第二井165。該第二井可設置於該裝置區中。例如，該第二井設置於該第一井內。該第二井作為該ESD裝置的體井(body well)。該第二裝置井包括針對第一極型裝置的第二極型摻雜物。例如，該第二 裝置井包括針對n型裝置的p型摻雜物或針對p型裝置的n型摻雜物。摻雜濃度可取決於該裝置的電壓要求。該第二裝置井可以第二極型摻雜物輕摻雜(x-)或中等摻雜(x)。例如，該第二井可為針對n型裝置的p型井。該第二裝置井亦可具有如適於高電壓應用的其他摻雜濃度。 A second well 165 is disposed in the substrate. The second well can be disposed in the device area. For example, the second well is disposed within the first well. The second well acts as a body well for the ESD device. The second device well includes a second pole type dopant for the first pole type device. For example, the second The device well includes a p-type dopant for the n-type device or an n-type dopant for the p-type device. The doping concentration can depend on the voltage requirements of the device. The second device well may be lightly doped (x-) or moderately doped (x) with the second pole type dopant. For example, the second well can be a p-type well for an n-type device. The second device well can also have other doping concentrations as suitable for high voltage applications.

該體井至少包圍該第一源極/汲極以及一部分該閘極。如圖所示，該體井包圍該第一及第二源極/汲極。該第二井亦可具有其他配置。該第二井的深度淺於該第一井。 The body well surrounds at least the first source/drain and a portion of the gate. As shown, the body well surrounds the first and second source/drain electrodes. The second well can also have other configurations. The second well has a shallower depth than the first well.

在一實施例中，該第一及第二井設有第一及第二井接觸162、167，以偏置該些井。該些井接觸為重摻雜區，類似該些源/汲極。例如，井接觸的深度淺於該裝置隔離區的深度，且該些井接觸分別與該些井連接。該些井接觸的摻雜濃度可約為5E15/cm3至9E15/cm3。該些井接觸具有與該些井相同的極型。例如，該第一井接觸為第一極型摻雜區，且該第二井接觸為第二極型摻雜區。 In one embodiment, the first and second wells are provided with first and second well contacts 162, 167 to bias the wells. The well contacts are heavily doped regions, similar to the source/drain electrodes. For example, the depth of the well contact is shallower than the depth of the isolation zone of the device, and the well contacts are respectively connected to the wells. The wells may have a doping concentration of about 5E15/cm 3 to 9E15/cm 3 . The well contacts have the same pole type as the wells. For example, the first well contact is a first pole doped region and the second well contact is a second pole doped region.

在一實施例中，可設置隔離區194以分離該些接觸區。該些隔離區可為淺溝槽隔離區。例如，該些隔離區可類似該些裝置隔離區。亦可使用其他類型或配置的隔離區。 In an embodiment, isolation regions 194 may be provided to separate the contact regions. The isolation regions can be shallow trench isolation regions. For example, the isolation regions can be similar to the device isolation regions. Other types or configurations of quarantines can also be used.

可在該閘極電極以及各接觸區上形成金屬矽化物接觸(未圖示)。例如，可在該些源/汲極、井接觸以及閘極電極上方設置金屬矽化物接觸。例如，該些矽化物接觸可為鎳基接觸，亦可使用其他類型的金屬矽化物接 觸。例如，該些矽化物接觸可為矽化鈷(CoSi)接觸。該些矽化物接觸的厚度可約為100至500埃，該些矽化物接觸亦可具有其他厚度，該些矽化物接觸可用於降低接觸電阻並促進與後端製程的金屬互連的接觸。 A metal halide contact (not shown) may be formed on the gate electrode and each contact region. For example, metal telluride contacts can be placed over the source/drain, well contacts, and gate electrodes. For example, the telluride contacts may be nickel-based contacts, and other types of metal telluride may also be used. touch. For example, the telluride contacts can be cobalt antimonide (CoSi) contacts. The telluride contacts may have a thickness of from about 100 to about 500 angstroms, and the telluride contacts may have other thicknesses that may be used to reduce contact resistance and facilitate contact with metal interconnects in the back end process.

在一實施例中，設置第三井170。該第三井設置於該第二井內的該基板中。例如，該第三井的深度淺於該第二井的深度。該第三井作為漂移井。在一實施例中，該第三井包圍該第二源極/汲極且延伸於該閘極下方。該閘極重疊該第三井或漂移井，以形成閘極重疊區Ogate。若設有內部隔離區，則該閘極重疊區Ogate位於該閘極下方的該第三井邊緣(亦即該第三井的內側邊緣)與該閘極下方的該漂移隔離區邊緣(亦即該漂移隔離區的內側邊緣)之間。在一實施例中，Ogate約為0.2至2μm。Ogate亦可具有其他值。例如，其寬度可取決於設計要求。 In an embodiment, a third well 170 is provided. The third well is disposed in the substrate within the second well. For example, the depth of the third well is shallower than the depth of the second well. The third well acts as a drift well. In an embodiment, the third well surrounds the second source/drain and extends below the gate. The gate overlaps the third well or the drift well to form a gate overlap region O gate . If an internal isolation region is provided, the gate overlap region O gate is located at the edge of the third well below the gate (ie, the inner edge of the third well) and the edge of the drift isolation region below the gate (also That is, between the inner edges of the drift isolation region). In one embodiment, the O gate is about 0.2 to 2 μm. O gate can also have other values. For example, its width can depend on design requirements.

在一實施例中，該第三井的深度或底部位於該些隔離區下方。例如，該漂移井自該裝置隔離區的底部延伸至該閘極下方。該第三井的深度可約為0.1至5μm，亦可具有其他深度，例如，其深度可取決於該裝置的設計電壓。位於該第一源極/汲極與第三井之間的該閘極下方之該基板形成該電晶體的通道。有效漂移距離始於該第二源極/汲極，繞過該漂移隔離區且到達該閘極下方的該通道。 In an embodiment, the depth or bottom of the third well is below the isolation regions. For example, the drift well extends from the bottom of the device isolation region to below the gate. The third well may have a depth of about 0.1 to 5 [mu]m and may have other depths, for example, the depth may depend on the design voltage of the device. The substrate below the gate between the first source/drain and the third well forms a channel for the transistor. The effective drift distance begins at the second source/drain, bypassing the drift isolation region and reaching the channel below the gate.

該漂移井包括第一極型摻雜物。在一實施例中，該漂移井的摻雜濃度低於該汲極的摻雜濃度。在一 實施例中，該漂移井可以第一極型摻雜物輕摻雜(x-)或中等摻雜(x)。例如，該漂移井的摻雜濃度約為1E12至IE14/cm2，亦可具有其他摻雜濃度。例如，其摻雜濃度可取決於該裝置的最大或崩潰電壓(breakdown voltage)要求。 The drift well includes a first pole type dopant. In an embodiment, the drift well has a doping concentration that is lower than a doping concentration of the drain. In an embodiment, the drift well may be lightly doped (x-) or moderately doped (x) with the first pole type dopant. For example, the drift well has a doping concentration of about 1E12 to IE14/cm 2 and may have other doping concentrations. For example, its doping concentration may depend on the maximum or breakdown voltage requirements of the device.

在一實施例中，該第二井、第一源極/汲極及閘極共同耦接該ESD裝置的第一電極端134。該第二源極/汲極耦接該ESD裝置的第二電極端144。例如，該第一電極端為源極端，且該第二電極端為汲極端。例如，該源極端耦接接地，而該汲極端耦接VDD或I/O(輸入/輸出)焊墊。該ESD裝置亦可具有其他配置的端連接。 In one embodiment, the second well, the first source/drain and the gate are coupled to the first electrode end 134 of the ESD device. The second source/drain is coupled to the second electrode end 144 of the ESD device. For example, the first electrode end is a source terminal and the second electrode end is a 汲 terminal. For example, the source terminal is coupled to ground and the drain is coupled to a VDD or I/O (input/output) pad. The ESD device can also have other configurations of end connections.

依據一實施例，設置第四井175。例如，該第四井作為第二源極/汲極井或汲極井。該汲極井設置於該汲極下方的該基板中。例如，該第四井的寬度可窄於、等於或大於該汲極的寬度，係取決於工作電壓。該汲極井的深度在該漂移隔離區的底部及體井之間，該汲極井亦可具有其他深度。 According to an embodiment, a fourth well 175 is provided. For example, the fourth well acts as a second source/dump or bungee well. The bungee well is disposed in the substrate below the drain. For example, the width of the fourth well may be narrower than, equal to, or greater than the width of the drain, depending on the operating voltage. The depth of the bungee well is between the bottom of the drift isolation zone and the well, and the bungee well can have other depths.

該汲極井包括第一極型摻雜物。在一實施例中，該汲極井的摻雜濃度介於該第二源極/汲極及漂移井之間。在一實施例中，該汲極井可以第一極型摻雜物中等摻雜(x)。其亦可具有其他摻雜濃度。 The bungee well includes a first pole type dopant. In one embodiment, the doping concentration of the bungee well is between the second source/drain and the drift well. In an embodiment, the bungee well may be doped (x) in the first pole type dopant. It can also have other doping concentrations.

可以發現，藉由在該汲極下方設置汲極井，在垂直方向形成較低電阻路徑。如此，引導電流沿垂直方向而非水平方向流動。因此，在早期階段減輕或抑制基極擴展。此結果導致該ESD裝置具有改進的更均勻導通。 It can be found that by providing a bungee well below the bungee, a lower resistance path is formed in the vertical direction. As such, the pilot current flows in a vertical direction rather than a horizontal direction. Therefore, the base extension is mitigated or suppressed at an early stage. This result results in an improved more uniform conduction of the ESD device.

第1b圖係顯示裝置100b之另一實施例的剖視圖。裝置100b類似第1a圖的裝置。共同的元件將不再加以描述或詳細描述。如圖所示，基板105具有由裝置隔離區190隔離的裝置區。該裝置區包括橫向擴散電晶體115，係作為ESD保護電路。該裝置區包括第一、第二、第三及第四摻雜井160、165、170、175。該第一井可作為隔離井，該第二井作為體井，該第三井作為漂移井，且該第四井作為汲極井。可設置井接觸區162、167，可設置隔離區，例如，漂移隔離區192及井接觸隔離區194，可在該閘極電極、源/汲極以及井接觸區上設置金屬矽化物接觸。 Figure 1b is a cross-sectional view of another embodiment of display device 100b. Device 100b is similar to the device of Figure 1a. Common components will not be described or described in detail. As shown, the substrate 105 has a device region that is isolated by the device isolation region 190. The device region includes a laterally diffusing transistor 115 as an ESD protection circuit. The device region includes first, second, third, and fourth doping wells 160, 165, 170, 175. The first well can be used as an isolation well, the second well as a body well, the third well as a drift well, and the fourth well as a bungee well. Well contact regions 162, 167 may be provided, and isolation regions may be provided, such as drift isolation regions 192 and well contact isolation regions 194, which may be provided with metal halide contacts on the gate electrodes, source/drain electrodes, and well contact regions.

在一實施例中，設置第五井180。該第五井作為低電壓(low voltage；LV)井，該低電壓井包括第二極型摻雜物，該低電壓井設於該漂移井內。在一實施例中，該低電壓井設置於該汲極井及該漂移井內側邊緣之間。如圖所示，該低電壓井設置於該漂移隔離區192下方。例如，該低電壓井設置於該漂移隔離區中心的下方。 In an embodiment, a fifth well 180 is provided. The fifth well acts as a low voltage (LV) well, the low voltage well including a second pole type dopant disposed in the drift well. In one embodiment, the low voltage well is disposed between the bungee well and the inner edge of the drift well. As shown, the low voltage well is disposed below the drift isolation region 192. For example, the low voltage well is disposed below the center of the drift isolation region.

已發現，該低電壓井可為增加該ESD裝置的保持電壓(Vh)。可以發現，藉由設置低電壓井，基極擴展現象被抑制。我們認為，該低電壓井沿水平方向為電流提供高電阻路徑。如此，引導電流沿垂直方向而非水平方向流動。此結果導致該ESD裝置具有改進的更均勻導通。 It has been found that the low voltage well can increase the holding voltage (Vh) of the ESD device. It can be found that the base extension phenomenon is suppressed by setting a low voltage well. We believe that this low voltage well provides a high resistance path for current in the horizontal direction. As such, the pilot current flows in a vertical direction rather than a horizontal direction. This result results in an improved more uniform conduction of the ESD device.

第1c圖係顯示裝置100c的另一實施例的剖視圖。裝置100c類似第1a圖的裝置。共同的元件將不再 加以描述或詳細描述。如圖所示，基板105具有由裝置隔離區190隔離的裝置區。該裝置區包括橫向擴散電晶體115，係作為ESD保護電路。該裝置區包括第一、第二、第三及第四摻雜井160、165、170、175。該第一井可作為隔離井，該第二井作為體井，該第三井作為漂移井，且該第四井作為汲極井。可設置井接觸區162、167，可設置隔離區，例如，漂移隔離區192及井接觸隔離區192。可在該閘極電極、源/汲極以及井接觸區上設置金屬矽化物接觸。 Figure 1c is a cross-sectional view of another embodiment of the display device 100c. Device 100c is similar to the device of Figure 1a. Common components will no longer Describe or describe in detail. As shown, the substrate 105 has a device region that is isolated by the device isolation region 190. The device region includes a laterally diffusing transistor 115 as an ESD protection circuit. The device region includes first, second, third, and fourth doping wells 160, 165, 170, 175. The first well can be used as an isolation well, the second well as a body well, the third well as a drift well, and the fourth well as a bungee well. Well contact regions 162, 167 may be provided, and isolation regions may be provided, such as drift isolation region 192 and well contact isolation region 192. Metal telluride contacts can be placed on the gate electrode, source/drain, and well contact regions.

依據一實施例，縮小該漂移井。如圖所示，縮小該漂移井以使其內側邊緣不會延伸至該閘極下方，且不會延伸至該通道區內。例如，該漂移井內側邊緣位於漂移隔離區192中心及裝置隔離區190下方。 According to an embodiment, the drift well is shrunk. As shown, the drift well is shrunk such that its inner edge does not extend below the gate and does not extend into the channel region. For example, the inner edge of the drift well is located below the center of the drift isolation region 192 and below the device isolation region 190.

已發現，縮小該漂移井可增加該ESD裝置的保持電壓(Vh)。可以發現，藉由縮小該漂移井，基極擴展現象被抑制。增加該ESD電路的寄生雙極型電晶體(BJT)的基極，以降低基區擴展現象，從而導致該ESD裝置具有改進的均勻導通。 It has been found that shrinking the drift well can increase the holding voltage (Vh) of the ESD device. It can be found that by narrowing the drift well, the base expansion phenomenon is suppressed. The base of the parasitic bipolar transistor (BJT) of the ESD circuit is increased to reduce the base extension phenomenon, resulting in improved uniform conduction of the ESD device.

第1d圖係顯示裝置100d的又一實施例的剖視圖。裝置100d類似第1a圖的裝置。共同的元件將不再加以描述或詳細描述。如圖所示，基板105具有由裝置隔離區190隔離的裝置區，該裝置區包括橫向擴散電晶體115，係作為ESD保護電路。該裝置區包括第一、第二及第四摻雜井160、165、175。該第一井可作為隔離井，該 第二井作為體井，且該第四井作為汲極井。可設置井接觸區162、167，可設置隔離區，例如，漂移隔離區192以及井接觸隔離區194。可在該閘極電極、源/汲極及井接觸區上設置金屬矽化物接觸。 Fig. 1d is a cross-sectional view of still another embodiment of the display device 100d. Device 100d is similar to the device of Figure 1a. Common components will not be described or described in detail. As shown, substrate 105 has a device region that is isolated by device isolation region 190, which includes laterally diffusing transistor 115 as an ESD protection circuit. The device region includes first, second, and fourth doping wells 160, 165, 175. The first well can be used as an isolation well, The second well acts as a body well and the fourth well acts as a bungee well. Well contact regions 162, 167 may be provided, and isolation regions may be provided, such as drift isolation region 192 and well contact isolation region 194. A metal telluride contact can be placed on the gate electrode, source/drain, and well contact regions.

依據一實施例，與第1a圖的裝置100a不同，不設置漂移井。如圖所示，該體井至少包圍該第一源極/汲極以及一部分該閘極。如圖所示，該體井包圍該第一源極/汲極以及自該閘極的第一側之該閘極的部分。在未設置漂移井的情況下，該汲極藉由該隔離井耦接該通道，例如，依據總體的汲極面積可優化該汲極井。移除該漂移井消除了基極擴展現象，電流經引導且僅沿垂直方向流動，此結果導致該ESD裝置上具有改進的均勻導通。亦可發現，該配置改進了ESD性能。 According to an embodiment, unlike the device 100a of Fig. 1a, no drift well is provided. As shown, the body well surrounds at least the first source/drain and a portion of the gate. As shown, the body well surrounds the first source/drain and portions of the gate from the first side of the gate. In the absence of a drift well, the drain is coupled to the passage by the isolation well, for example, the anode well can be optimized based on the overall drain area. Removing the drift well eliminates the base expansion phenomenon, the current is directed and flows only in the vertical direction, which results in improved uniform conduction on the ESD device. It can also be found that this configuration improves ESD performance.

第2a圖係顯示裝置200a的替代實施例的剖視圖。該裝置類似第1a圖的裝置100a。共同的元件將不再加以描述或詳細描述。如圖所示，設置基板105。例如，該基板為半導體基板，例如，矽基板，亦可使用其他類型的基板。在該基板上定義裝置區110。可設置裝置隔離區190，以將該裝置區與該基板上的其他裝置區隔離或分離。在一實施例中，該裝置隔離區圍繞該裝置區，例如，該隔離區為淺溝槽隔離(shallow trench isolation；STI)區，亦可使用其他類型的隔離區。 Figure 2a is a cross-sectional view of an alternate embodiment of display device 200a. This device is similar to device 100a of Figure 1a. Common components will not be described or described in detail. As shown in the figure, the substrate 105 is provided. For example, the substrate is a semiconductor substrate, for example, a germanium substrate, and other types of substrates may be used. A device region 110 is defined on the substrate. A device isolation region 190 can be provided to isolate or separate the device region from other device regions on the substrate. In one embodiment, the device isolation region surrounds the device region. For example, the isolation region is a shallow trench isolation (STI) region, and other types of isolation regions may be used.

該裝置區包括ESD保護電路215。該ESD保護電路包括多個並聯耦接的橫向擴散電晶體。例如，該 ESD保護電路包括n個橫向擴散電晶體。如圖所示，該裝置區包括第一及第二(例如，n=2)橫向擴散電晶體115a、115b。亦可設置其他數量的橫向擴散電晶體。 The device area includes an ESD protection circuit 215. The ESD protection circuit includes a plurality of laterally diffused transistors coupled in parallel. For example, the The ESD protection circuit includes n laterally diffusing transistors. As shown, the device region includes first and second (e.g., n = 2) laterally diffusing transistors 115a, 115b. Other numbers of laterally diffusing transistors can also be provided.

第一摻雜井160設置於該裝置區的該基板中。如圖所示，該第一摻雜井包圍該全部裝置區。例如，該第一摻雜井作為隔離井，該第一井包括第一極型摻雜物。在一實施例中，該第一井以第一極型摻雜物輕摻雜，亦可設置具有其他摻雜濃度的第一井。 A first doping well 160 is disposed in the substrate of the device region. As shown, the first doping well surrounds the entire device area. For example, the first doped well acts as an isolation well and the first well includes a first pole type dopant. In one embodiment, the first well is lightly doped with a first pole type dopant, and a first well having other doping concentrations may also be provided.

電晶體包括閘極120，係設置於該裝置區中的該基板表面上。該閘極包括設置於閘極介電層124上方的閘極電極126。該閘極可為閘極導體，係構成多個電晶體的閘極。該閘極設於第一及第二源極/汲極(S/D)區130、140之間，該第一源極/汲極鄰近該閘極的第一側。在一實施例中，該閘極重疊該第一源極/汲極，例如，該閘極的該第一側重疊該第一源極/汲極，重疊量應當足以使該第一源極/汲極與該閘極下方的該電晶體的通道連接。例如，重疊量約為0.1至0.5μm。在一實施例中，該閘極重疊該第一源極/汲極的輕摻雜(lightly doped；LD)區，該第一源極/汲極亦可具有其他配置。該第二源極/汲極離開該閘極的第二側，例如，其位移可為漂移距離。 The transistor includes a gate 120 disposed on a surface of the substrate in the device region. The gate includes a gate electrode 126 disposed over the gate dielectric layer 124. The gate may be a gate conductor and constitute a gate of a plurality of transistors. The gate is disposed between the first and second source/drain (S/D) regions 130, 140, the first source/drain being adjacent to the first side of the gate. In one embodiment, the gate overlaps the first source/drain, for example, the first side of the gate overlaps the first source/drain, and the amount of overlap should be sufficient for the first source/ The drain is connected to the channel of the transistor below the gate. For example, the amount of overlap is about 0.1 to 0.5 μm. In one embodiment, the gate overlaps the first source/drain lightly doped (LD) region, and the first source/drain may have other configurations. The second source/drain exits the second side of the gate, for example, the displacement can be a drift distance.

在一實施例中，在該閘極與該第二源極/汲極之間設置漂移隔離區192。例如，該漂移隔離區為淺溝槽隔離，亦可使用其他類型的漂移隔離區。如圖所示，該閘極重疊該漂移隔離區，該漂移隔離區可用於增加有效漂 移距離。例如，可將該漂移距離增加至與該漂移隔離區的剖面相等。 In an embodiment, a drift isolation region 192 is disposed between the gate and the second source/drain. For example, the drift isolation region is shallow trench isolation, and other types of drift isolation regions can be used. As shown, the gate overlaps the drift isolation region, and the drift isolation region can be used to increase effective drift Move the distance. For example, the drift distance can be increased to be equal to the profile of the drift isolation region.

該閘極的側壁可具有介電間隔件128。例如，該些介電間隔件可為氧化矽間隔件。亦可使用其他類型的介電材料，例如，氮化矽或介電材料或層的組合。例如，該些間隔件可為複合間隔件。該些間隔件可幫助形成該輕摻雜區及源/汲極。例如，在形成間隔件之前形成該輕摻雜區，而在形成間隔件後形成該第一源極/汲極，亦可使用其他配置的間隔件，例如，該間隔件可為單個間隔件。在一些情況下，該電晶體亦可包括環狀(halo)區，該環狀區為第二極型摻雜區，鄰接該閘極下方的該輕摻雜區及第一源極/汲極。 The sidewall of the gate can have a dielectric spacer 128. For example, the dielectric spacers can be yttria spacers. Other types of dielectric materials can also be used, such as tantalum nitride or dielectric materials or combinations of layers. For example, the spacers can be composite spacers. The spacers can help form the lightly doped region and the source/drain. For example, the lightly doped region is formed prior to forming the spacer, and the first source/drain is formed after the spacer is formed, and other configured spacers may be used, for example, the spacer may be a single spacer. In some cases, the transistor may further include a halo region, which is a second pole doped region adjacent to the lightly doped region under the gate and the first source/drain .

在一些實施例中，在該些電晶體上方形成介電蝕刻停止層(未圖示)。例如，該蝕刻停止層為氮化矽蝕刻停止層。亦可使用其他類型的蝕刻停止層。該蝕刻停止層應當具有可自上方的介電層選擇性移除的材料。該蝕刻停止層幫助形成接觸該電晶體的區域(例如，該閘極電極及摻雜區)的接觸塞。在一些實施例中，該蝕刻停止層亦可作為應力層，以施加應力於該閘極下方的該電晶體通道上，從而提升性能。 In some embodiments, a dielectric etch stop layer (not shown) is formed over the plurality of transistors. For example, the etch stop layer is a tantalum nitride etch stop layer. Other types of etch stop layers can also be used. The etch stop layer should have a material that is selectively removable from the upper dielectric layer. The etch stop layer helps form a contact plug that contacts a region of the transistor (eg, the gate electrode and the doped region). In some embodiments, the etch stop layer can also act as a stressor layer to apply stress to the transistor channel under the gate to improve performance.

如圖所示，該第一及第二橫向擴散電晶體經配置而具有共同的第二源極/汲極或汲極，該些橫向擴散電晶體亦可具有其他配置。 As shown, the first and second laterally diffusing transistors are configured to have a common second source/drain or drain, and the laterally diffusing transistors can have other configurations.

在該基板中設置第二井165。該第二井可設 置於該裝置區中，例如，該第二井設於該第一井內。該第二井作為該些電晶體的體井，該第二裝置井包括第二極型摻雜物。該第二裝置井可以第一極型摻雜物輕摻雜(x-)或中等摻雜(x)，該第二裝置井亦可具有其他摻雜濃度。 A second well 165 is disposed in the substrate. The second well can be set Placed in the device zone, for example, the second well is disposed within the first well. The second well serves as a body well of the plurality of transistors, and the second device well includes a second pole type dopant. The second device well may be lightly doped (x-) or moderately doped (x) with the first pole type dopant, and the second device well may also have other doping concentrations.

該體井至少包圍該第一源極/汲極以及一部分該閘極。如圖所示，該體井包圍該第一及第二源極/汲極，該第二井亦可具有其他配置，該第二井的深度淺於該第一井，該第二井亦可具有其他深度。 The body well surrounds at least the first source/drain and a portion of the gate. As shown, the body well surrounds the first and second source/drain electrodes, and the second well may have other configurations. The second well has a shallower depth than the first well, and the second well may also Has other depths.

在一實施例中，該第一及第二井設有第一及第二井接觸162、167，以偏置該些井。該些井接觸為重摻雜區，類似該些源/汲極。例如，井接觸的深度淺於該裝置隔離區的深度，且該些井接觸分別與該些井連接。該些井接觸的摻雜濃度可約為5E15/cm3至9E15/cm3。該些井接觸具有與該些井相同的極型。例如，該第一井接觸為第一極型摻雜區，且該第二井接觸為第二極型摻雜區。 In one embodiment, the first and second wells are provided with first and second well contacts 162, 167 to bias the wells. The well contacts are heavily doped regions, similar to the source/drain electrodes. For example, the depth of the well contact is shallower than the depth of the isolation zone of the device, and the well contacts are respectively connected to the wells. The wells may have a doping concentration of about 5E15/cm 3 to 9E15/cm 3 . The well contacts have the same pole type as the wells. For example, the first well contact is a first pole doped region and the second well contact is a second pole doped region.

在一實施例中，可設置隔離區194以分離接觸區。該些隔離區可為淺溝槽隔離區。例如，該些隔離區可類似該些裝置隔離區。亦可使用其他類型或配置的隔離區。 In an embodiment, isolation regions 194 may be provided to separate the contact regions. The isolation regions can be shallow trench isolation regions. For example, the isolation regions can be similar to the device isolation regions. Other types or configurations of quarantines can also be used.

可在該閘極電極以及各接觸區上形成金屬矽化物接觸(未圖示)。例如，可在該些源/汲極、井接觸以及閘極電極上方設置金屬矽化物接觸。例如，該些矽化物接觸可為鎳基接觸，亦可使用其他類型的金屬矽化物接觸。例如，該些矽化物接觸可為矽化鈷(CoSi)接觸，該些 矽化物接觸的厚度可約為100至500埃，亦可使用具有其他厚度的矽化物接觸，該些矽化物接觸可用於降低接觸電阻且促進與後端制程的金屬互連的接觸。 A metal halide contact (not shown) may be formed on the gate electrode and each contact region. For example, metal telluride contacts can be placed over the source/drain, well contacts, and gate electrodes. For example, the telluride contacts can be nickel-based contacts, and other types of metal halide contacts can also be used. For example, the telluride contacts can be cobalt hydride (CoSi) contacts, The telluride contact may have a thickness of between about 100 and 500 angstroms, and may also be used with other thicknesses of telluride contacts that may be used to reduce contact resistance and facilitate contact with metal interconnects in the back end process.

在一實施例中，設置第三井170。該第三井設置於該第二井內的該基板中。例如，該第三井的深度淺於該第二井的深度，該第三井作為漂移井。在一實施例中，該第三井包圍該第二源極/汲極且延伸於該閘極下方，該閘極重疊該第三井或漂移井，以形成閘極重疊區Ogate。 In an embodiment, a third well 170 is provided. The third well is disposed in the substrate within the second well. For example, the depth of the third well is shallower than the depth of the second well, which acts as a drift well. In one embodiment, the third well surrounds the second source/drain and extends below the gate, the gate overlapping the third well or drift well to form a gate overlap region O gate .

在一實施例中，該第三井的深度或底部位於該隔離區下方。例如，該漂移井自該裝置隔離區的底部延伸至該閘極下方。該第三井的深度可約為0.1至5μm，亦可具有其他深度，例如，其深度可取決於該裝置的設計電壓。位於該第一源極/汲極與第三井之間的該閘極下方的該基板形成該電晶體的通道，有效漂移距離始於該第二源極/汲極，繞過該漂移隔離區且到達該閘極下方的該通道。 In an embodiment, the depth or bottom of the third well is below the isolation zone. For example, the drift well extends from the bottom of the device isolation region to below the gate. The third well may have a depth of about 0.1 to 5 [mu]m and may have other depths, for example, the depth may depend on the design voltage of the device. The substrate under the gate between the first source/drain and the third well forms a channel of the transistor, the effective drift distance starting from the second source/drain, bypassing the drift isolation region And reach the channel below the gate.

該漂移井包括第一極型摻雜物。在一實施例中，該漂移井的摻雜濃度低於該汲極的摻雜濃度。在一實施例中，該漂移井可以第一極型摻雜物輕摻雜(x-)或中等摻雜(x)。例如，該漂移井的摻雜濃度約為1E12至1E14/cm3，亦可具有其他摻雜濃度。例如，其摻雜濃度可取決於該裝置的最大或崩潰電壓要求。 The drift well includes a first pole type dopant. In an embodiment, the drift well has a doping concentration that is lower than a doping concentration of the drain. In an embodiment, the drift well may be lightly doped (x-) or moderately doped (x) with the first pole type dopant. For example, the drift well has a doping concentration of about 1E12 to 1E14/cm 3 and may have other doping concentrations. For example, its doping concentration may depend on the maximum or breakdown voltage requirements of the device.

在一實施例中，該第二井、第一源極/汲極以及閘極共同耦接該ESD裝置的第一電極端。該第二源極/汲極耦接該ESD裝置的第二電極端。例如，該第一電極 端為源極端，且該第二電極端為汲極端。例如，該源極端耦接地，而該汲極端耦接VDD或I/O(輸入/輸出)焊墊。該ESD裝置亦可具有其他配置的端連接。 In one embodiment, the second well, the first source/drain, and the gate are coupled to the first electrode end of the ESD device. The second source/drain is coupled to the second electrode end of the ESD device. For example, the first electrode The terminal is the source terminal, and the second electrode terminal is the 汲 terminal. For example, the source is coupled to ground and the drain is coupled to a VDD or I/O (input/output) pad. The ESD device can also have other configurations of end connections.

依據一實施例，設置第四井175。例如，該第四井作為第二源極/汲極井或汲極井。該汲極井設置於該汲極下方的該基板中。例如，該第四井的寬度可窄於、等於或大於該汲極的寬度，取決於工作電壓。該汲極井的深度在該漂移隔離區的底部與體井之間，該汲極井亦可具有其他深度。 According to an embodiment, a fourth well 175 is provided. For example, the fourth well acts as a second source/dump or bungee well. The bungee well is disposed in the substrate below the drain. For example, the width of the fourth well may be narrower than, equal to, or greater than the width of the drain, depending on the operating voltage. The depth of the bungee well is between the bottom of the drift isolation zone and the body well, and the bungee well may have other depths.

該汲極井包括第一極型摻雜物。在一實施例中，該汲極井的摻雜濃度介於該第二源極/汲極與漂移井之間。在一實施例中，該汲極井可以第一極型摻雜物中等摻雜(x)。 The bungee well includes a first pole type dopant. In one embodiment, the doping concentration of the bungee well is between the second source/drain and the drift well. In an embodiment, the bungee well may be doped (x) in the first pole type dopant.

可以發現，藉由在該汲極下方設置汲極井，電流經引導沿垂直方向而非水平方向流動。如此，在早期階段減輕或抑制基極擴展。此結果導致該ESD裝置具有改進的更均勻導通。 It can be found that by providing a bungee well below the bungee, current is directed to flow in a vertical direction rather than a horizontal direction. As such, the base extension is mitigated or suppressed at an early stage. This result results in an improved more uniform conduction of the ESD device.

第2b圖係顯示裝置200b的另一實施例的剖視圖。該裝置類似第2a圖的裝置200a以及第1b圖的裝置100b。共同的元件將不再加以描述或詳細描述。如圖所示，基板105具有由裝置隔離區190隔離的裝置區。該裝置區包括ESD保護電路的第一及第二橫向擴散電晶體115a、115b。該裝置區包括第一、第二、第三以及第四摻雜井160、165、170、175。該第一井可作為隔離井，該第二井作為體 井，該第三井作為漂移井，且該第四井作為汲極井。可設置井接觸區162、167，可設置隔離區，例如，漂移隔離區192及井接觸隔離區194。可在該閘極電極、源/汲極及井接觸區上設置金屬矽化物接觸。 Figure 2b is a cross-sectional view of another embodiment of display device 200b. This device is similar to device 200a of Figure 2a and device 100b of Figure 1b. Common components will not be described or described in detail. As shown, the substrate 105 has a device region that is isolated by the device isolation region 190. The device region includes first and second lateral diffusion transistors 115a, 115b of the ESD protection circuit. The device region includes first, second, third, and fourth doping wells 160, 165, 170, 175. The first well can be used as an isolation well, and the second well is used as a body Well, the third well acts as a drift well and the fourth well acts as a bungee well. Well contact regions 162, 167 may be provided, and isolation regions may be provided, such as drift isolation region 192 and well contact isolation region 194. A metal telluride contact can be placed on the gate electrode, source/drain, and well contact regions.

在一實施例中，設置第五井180。該第五井作為低電壓井。該低電壓井包括第二極型摻雜物。該低電壓井設置於該漂移井內。在一實施例中，該低電壓井設置於該汲極井與該漂移井邊緣之間。如圖所示，該低電壓井設置於該漂移隔離區192下方。 In an embodiment, a fifth well 180 is provided. The fifth well acts as a low voltage well. The low voltage well includes a second pole type dopant. The low voltage well is disposed within the drift well. In an embodiment, the low voltage well is disposed between the bungee well and the edge of the drift well. As shown, the low voltage well is disposed below the drift isolation region 192.

已發現，該低電壓井可增加該ESD裝置的保持電壓(Vh)。可以發現，藉由設置低電壓井，基極擴展現象被抑制。我們認為，該低電壓井沿水平方向為電流提供高電阻路徑。如此，引導電流沿垂直方向而非水平方向流動。此結果導致該ESD裝置具有改進的更均勻導通。 It has been found that the low voltage well can increase the holding voltage (Vh) of the ESD device. It can be found that the base extension phenomenon is suppressed by setting a low voltage well. We believe that this low voltage well provides a high resistance path for current in the horizontal direction. As such, the pilot current flows in a vertical direction rather than a horizontal direction. This result results in an improved more uniform conduction of the ESD device.

第2c圖係顯示裝置200c的另一實施例的剖視圖。裝置200c類似第2a圖的裝置200a及第1c圖的裝置100c。共同的元件將不再加以描述或詳細描述。如圖所示，基板105具有由裝置隔離區190隔離的裝置區。該裝置區包括ESD保護電路的第一及第二橫向擴散電晶體115a、115b。該裝置區包括第一、第二、第三及第四摻雜井160、165、170、175。該第一井可作為隔離井，該第二井作為體井，該第三井作為漂移井，且該第四井作為汲極井。可設置井接觸區162、167。可設置隔離區，例如，漂移隔離區192及井接觸隔離區192，可在該閘極電極、源/ 汲極及井接觸區上設置金屬矽化物接觸。 Figure 2c is a cross-sectional view of another embodiment of display device 200c. The device 200c is similar to the device 200a of Fig. 2a and the device 100c of Fig. 1c. Common components will not be described or described in detail. As shown, the substrate 105 has a device region that is isolated by the device isolation region 190. The device region includes first and second lateral diffusion transistors 115a, 115b of the ESD protection circuit. The device region includes first, second, third, and fourth doping wells 160, 165, 170, 175. The first well can be used as an isolation well, the second well as a body well, the third well as a drift well, and the fourth well as a bungee well. Well contact zones 162, 167 can be provided. An isolation region, such as a drift isolation region 192 and a well contact isolation region 192, may be provided at the gate electrode, source/ Metal halide contact is placed on the bungee and well contact areas.

依據一實施例，縮小該漂移井。如圖所示，縮小該漂移井，以使其邊緣不會延伸於該閘極下方，且不會延伸至該通道區內。例如，該漂移井的內側邊緣位於該漂移隔離區192的中心下方。 According to an embodiment, the drift well is shrunk. As shown, the drift well is shrunk so that its edges do not extend below the gate and do not extend into the channel region. For example, the inner edge of the drift well is below the center of the drift isolation region 192.

已發現，縮小該漂移井可增加該ESD裝置的保持電壓(Vh)。可以發現，藉由縮小該漂移井，基極擴展現象被抑制。增加該ESD電路的寄生雙極型電晶體(BJT)的基極，以降低基區擴展現象，從而導致該ESD裝置具有改進的均勻導通。 It has been found that shrinking the drift well can increase the holding voltage (Vh) of the ESD device. It can be found that by narrowing the drift well, the base expansion phenomenon is suppressed. The base of the parasitic bipolar transistor (BJT) of the ESD circuit is increased to reduce the base extension phenomenon, resulting in improved uniform conduction of the ESD device.

第2d圖係顯示裝置200d的另一實施例的剖視圖。該裝置類似第2a圖的裝置200a及第1d圖的裝置100d。共同的元件將不再加以描述或詳細描述。如圖所示，基板105具有由裝置隔離區190隔離的裝置區。該裝置區包括ESD保護電路的第一及第二橫向擴散電晶體115a、115b。該裝置區包括第一、第二及第四摻雜井160、165、175。該第一井可作為隔離井，該第二井作為體井，且該第四井作為汲極井。可設置井接觸區162、167，可設置隔離區，例如，漂移隔離區192以及井接觸隔離區194，可在該閘極電極、源/汲極以及井接觸區上設置金屬矽化物接觸。 Fig. 2d is a cross-sectional view of another embodiment of the display device 200d. This device is similar to the device 200a of Fig. 2a and the device 100d of Fig. 1d. Common components will not be described or described in detail. As shown, the substrate 105 has a device region that is isolated by the device isolation region 190. The device region includes first and second lateral diffusion transistors 115a, 115b of the ESD protection circuit. The device region includes first, second, and fourth doping wells 160, 165, 175. The first well can be used as an isolation well, the second well as a body well, and the fourth well as a bungee well. Well contact regions 162, 167 may be provided, and isolation regions may be provided, such as drift isolation regions 192 and well contact isolation regions 194, which may be provided with metal halide contacts on the gate electrodes, source/drain electrodes, and well contact regions.

依據一實施例，與第2a圖的裝置200a不同，不設置漂移井。如圖所示，該體井至少包圍該第一源極/汲極以及一部分該閘極。如圖所示，該體井包圍該第一 源極/汲極以及自該閘極的第一側起的該閘極的部分。在未設置漂移井的情況下，該汲極藉由該隔離井耦接該通道，例如，依據總體的汲極面積可優化該汲極井。移除該漂移井消除了基極擴展現象。電流經引導且僅沿垂直方向流動。此結果導致該ESD裝置具有改進的更均勻導通。亦可發現，該配置改進了ESD性能。 According to an embodiment, unlike the device 200a of Figure 2a, no drift well is provided. As shown, the body well surrounds at least the first source/drain and a portion of the gate. As shown, the body surrounds the first a source/drain and a portion of the gate from the first side of the gate. In the absence of a drift well, the drain is coupled to the passage by the isolation well, for example, the anode well can be optimized based on the overall drain area. Removing the drift well eliminates the base expansion phenomenon. The current is directed and flows only in the vertical direction. This result results in an improved more uniform conduction of the ESD device. It can also be found that this configuration improves ESD performance.

可以其他特定形式實施本發明而不背離本發明的精神或基本特徵。因此，上述實施例在各方面被視為說明性質而非限制本發明。因此，本發明的範圍由所附申請專利範圍而非上述說明表示，且意圖包括在該申請專利範圍的等同意義及範圍內的所有變更。 The invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the above-described embodiments are to be considered in all respects as illustrative and not limiting. Therefore, the scope of the invention is to be construed as being limited by the scope of the claims

100a‧‧‧裝置 100a‧‧‧ device

105‧‧‧基板 105‧‧‧Substrate

110‧‧‧裝置區 110‧‧‧Device area

115‧‧‧ESD保護電路 115‧‧‧ESD protection circuit

120‧‧‧閘極 120‧‧‧ gate

124‧‧‧閘極介電層 124‧‧‧ gate dielectric layer

126‧‧‧閘極電極 126‧‧‧gate electrode

130‧‧‧第一源極/汲極區 130‧‧‧First source/bungee area

134‧‧‧第一電極端 134‧‧‧first electrode end

140‧‧‧第二源極/汲極區 140‧‧‧Second source/drain region

144‧‧‧第二電極端 144‧‧‧second electrode end

160‧‧‧第一井 160‧‧‧First Well

162‧‧‧第一井接觸 162‧‧‧First well contact

165‧‧‧第二井 165‧‧‧ second well

167‧‧‧第二井接觸 167‧‧‧Second well contact

170‧‧‧第三井 170‧‧‧ third well

175‧‧‧第四井 175‧‧‧fourth well

190、194‧‧‧隔離區 190, 194‧‧ ‧ quarantine area

192‧‧‧漂移隔離區 192‧‧‧ Drift isolation zone

Claims (21)

一種具有靜電放電保護電路之裝置，係包括：基板，係定義為裝置區，該裝置區包括具有電晶體的靜電放電(ESD)保護電路，其中，該電晶體包括：閘極，係具有第一側及第二側，第一擴散區，係位於鄰近該閘極之該第一側的該裝置區中，其中，該閘極重疊該第一擴散區，第二擴散區，係位於離開該閘極之該第二側的該裝置區中，其中，該第一及第二擴散區包括第一極型摻雜物，以及漂移隔離區，係設置於該閘極及該第二擴散區之間；第一裝置井，係包圍該裝置區；第二裝置井，係設置於該第一裝置井內；以及汲極井，係具有該第一極型摻雜物，該汲極井設置於該第二擴散區下方及該第一裝置井內。 An apparatus having an electrostatic discharge protection circuit includes: a substrate defined as a device region, the device region including an electrostatic discharge (ESD) protection circuit having a transistor, wherein the transistor includes: a gate having a first a side and a second side, the first diffusion region is located in the device region adjacent to the first side of the gate, wherein the gate overlaps the first diffusion region, and the second diffusion region is located away from the gate In the device region of the second side, wherein the first and second diffusion regions comprise a first pole type dopant, and a drift isolation region is disposed between the gate electrode and the second diffusion region a first device well surrounding the device region; a second device well disposed in the first device well; and a bungee well having the first pole type dopant, the bungee well being disposed at the Below the second diffusion zone and within the first device well. 如申請專利範圍第1項所述的裝置，其中，該第一裝置井包括該第一極型摻雜物，且該第二裝置井包括第二極型摻雜物。 The device of claim 1, wherein the first device well comprises the first pole type dopant and the second device well comprises a second pole type dopant. 如申請專利範圍第2項所述的裝置，其中，該第一極型包括n型，且該第二極型包括p型。 The device of claim 2, wherein the first pole type comprises an n-type and the second pole type comprises a p-type. 如申請專利範圍第1項所述的裝置，其中，該第二裝置井至少包圍該第一擴散區及一部分該閘極。 The device of claim 1, wherein the second device well surrounds at least the first diffusion region and a portion of the gate. 如申請專利範圍第4項所述的裝置，其中，該第二裝 置井包圍該閘極、該漂移隔離區及該第二擴散區。 The device of claim 4, wherein the second device The well surrounds the gate, the drift isolation region, and the second diffusion region. 如申請專利範圍第1項所述的裝置，復包括漂移井，設置於該第二裝置井內。 The device of claim 1, wherein the device comprises a drift well disposed in the second device well. 如申請專利範圍第6項所述的裝置，其中，該第一裝置井及該漂移井包括該第一極型摻雜物，且該第二裝置井包括第二極型摻雜物。 The device of claim 6, wherein the first device well and the drift well comprise the first pole type dopant, and the second device well comprises a second pole type dopant. 如申請專利範圍第7項所述的裝置，其中，該第一極型包括n型，且該第二極型包括p型。 The device of claim 7, wherein the first pole type comprises an n-type and the second pole type comprises a p-type. 如申請專利範圍第6項所述的裝置，其中，該漂移井包圍該第二擴散區。 The device of claim 6, wherein the drift well surrounds the second diffusion region. 如申請專利範圍第9項所述的裝置，其中，該漂移井自該閘極的該第二側延伸於該閘極下方。 The device of claim 9, wherein the drift well extends from the second side of the gate below the gate. 如申請專利範圍第1項所述的裝置，其中，該閘極重疊該第一擴散區0.1-0.5μm。 The device of claim 1, wherein the gate overlaps the first diffusion region by 0.1-0.5 μm. 如申請專利範圍第1項所述的裝置，其中，該汲極井具有介於該漂移隔離區與該第二裝置井之間的深度。 The device of claim 1, wherein the bungee well has a depth between the drift isolation zone and the second device well. 如申請專利範圍第12項所述的裝置，其中，該汲極井具有窄於該第二裝置井的寬度。 The device of claim 12, wherein the bungee well has a width that is narrower than the second device well. 一種靜電放電保護電路，係包括：基板，係具有位於裝置區中的第一裝置井及第二裝置井，其中，該第二裝置井設置於該第一裝置井內；電晶體，係位於該裝置區中，其中，該電晶體包括：閘極，係具有第一側及第二側，以及 鄰近該閘極的該第一側的第一擴散區以及離開該閘極的該第二側的第二擴散區，其中，該閘極重疊該第一擴散區，以及漂移隔離區，係設於該閘極及該第二擴散區之間；以及汲極井，係設置於該第二擴散區下方及該第一裝置井內。 An electrostatic discharge protection circuit includes: a substrate having a first device well and a second device well located in the device region, wherein the second device well is disposed in the first device well; the transistor is located in the In the device area, wherein the transistor comprises: a gate having a first side and a second side, and a first diffusion region on the first side adjacent to the gate and a second diffusion region on the second side exiting the gate, wherein the gate overlaps the first diffusion region, and the drift isolation region is The gate and the second diffusion region; and the bungee well are disposed below the second diffusion region and in the first device well. 如申請專利範圍第14項所述的靜電放電保護電路，其中，該第一及第二擴散區、該第一裝置井及該汲極井包括第一極型摻雜物，且該第二裝置井包括第二極型摻雜物。 The electrostatic discharge protection circuit of claim 14, wherein the first and second diffusion regions, the first device well and the drain well comprise a first pole type dopant, and the second device The well includes a second pole type dopant. 如申請專利範圍第15項所述的靜電放電保護電路，其中，該第一極型包括n型，且該第二極型包括p型。 The electrostatic discharge protection circuit of claim 15, wherein the first pole type comprises an n-type and the second pole type comprises a p-type. 如申請專利範圍第14項所述的靜電放電保護電路，其中，該第二裝置井至少包圍該第一擴散區以及一部分該閘極。 The electrostatic discharge protection circuit of claim 14, wherein the second device well surrounds at least the first diffusion region and a portion of the gate. 如申請專利範圍第17項所述的靜電放電保護電路，其中，該第二裝置井包圍該閘極、該漂移隔離區及該第二擴散區。 The electrostatic discharge protection circuit of claim 17, wherein the second device well surrounds the gate, the drift isolation region, and the second diffusion region. 如申請專利範圍第14項所述的靜電放電保護電路，復包括漂移井，設置於該第二裝置井內。 The electrostatic discharge protection circuit of claim 14, comprising a drift well disposed in the second device well. 如申請專利範圍第14項所述的靜電放電保護電路，其中，該閘極重疊該第一擴散區0.1-0.5μm。 The electrostatic discharge protection circuit of claim 14, wherein the gate overlaps the first diffusion region by 0.1-0.5 μm. 一種具有靜電放電保護電路之裝置，係包括： 基板，係定義為裝置區，該裝置區包括具有電晶體的靜電放電(ESD)保護電路，其中，該電晶體包括：閘極，係具有第一側及第二側，第一擴散區，係位於鄰近該閘極之該第一側的該裝置區中，第二擴散區，係位於離開該閘極之該第二側的該裝置區中，其中，該第一及第二擴散區包括第一極型摻雜物，以及漂移隔離區，係設置於該閘極及該第二擴散區之間；第一裝置井，係包圍該裝置區；第二裝置井，係設置於該第一裝置井內；汲極井，係具有該第一極型摻雜物，該汲極井設置於該第二擴散區下方及該第一裝置井內；以及低電壓井，其中，該低電壓井設置於該漂移井內與該漂移隔離區下方。 A device having an electrostatic discharge protection circuit, comprising: The substrate is defined as a device region, and the device region includes an electrostatic discharge (ESD) protection circuit having a transistor, wherein the transistor includes: a gate having a first side and a second side, a first diffusion region, a second diffusion region located in the device region adjacent to the second side of the gate, wherein the first and second diffusion regions are included a pole type dopant, and a drift isolation region disposed between the gate and the second diffusion region; a first device well surrounding the device region; and a second device well disposed on the first device In the well; the bungee well has the first pole type dopant, the bungee well is disposed below the second diffusion zone and the first device well; and the low voltage well, wherein the low voltage well is set Within the drift well and below the drift isolation region.
TW101146035A 2012-01-19 2012-12-07 Esd protection circuit TWI549253B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201261588186P 2012-01-19 2012-01-19
US13/669,409 US8853783B2 (en) 2012-01-19 2012-11-05 ESD protection circuit

Publications (2)

Publication Number Publication Date
TW201338125A TW201338125A (en) 2013-09-16
TWI549253B true TWI549253B (en) 2016-09-11

Family

ID=48742538

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101146035A TWI549253B (en) 2012-01-19 2012-12-07 Esd protection circuit

Country Status (6)

Country Link
US (1) US8853783B2 (en)
KR (1) KR20130085355A (en)
CN (1) CN103219362B (en)
DE (1) DE102013200649B4 (en)
SG (1) SG192335A1 (en)
TW (1) TWI549253B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853022B2 (en) 2012-01-17 2014-10-07 Globalfoundries Singapore Pte. Ltd. High voltage device
US8822291B2 (en) * 2012-01-17 2014-09-02 Globalfoundries Singapore Pte. Ltd. High voltage device
US9040367B2 (en) * 2012-08-21 2015-05-26 Globalfoundries Singapore Pte. Ltd. Latch-up immunity nLDMOS
US8878297B2 (en) * 2012-09-25 2014-11-04 Globalfoundries Singapore Pte. Ltd. ESD protection circuit
TWI562331B (en) 2012-11-05 2016-12-11 Globalfoundries Sg Pte Ltd Esd protection circuit
US9754929B2 (en) * 2014-06-20 2017-09-05 Texas Instruments Incorporated Positive strike SCR, negative strike SCR, and a bidirectional ESD structure that utilizes the positive strike SCR and the negative strike SCR
US10217821B2 (en) * 2014-09-01 2019-02-26 Sk Hynix System Ic Inc. Power integrated devices, electronic devices and electronic systems including the same
KR102248307B1 (en) * 2014-09-01 2021-05-04 에스케이하이닉스 시스템아이씨 주식회사 Power integrated device, and electronic device and electronic system having the power integrated device
DE102015107680B4 (en) * 2015-05-15 2020-07-30 Infineon Technologies Ag Integrated circuit with lateral field effect transistor with isolated gate
US10032765B1 (en) 2017-05-18 2018-07-24 Globalfoundries Singapore Pte. Ltd. Integrated circuits with electrostatic discharge protection and methods for producing the same
US10453836B2 (en) 2017-08-17 2019-10-22 Globalfoundries Singapore Pte. Ltd. High holding high voltage (HHHV) FET for ESD protection with modified source and method for producing the same
US10037988B1 (en) * 2017-08-24 2018-07-31 Globalfoundries Singapore Pte. Ltd. High voltage PNP using isolation for ESD and method for producing the same
US10340266B2 (en) * 2017-10-02 2019-07-02 Globalfoundries Singapore Pte. Ltd. ESD protection circuit and method of making the same
US10672903B2 (en) * 2018-07-25 2020-06-02 Nxp Usa, Inc. Semiconductor device with drain active area
US11476244B2 (en) * 2020-08-19 2022-10-18 Globalfoundries Singapore Pte. Ltd. Laterally-diffused metal-oxide-semiconductor devices for electrostatic discharge protection applications
TWI817861B (en) * 2022-12-06 2023-10-01 世界先進積體電路股份有限公司 Electrostatic discharge protection device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050285200A1 (en) * 2004-06-29 2005-12-29 Magnachip Semiconductor, Ltd. Device for electrostatic discharge protection
TWI253721B (en) * 2004-06-14 2006-04-21 Nec Electronics Corp MOS type semiconductor device having electrostatic discharge protection arrangement
TWI260762B (en) * 2003-09-12 2006-08-21 Grace Semiconductor Mfg Corp Manufacturing method of transistor in ESD protection device
US20090072314A1 (en) * 2007-09-19 2009-03-19 Texas Instruments Incorporated Depletion Mode Field Effect Transistor for ESD Protection
TW201108383A (en) * 2009-08-18 2011-03-01 United Microelectronics Corp ESD protection device structure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3315356B2 (en) * 1997-10-15 2002-08-19 株式会社東芝 High voltage semiconductor device
US6835985B2 (en) * 2000-12-07 2004-12-28 Chartered Semiconductor Manufacturing Ltd. ESD protection structure
US20020076876A1 (en) * 2000-12-15 2002-06-20 Ming-Dou Ker Method for manufacturing semiconductor devices having ESD protection
JP4313789B2 (en) * 2005-07-29 2009-08-12 富士通マイクロエレクトロニクス株式会社 Semiconductor imaging device and manufacturing method thereof
JP5108250B2 (en) * 2006-04-24 2012-12-26 オンセミコンダクター・トレーディング・リミテッド Semiconductor device and manufacturing method thereof
JP2008078469A (en) * 2006-09-22 2008-04-03 Texas Instr Japan Ltd Field effect transistor
US7541247B2 (en) * 2007-07-16 2009-06-02 International Business Machines Corporation Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication
KR101057651B1 (en) * 2008-11-24 2011-08-18 주식회사 동부하이텍 Method of manufacturing semiconductor device
US7786507B2 (en) * 2009-01-06 2010-08-31 Texas Instruments Incorporated Symmetrical bi-directional semiconductor ESD protection device
JP5546191B2 (en) * 2009-09-25 2014-07-09 セイコーインスツル株式会社 Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI260762B (en) * 2003-09-12 2006-08-21 Grace Semiconductor Mfg Corp Manufacturing method of transistor in ESD protection device
TWI253721B (en) * 2004-06-14 2006-04-21 Nec Electronics Corp MOS type semiconductor device having electrostatic discharge protection arrangement
US20050285200A1 (en) * 2004-06-29 2005-12-29 Magnachip Semiconductor, Ltd. Device for electrostatic discharge protection
US20090072314A1 (en) * 2007-09-19 2009-03-19 Texas Instruments Incorporated Depletion Mode Field Effect Transistor for ESD Protection
TW201108383A (en) * 2009-08-18 2011-03-01 United Microelectronics Corp ESD protection device structure

Also Published As

Publication number Publication date
US8853783B2 (en) 2014-10-07
SG192335A1 (en) 2013-08-30
DE102013200649A1 (en) 2013-07-25
DE102013200649B4 (en) 2019-10-31
US20130187218A1 (en) 2013-07-25
CN103219362B (en) 2015-12-23
CN103219362A (en) 2013-07-24
TW201338125A (en) 2013-09-16
KR20130085355A (en) 2013-07-29

Similar Documents

Publication Publication Date Title
TWI549253B (en) Esd protection circuit
TWI515862B (en) Esd protection circuit
EP2680312B1 (en) High breakdown voltage LDMOS device
US9590097B2 (en) Semiconductor devices and related fabrication methods
US20170062406A1 (en) Electrostatic discharge protection device and electronic device having the same
TWI525793B (en) Esd protection circuit
JP2008147415A (en) Semiconductor device and its manufacturing method
US8823097B2 (en) Protection device with a thin-film resistance connected to plural drain regions
US9306057B2 (en) Metal oxide semiconductor devices and fabrication methods
US10930776B2 (en) High voltage LDMOS transistor and methods for manufacturing the same
CN103811485B (en) Esd protection circuit
CN104867971B (en) Semiconductor element and its operating method
US9564436B2 (en) Semiconductor device
US10249614B2 (en) Semiconductor device
US8878297B2 (en) ESD protection circuit
TWI782335B (en) Semiconductor device and method of forming the same
JP2010016284A (en) Semiconductor device
JP6188205B2 (en) Bipolar transistor with high breakdown voltage
TWI798825B (en) Manufacturing method of semiconductor device
Liaw et al. P-Channel Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance
TWI394277B (en) Lateral diffused metal-oxide semiconductor