JP2008078469A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor capable of reducing a drain capacitance per unit gate width. <P>SOLUTION: A rectangular annular gate electrode 21(G) having four sides is formed in a first conductivity type first semiconductor region 14 having a channel formation region, a drain region 18D(D) is formed on the inner side of the gate electrode, a source region 18S(S) is formed with such a width that the channel width of a corresponding drain region is not narrowed in each region on the outer side of the four sides, that is, the gate electrode is formed on all the four sides of the drain region in a rectangular shape for transistor formation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor, and more particularly to a depletion type n-channel MOS field effect transistor used for a protection circuit against electrostatic breakdown of a magnetic head.

  For example, in a magnetic head such as a GMR magnetic head incorporated in a magnetic recording apparatus such as an HDD (Hard Disk Drive), a depletion type n is included in a preamplifier IC that drives the head as a protection circuit for protecting the magnetic head from electrostatic breakdown. A channel MOS field effect transistor is used.

FIG. 8A is a plan view of a depletion-type n-channel MOS field effect transistor according to a conventional example.
For example, a gate electrode 41 is formed on a p-type semiconductor region provided on a semiconductor substrate via a gate insulating film, and an n-type source is formed on the surface layer portion of the p-type semiconductor region on both sides of the gate electrode 41. A region 40S and a drain region 40D are formed.
Further, an n-type channel region is formed in the surface layer portion of the p-type semiconductor region immediately below the gate electrode 41, thereby forming a depletion-type n-channel MOS field effect transistor.

For example, as HDDs increase in speed and capacity, there is a need for a depletion type n-channel field effect transistor having a lower capacity and a lower on-resistance in order to improve the performance as an ESD protection element.
In order to realize the above, reduction of on-resistance, reduction of drain capacitance, and the like are required. For example, a technique of reducing on-resistance without increasing the drain capacitance is used.

FIG. 8B is a plan view of a depletion type n-channel MOS field effect transistor according to a conventional example.
For example, two gate electrodes (41a, 41b) are formed on a p-type semiconductor region provided on a semiconductor substrate via a gate insulating film, and 3 separated by the two gate electrodes (41a, 41b). A source region 40Sa, a drain region 40D, and a source region 40Sb are formed in the surface layer portion of the p-type semiconductor region in one region.
An n-type channel region is formed in the surface layer portion of the p-type semiconductor region immediately below the two gate electrodes (41a, 41b), thereby forming a depletion-type n-channel MOS field effect transistor.

  The field effect transistor having the configuration shown in FIG. 8B has a gate width approximately twice that of the field effect transistor having the configuration shown in FIG. The resistance is reduced by about half. That is, the drain capacity per unit gate width is reduced to about half.

  However, in recent years, further drive speeding has been demanded, and further reduction of on-resistance and drain capacity has been demanded.

  The present invention has been made in view of the above situation, and an object of the present invention is to provide a field effect transistor capable of reducing the drain capacitance per unit gate width.

  In order to achieve the above object, a field effect transistor of the present invention includes a first conductivity type first semiconductor region having a channel formation region, and a gate insulating film above the channel formation region of the first semiconductor region. A gate electrode formed in a rectangular ring pattern having four sides, a drain region of a second conductivity type formed in a surface layer portion of the first semiconductor region in a region inside the gate electrode, and Each of the regions outside the four sides of the gate electrode is formed in the surface layer portion of the first semiconductor region with a width that does not narrow the channel width of the corresponding drain region when viewed from each region outside the gate electrode. And a second conductivity type source region.

In the above-described field effect transistor of the present invention, a rectangular gate electrode having four sides is formed in a first conductivity type first semiconductor region having a channel formation region, and a drain region is formed inside the gate electrode. In each of the regions outside the four sides, a source region is formed with a width that does not narrow the channel width of the corresponding drain region.
That is, a gate electrode is formed on all four sides of the rectangular drain region to constitute a transistor.

  In the field effect transistor of the present invention, preferably, the rectangular gate electrode is two-dimensionally repeated and formed in a lattice shape, and a region inside the lattice is formed with respect to one lattice. One of the drain region and the source region corresponds to each other, and the drain region and the source region are alternately and repeatedly formed two-dimensionally.

In the field effect transistor of the present invention, preferably, a back gate is formed inside the first semiconductor region.
More preferably, the back gate and the source region are connected and a common potential is applied.

  The field effect transistor of the present invention is preferably an n-channel field effect transistor in which the first conductivity type is p-type and the second conductivity type is n-type.

The field effect transistor of the present invention is preferably a depletion type in which a channel region of the second conductivity type is formed in the surface layer portion of the first semiconductor region in the channel formation region.
More preferably, As is implanted as a conductive impurity in the channel region of the second conductivity type.

  The field effect transistor according to the present invention is preferably used as a switch for protecting the magnetic head from electrostatic breakdown in an electrostatic breakdown protection circuit of the magnetic head.

  According to the field effect transistor of the present invention, a gate electrode is formed on all four sides of a rectangular drain region, which is compared with a field effect transistor having the same drain region area and only a gate electrode length of one side. Then, the on-resistance can be reduced to ¼ even with the same drain capacitance, that is, the drain capacitance per unit gate width can be reduced to ¼.

  Embodiments of a field effect transistor according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1A is a plan view of a field effect transistor according to this embodiment, and FIG. 1B is a cross-sectional view taken along the line ABC in FIG.
For example, a first n-type semiconductor layer (n-type tank) 11 is formed on a p-type silicon substrate (p-sub) 10, and a second n-type semiconductor layer 12 is formed on the entire surface layer portion.

For example, a p-type well (first conductivity type first semiconductor region) 14 having a channel formation region in an element formation region from the surface formed by stacking the first n-type semiconductor layer 11 and the second n-type semiconductor layer 12 is formed. A p ⁺ type buried layer 13 serving as a back gate is formed at a depth near the boundary between the first n type semiconductor layer 11 and the second n type semiconductor layer 12 on the bottom surface of the p type well 14. .
Further, for example, an element isolation insulating film 15 (I) is formed in a predetermined pattern on the surface of the p-type well 14 to isolate the elements. The element isolation insulating film 15 (I) is formed by, for example, a LOCOS (local oxidation of silicon) method or an STI (shallow trench isolation) method, and the insulating film by the LOCOS method is shown in the drawing.

  For example, a gate electrode 21 (G) made of polysilicon is formed in a rectangular ring pattern having four sides on the p-type well 14 having a channel formation region via a gate insulating film 20 made of silicon oxide. Is formed. For example, sidewall insulating films 22 made of silicon oxide or the like are formed on both sides of the gate electrode 21 (G).

Further, for example, the n ⁺ -type source region 18S (S) and the drain region 18D (D) containing n-type conductive impurities at a high concentration in the surface layer portion of the p-type well 14 on both sides of the sidewall insulating film 22. ) Is formed.
Here, as shown in FIG. 1A, the gate electrode 21 (G) is formed in a rectangular ring shape, and the drain region 18D (D) is formed in the inner region, while the gate electrode 21 ( In each of the regions outside the four sides of G), the source region 18S (S) is formed with a width that does not reduce the channel width of the corresponding drain region 18D (D) when viewed from each of the outer regions. Has been.

  Further, for example, the surface layer portion of the p-type well 14 below the sidewall insulating film 22 is formed shallower than the source region 18D and the drain region 18D, and includes LDD (lightly doped) containing an n-type conductive impurity at a low concentration. drain) region 17 is formed, and so-called LDD type source and drain regions are formed.

Further, for example, an n-type channel region 16 containing an n-type conductive impurity such as As is formed in the surface layer portion of the p-type well 14 serving as a channel formation region under the gate electrode 21 (G). Yes. For example, it is a shallow region in which As is introduced at a high concentration, which can reduce off-state current and on-resistance.
As described above, a depletion type n-channel MOS field effect transistor is configured.

Further, for example, a p ⁺ type buried layer containing a high concentration of p type conductive impurities in the surface layer portion of the p type well 14 in the vicinity of the corner of the rectangular ring-shaped gate electrode 21 (G) and serving as a back gate. A p ⁺ -type back gate region 18BG (BG) electrically connected to 13 is formed.

  Although the back gate region 18BG (BG) is separated from the source region 18S (S) by the element isolation insulating film 15 (I), the boundary region between the back gate region 18BG (BG) and the source region 18S (S) The rectangular ring-shaped gate electrode 21 (G) may be extended to the above. In this case, the gate electrode 21 (G) has a lattice shape.

  Further, for example, an interlayer insulating film 23 made of silicon oxide is formed so as to cover the field effect transistor, and the source region 18S (S), the drain region 18D (D), and the back gate region 18BG (BG) are formed. Reaching openings (24S, 24D, 24BG) connected to the source region 18S (S), the drain region 18D (D), and the back gate region 18BG (BG) are formed integrally with the plug embedded in the opening. ) Is formed.

  According to the depletion-type n-channel MOS field effect transistor of the present embodiment, the gate electrode is formed on all four sides of the rectangular drain region, and the drain region has the same area and the length of one side. Compared with a field effect transistor having only one gate electrode, the on-resistance can be reduced to ¼ even with the same drain capacitance, that is, the drain capacitance per unit gate width can be reduced to ¼.

In the field effect transistor of the present embodiment configured as described above, for example, wirings (24S, 24BG) are connected, the back gate region 18BG (BG) and the source region 18S (S) are connected, and a common potential is applied.
Further, for example, the field effect transistor of this embodiment is used as a switch for protecting the magnetic head from electrostatic breakdown in an electrostatic breakdown protection circuit of the magnetic head.

Second Embodiment FIG. 2 is a plan view of a field effect transistor according to this embodiment.
For example, a rectangular gate electrode according to the first embodiment is a two-dimensionally repeated gate electrode G formed in a lattice shape.
In addition, for example, the drain region D and the source region S are alternately and two-dimensionally repeated with one of the drain region and the source region corresponding to one lattice in the region inside the lattice. ing.
As described above, the drain region D and the source region S are formed in a so-called checkered layout.

Here, the drain region D is not disposed on the outermost periphery, that is, the source region S is formed at positions corresponding to the four sides of the rectangular drain region, and the back gate region BG is laid out between them.
As described above, since the transistor cannot be configured with four sides as the drain region in the outermost periphery, the outermost region is preferably the source region or the back gate region, but the transistor cannot be configured with four sides in this portion. If this is not a problem, the drain region can be arranged on the outermost periphery.

  In the above configuration, the gate electrode is arranged so as to surround all the regions including the source region S and the back gate region BG in the outermost peripheral part in consideration of the ease of taking out the gate electrode. Alternatively, the gate electrode between the source region S and the back gate region BG may be deleted, and the back gate region BG and the source region S may be separated by the element isolation insulating film I.

FIG. 3A is a cross-sectional view taken along the line XX ′ in FIG.
Similar to the first embodiment, for example, a first n-type semiconductor layer 11 is formed on a p-type silicon substrate 10 and a p-type well (first conductivity type first semiconductor region) 14 having a channel formation region and a back surface are formed. A p ⁺ type buried layer 13 to be a gate is formed.
Further, for example, a gate electrode 21 (G) made of polysilicon is formed in a lattice pattern on the p-type well 14 having a channel formation region via a gate insulating film 20 made of silicon oxide, and the gate Sidewall insulating films 22 made of silicon oxide or the like are formed on both sides of the electrode 21.

Further, for example, n ⁺ -type source regions 18S and drain regions 18D are alternately formed in a region inside the lattice, and the source regions are arranged on the outermost periphery.
Further, for example, an LDD region 17 is formed in the surface layer portion of the p-type well 14 below the sidewall insulating film 22.
Further, for example, an n-type channel region 16 containing an n-type conductive impurity such as As is formed in the surface layer portion of the p-type well 14 serving as a channel formation region under the gate electrode 21.

FIG. 3B is a cross-sectional view taken along line YY ′ in FIG.
Is basically FIG. 3 (A) similar to configuration, the outermost, p ⁺ -type back gate region 18BG is arranged to electrically connect to the p ⁺ -type buried layer 13 serving as a back gate, the In the inner region, the source region 18S and the drain region 18D are formed alternately and repeatedly.

  In the above configuration, the gate electrode 21 (G) has a lattice shape, and the rectangular annular gate electrode 21 (G) extends to the boundary region between the back gate region 18BG (BG) and the source region 18S (S). However, the back gate region 18BG (BG) and the source region 18S (S) may be separated by the element isolation insulating film 15 (I).

  Each of the plurality of source regions 18S and drain regions 18D as described above is connected to one system by wirings to be described later, and the back gate region 18BG is connected to the source region 18S.

FIG. 4 is a plan view showing the layout of the first layer wiring connected to the source region, drain region, and back gate region of the field effect transistor according to the present embodiment.
Upper wirings (24S, 24D, 24BG) are formed through contacts CT for the source region S, the drain region D, and the back gate region BG.
Since the source regions S are connected together in one system by the wiring 24S and the wiring 24BG is connected to the wiring 24S, the source region S is connected together in one system together with the back gate region BG.
On the other hand, the drain region D is divided into portions connectable between the wirings 24S, and is divided into five systems in the drawing and connected to the wirings 24D.

FIG. 5 shows the first layer wiring connected to the source region and back gate region of the field effect transistor according to the present embodiment, and the first layer wiring connected to the drain region. It is a top view which shows the layout of two-layer wiring.
By the second layer wiring 25D, the first layer wirings 24D divided into a plurality of (five systems on the drawing) are connected together in one system.
Further, although the wiring 24S (wiring 24BG) is already connected to one system, the wiring resistance is reduced by the second-layer wiring 25S so that the wiring 24S is connected to the one system.
Further, for example, the second wiring (25S, 25D) may be formed in a region other than the above in order to reduce the wiring resistance.

  In the above configuration, the source region and the drain region are divided into a plurality of so-called checkered patterns and are laid out, and gate electrodes are arranged at the lattice boundary portions of the respective source regions and drain regions. Although a field effect transistor is configured for each of the source region and the drain region adjacent to each other via the gate electrode, each source region and the drain region are combined into one system, so that one depletion type as a whole. The n-channel MOS field effect transistor is constructed.

  According to the above-described depletion type n-channel MOS field effect transistor of the present embodiment, the gate width of the transistor is markedly greater than that of a field effect transistor having the same drain region area but having only one drain region. This corresponds to the expanded one, and thus the on-resistance can be reduced while maintaining the same drain capacitance, that is, the drain capacitance per unit gate width can be reduced.

Third Embodiment In the field effect transistors of the first and second embodiments described above, the back gate region is separated from the source region by an element isolation insulating film, or the back gate region and the source region are separated from each other. When the gate electrode is formed up to the boundary region and the source region and the back gate region are connected by the upper wiring, but it is assumed that the source region and the back gate region are connected There is no need to separate the source region and the back gate region into individual regions by an element isolation insulating film or the like.
In the field effect transistor of this embodiment, the source region and the back gate region are arranged adjacent to each other without being separated by an element isolation insulating film or the like.

FIG. 6A is a partial cross-sectional view of an example of a field effect transistor according to this embodiment.
For example, as in FIG. 3A, a lattice-like gate electrode 21 is formed, and n ⁺ -type source regions 18S and drain regions 18D are alternately and repeatedly formed in regions inside each lattice. The source region 18S is arranged on the outermost periphery.
In this embodiment, the p ⁺ -type back gate region 18BG is arranged adjacent to the outermost peripheral source region 18S without being separated by an element isolation insulating film or the like. In this case, the source region 18S and the back gate region 18BG may be connected to the upper layer wiring through a common contact.
The source region 18S and the back gate region 18BG that are arranged adjacent to each other without being separated by the element isolation insulating film as described above are, for example, openings of a mask for ion-implanting n-type impurities for forming the source region 18S. And the opening of a mask for ion implantation of a p-type impurity for forming the back gate region 18BG are adjacent to each other, that is, each impurity is ion-implanted into the adjacent region. .

FIG. 6B is a partial cross-sectional view of another example of the field effect transistor according to the present embodiment.
For example, as in FIG. 3A, in a configuration in which n ⁺ -type source regions 18S and drain regions 18D are alternately formed, the source region 18S in the region sandwiched between the drain regions 18D is formed. The p ⁺ -type back gate region 18BG is disposed adjacent to the inner region of the source region 18S without being separated by an element isolation insulating film or the like.
Similarly to the above, the source region 18S and the back gate region 18BG can be connected by a common contact, and this structure is formed by ion-implanting respective impurities into adjacent regions. It is possible.

The configuration of this embodiment can be applied to each of the above embodiments.
According to the field effect transistor of the present embodiment, as in the above embodiments, the on-resistance can be reduced while having the same drain capacitance, that is, the drain capacitance per unit gate width can be reduced. it can. Further, since the back gate region for connecting to the back gate can be laid out adjacent to the source region, it contributes to reducing the area of the element.

Fourth Embodiment FIG. 7 is a circuit diagram showing a protection circuit for protecting a magnetic head from electrostatic breakdown (ESD) in a magnetic head such as a GMR magnetic head incorporated in a magnetic recording apparatus.
As the switch element in the protection circuit, the field effect transistor of each of the above embodiments can be used.

For example, a magnetic head 30 such as a GMR magnetic head is connected to a preamplifier 32 via a line 31a and a line 31b.
Here, field effect transistors 33 and 34 as ESD protection circuits are connected to the line 31a and the line 31b, respectively.

Here, the ESD protection circuit is composed of the depletion-type n-channel field effect transistor of each of the embodiments described above, the drain region is connected to the line 31a and the line 31b, respectively, and the source region is the reference potential. (For example, ground).
Since the ESD protection circuit conducts only when an excessive voltage is applied to the lines 31a and 31b and releases the excessive voltage to the reference potential, the gate terminals of the depletion type field effect transistors 33 and 34 A negative potential is applied to 33a and 34a so that the transistors 33 and 34 are non-conductive in a steady state.
A bias current is supplied to the magnetic head 30 through the path of the positive power source, the line 31a, the magnetic head 30, the line 31b, and the negative power source. At this time, the voltage of the positive power supply is about +3 to + 5V, and the voltage of the negative power supply is about −2 to −5V. In this case, the gate electrodes 33a and 34a of the field effect transistors 33 and 34 may be connected to a negative power source. Further, a voltage difference of about 100 mV is generated between the line 31a and the line 31b, that is, at both ends of the magnetic head 30.
Although the preamplifier 32 and the field effect transistors 33 and 34 can be formed in one semiconductor integrated circuit (IC), the magnetic head 30 is externally attached to the semiconductor integrated circuit.

  In addition to the above, depending on the element or circuit to be protected, the timing to be protected, etc., the field effect transistor constituting the ESD protection circuit is classified into a depletion type / enhancement type, or an n channel type / p channel type. Can be selected as appropriate.

The present invention is not limited to the above description.
For example, a silicide layer may be formed on part or all of the surfaces of the source region, the drain region, the back gate region, and the gate electrode. For example, it can be formed on the entire upper surface of the source region, drain region, back gate region, and gate electrode by a salicide process or the like.
Although the depletion type field effect transistor has been described in the above embodiment, it can be applied to an enhancement type by not forming a channel region.
Further, although an n-channel field effect transistor is described, the present invention can also be applied to a p-channel field effect transistor.
In addition, various modifications can be made without departing from the scope of the present invention.

  The field effect transistor of the present invention can be applied as a switch transistor that constitutes a protection circuit against electrostatic breakdown in a magnetic head such as a GMR magnetic head.

FIG. 1A is a plan view of the field effect transistor according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line ABC in FIG. FIG. 2 is a plan view of a field effect transistor according to a second embodiment of the present invention. 3A is a cross-sectional view taken along line X-X ′ in FIG. 2, and FIG. 3B is a cross-sectional view taken along line Y-Y ′ in FIG. 2. FIG. 4 is a plan view showing the layout of the first layer wiring connected to the source region, drain region and back gate region of the field effect transistor according to the second embodiment of the present invention. FIG. 5 illustrates a connection of the first layer wiring connected to the source region and the back gate region and the first layer wiring connected to the drain region of the field effect transistor according to the second embodiment of the present invention. It is a top view which shows the layout of the wiring of the 2nd layer formed. FIG. 6A is a partial cross-sectional view of an example of a field effect transistor according to the third embodiment of the present invention, and FIG. 6B is a partial cross-sectional view of another example. FIG. 7 is a circuit diagram showing a protection circuit for protecting a magnetic head from electrostatic breakdown (ESD) in a magnetic head such as a GMR magnetic head incorporated in a magnetic recording apparatus. FIGS. 8A and 8B are plan views of a depletion type n-channel MOS field effect transistor according to a conventional example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... p-type silicon substrate, 11 ... 1st n-type semiconductor layer, 12 ... 2n-type semiconductor layer, 13 ... p ⁺ type buried layer, 14 ... p-type well (first conductivity type first semiconductor region), 15 ... Element isolation insulating film, 16 ... channel region, 17 ... LDD region, 18S ... source region, 18D ... drain region, 18BG ... back gate region, 20 ... gate insulating film, 21 ... gate electrode, 22 ... sidewall insulating film, 23 ... Interlayer insulating film, 24S, 24D, 24BG ... wiring, 25S, 25D ... second wiring, 30 ... magnetic head, 31a ... line, 31b ... line, 32 ... preamplifier, 33, 34 ... field effect transistor, 40S, 40Sa , 40Sb ... source region, 40D ... drain region, 33a, 34b, 41, 41a, 41b ... gate electrode, S ... source region, D ... drain region, BG ... back gate region, G ... gate electrode, I ... element isolation insulating film, CT ... contact

Claims (14)

A first semiconductor region of a first conductivity type having a channel formation region;
A gate electrode formed in a rectangular ring pattern having four sides through a gate insulating film in an upper layer of the channel formation region of the first semiconductor region;
A drain region of a second conductivity type formed in a surface layer portion of the first semiconductor region in a region inside the gate electrode;
Each of the outer regions of the four sides of the gate electrode has a width that does not reduce the channel width of the corresponding drain region when viewed from the outer regions, and is formed on the surface layer portion of the first semiconductor region. A field effect transistor having a source region of the second conductivity type formed. The rectangular gate electrode is two-dimensionally repeated and formed in a lattice shape,
One of the drain region and the source region corresponds to one region of the lattice, and the drain region and the source region are alternately and two-dimensionally repeated. The field effect transistor according to claim 1. The field effect transistor according to claim 1, wherein a back gate is formed inside the first semiconductor region. The field effect transistor according to claim 3, wherein the back gate and the source region are connected and a common potential is applied. The field effect transistor according to claim 1, wherein the first conductivity type is p-type, the second conductivity type is n-type, and an n-channel field-effect transistor. The field effect transistor according to claim 1, wherein a channel region of a second conductivity type is formed in a surface layer portion of the first semiconductor region in the channel formation region, and is a depletion type. The field effect transistor according to claim 6, wherein As is implanted as a conductive impurity in the channel region of the second conductivity type. The field effect transistor according to claim 1, wherein the field effect transistor is used as a switch for protecting the magnetic head from electrostatic breakdown in an electrostatic breakdown protection circuit of the magnetic head. A first semiconductor layer of a first conductivity type formed on a semiconductor substrate;
A rectangular drain region of a second conductivity type formed on the main surface of the first semiconductor layer;
A plurality of second conductivity type source regions respectively formed on the main surface of the first semiconductor layer at a predetermined interval with respect to the drain region;
It is located on the channel region of the first semiconductor layer located between the drain region and the plurality of source regions, and is formed on the first semiconductor layer so as to surround the drain region via an insulating layer. A grid-shaped gate electrode,
Have
A field effect transistor, wherein the plurality of source regions are respectively arranged at positions facing side portions of the drain region, and the plurality of source regions are electrically connected to each other. The drain region, the plurality of source regions, and the gate electrode are formed in a repeating pattern,
The drain regions formed in a repeating pattern are electrically connected to each other;
The field effect transistor according to claim 9, wherein the plurality of source regions formed in a repetitive pattern are electrically connected to each other. A back gate region of the first conductivity type formed on the main surface of the first semiconductor layer;
The field effect transistor according to claim 9 or 10, wherein the plurality of source regions and the back gate region are electrically connected. The field effect transistor according to any one of claims 9 to 11, wherein the channel region is a depletion type transistor including a first conductivity type semiconductor region formed on a main surface of the first semiconductor layer. The field effect transistor according to claim 12, wherein the first conductivity type is p-type, and the second conductivity type is n-type. A field effect transistor that functions as an ESD protection circuit connected between a signal line to which a magnetic head is connected and a reference potential, and a voltage is applied to the gate terminal so that the transistor becomes non-conductive in a steady state. The field effect transistor according to claim 9.

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