JPH0697380A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0697380A
JPH0697380A JP4246143A JP24614392A JPH0697380A JP H0697380 A JPH0697380 A JP H0697380A JP 4246143 A JP4246143 A JP 4246143A JP 24614392 A JP24614392 A JP 24614392A JP H0697380 A JPH0697380 A JP H0697380A
Authority
JP
Japan
Prior art keywords
dmos
circuit
power supply
semiconductor device
electrostatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4246143A
Other languages
Japanese (ja)
Inventor
Shoji Sato
照二 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4246143A priority Critical patent/JPH0697380A/en
Publication of JPH0697380A publication Critical patent/JPH0697380A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To pass an electrostatic breakdown pulse to the power supply side having lower impedance by providing a conduction DMOS at an I/O circuit section thereby short-circuiting I/O terminal and a power supply. CONSTITUTION:An I/O terminal 1, a protective element 2, and other circuits 3-6 are formed on a semiconductor substrate. The protective element 2 is constituted of a P-type DMOS 2a and an N-type DMOS 2b. When a semiconductor device is not fed with power, DMOSs are conducting to short-circuit between the I/O terminal 1 and the power supply side. Consequently, an electrostatic pulse applied on the I/O terminal 1 passes through a DMOS having lower impedance and flows into the power supply thus suppressing damage of internal circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体により構成され
るIC,LSI等の半導体装置に関し、静電破壊耐量の
向上に有効な発明に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC or an LSI composed of a semiconductor, and more particularly to an invention effective for improving electrostatic breakdown resistance.

【0002】[0002]

【従来の技術】従来の静電破壊保護回路を図2に示す。
従来回路では、入出力端子1に印加された高電圧の電気
パルス(静電気パルス)は、アルミ寄生MOS7やクラ
ンプMOS8を介して電源側(VCC,GND)に流
れ、内部回路のゲート酸化膜等に、静電気パルスが直接
達するのを防ぐ様にしている。
2. Description of the Related Art A conventional electrostatic breakdown protection circuit is shown in FIG.
In the conventional circuit, the high-voltage electric pulse (electrostatic pulse) applied to the input / output terminal 1 flows to the power supply side (VCC, GND) via the aluminum parasitic MOS 7 and the clamp MOS 8 and is applied to the gate oxide film of the internal circuit. , It is designed to prevent the electrostatic pulse from reaching directly.

【0003】ただし、アルミ寄生MOSやクランプMO
Sは、導通する電圧が高いため、静電気パルスが印加さ
れてから、電源側に流れ込むまで、時間遅れがある。
However, aluminum parasitic MOS and clamp MO
Since S has a high conducting voltage, there is a time delay from the application of the electrostatic pulse to the flow into the power supply side.

【0004】このため、印加パルスが内部回路に到達し
て、ゲート酸化膜や接合が破壊されたり、ダメージを受
ける可能性が高いという問題がある。
Therefore, there is a high possibility that the applied pulse reaches the internal circuit and the gate oxide film and the junction are destroyed or damaged.

【0005】[0005]

【発明が解決しようとする課題】このように従来の半導
体装置は、静電破壊保護用のアルミ寄生MOSやクラン
プMOSが導通状態に達するまでに、静電気パルスによ
り内部回路がダメージを受け、静電破壊耐量が低下する
可能性があった。
As described above, in the conventional semiconductor device, the internal circuit is damaged by the electrostatic pulse before the aluminum parasitic MOS for electrostatic breakdown protection and the clamp MOS reach the conductive state, and electrostatic discharge occurs. There is a possibility that the fracture resistance will decrease.

【0006】本発明によれば、入出力回路部に設けたD
MOSを介して、静電気パルスが電源側に流れ込むが、
半導体装置に電源を供給していない状態(半導体装置を
搬送したり、他の装置に組み込む等、静電気パルスを受
けて、静電破壊を起こしやすい状態)では、DMOSが
導通し、入出力端子と電源側が短絡状態となっているた
め、静電気パルスがインピーダンスの低い電源側に流れ
込む。これにより、内部回路へのダメージを減少させ、
静電破壊耐量の向上を図るものである。
According to the present invention, the D provided in the input / output circuit section
An electrostatic pulse flows into the power supply side through the MOS,
When power is not being supplied to the semiconductor device (state in which the semiconductor device is transported or incorporated into another device, etc., is susceptible to electrostatic breakdown due to static electricity pulse), the DMOS conducts to connect to the input / output terminal. Since the power supply side is short-circuited, electrostatic pulses flow into the power supply side with low impedance. This reduces damage to internal circuits,
This is intended to improve the electrostatic breakdown resistance.

【0007】[0007]

【課題を解決するための手段】本発明の概要を、CMO
S(Complementary Metal Oxide Semiconducter)回路を
例に説明すれば下記の通りである。
SUMMARY OF THE INVENTION The outline of the present invention is described in CMO.
To describe S a (C omplementary M etal O xide S emiconducter) circuit as an example as follows.

【0008】入出力回路部に、導通状態にあるDMOS
を設ける事により、入出力端子と電源の間を短絡させ、
静電破壊パルスをインピーダンスの低い電源側に流れ込
ませることにより、内部回路へのダメージを減少させ、
静電破壊耐量の向上を図るものである。
The input / output circuit section has a conductive DMOS.
By providing a short circuit between the input and output terminals and the power supply,
By causing the electrostatic breakdown pulse to flow into the power supply side with low impedance, damage to the internal circuit is reduced,
This is intended to improve the electrostatic breakdown resistance.

【0009】[0009]

【作用】上記手段によれば、IC,LSI等の半導体装
置において、静電破壊耐量の向上が可能となる。
According to the above means, it is possible to improve the electrostatic breakdown resistance of a semiconductor device such as an IC or LSI.

【0010】[0010]

【実施例】図1には、本発明の半導体装置の一実施例で
あるDMOSを設けた静電破壊保護回路を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an electrostatic breakdown protection circuit provided with a DMOS which is an embodiment of a semiconductor device of the present invention.

【0011】入出力端子1,保護素子2、およびその他
の回路(3〜6)は、特に制限されないが、公知の半導
体集積回路製造技術によって、シリコンのような1個の
半導体基板に形成される。
The input / output terminal 1, the protection element 2, and the other circuits (3 to 6) are not particularly limited, but are formed on one semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique. .

【0012】保護素子2は、P型DMOS 2a,N型
DMOS 2b、によって構成される。DMOSによる
保護回路を設けた場合、半導体装置に電源を供給してい
ない状態(半導体装置を搬送したり、他の装置に組み込
む等、静電気パルスを受けて、静電破壊を起こしやすい
状態)では、DMOSは、導通しているため、入出力端
子1と電源側が短絡した状態にある。このため、入出力
端子1に印加された静電気パルスは、インピーダンスの
低いDMOSを通じて、電源に流れ込み、内部回路への
ダメージは、図2に示した従来の保護回路より、減少す
る。
The protection element 2 is composed of a P-type DMOS 2a and an N-type DMOS 2b. When a protection circuit using a DMOS is provided, in a state where power is not supplied to the semiconductor device (state in which the semiconductor device is easily transported or incorporated into another device, an electrostatic pulse is likely to cause electrostatic breakdown), Since the DMOS is conducting, the input / output terminal 1 and the power supply side are short-circuited. Therefore, the electrostatic pulse applied to the input / output terminal 1 flows into the power source through the DMOS having a low impedance, and the damage to the internal circuit is reduced as compared with the conventional protection circuit shown in FIG.

【0013】DMOSを保護回路として設けた場合、半
導体装置が動作状態にある場合は、図1に示す保護素子
2のDMOSを非導通状態にし、入出力信号が、入出力
端子1と内部回路6の間で伝達される様にする必要があ
る。
When the DMOS is provided as the protection circuit and the semiconductor device is in the operating state, the DMOS of the protection element 2 shown in FIG. 1 is brought into the non-conducting state, and the input / output signal is changed to the input / output terminal 1 and the internal circuit 6. Need to be transmitted between.

【0014】保護素子2のDMOSを非導通状態にする
ため、発振回路3,負電位発生回路4,バックバイアス
電位制御回路5から成る回路にて、負電位を発生させ、
これを保護素子2のDMOSの基板に印加する。これに
より、DMOSのしきい値電圧を上昇させ、通常の入出
力信号の電位では、DMOSが導通しない様にし、入出
力信号の入出力端子1と内部回路6の間での伝達を可能
にする。
In order to make the DMOS of the protection element 2 non-conductive, a negative potential is generated in the circuit composed of the oscillation circuit 3, the negative potential generation circuit 4, and the back bias potential control circuit 5.
This is applied to the DMOS substrate of the protection element 2. As a result, the threshold voltage of the DMOS is raised so that the DMOS does not conduct at the potential of the normal input / output signal, and the input / output signal can be transmitted between the input / output terminal 1 and the internal circuit 6. .

【0015】[0015]

【発明の効果】本発明によって得られる効果を簡単に説
明すれば下記の通りである。すなわち、半導体装置にお
いて、入出力回路部に静電破壊保護素子としてのDMO
Sを設ける事により、静電気パルスに対する静電破壊耐
量を向上させる効果がある。
The effects obtained by the present invention will be briefly described as follows. That is, in a semiconductor device, a DMO as an electrostatic breakdown protection element is provided in an input / output circuit section.
Providing S has the effect of improving the electrostatic breakdown withstand capability against electrostatic pulses.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る半導体装置、すなわち
本実施例では静電破壊の保護素子としてDMOSを設け
た場合の回路図である。
FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, that is, a case where a DMOS is provided as an electrostatic breakdown protection element in this embodiment.

【図2】従来の静電破壊保護回路図である。FIG. 2 is a conventional electrostatic breakdown protection circuit diagram.

【符号の説明】[Explanation of symbols]

1…入出力端子、2…保護素子、2a…P型DMOS,
2b…N型DMOS,3…発振回路、4…負電位発生回
路、4a…N型DMOS、4b…容量、4c…NOR回
路、4d…負電位発生点、5…バックバイアス電位制御
回路、5a…N型DMOS、5b…抵抗、6…内部回
路、7…アルミ寄生MOS、8…クランプMOS。
1 ... I / O terminal, 2 ... Protecting element, 2a ... P-type DMOS,
2b ... N-type DMOS, 3 ... Oscillation circuit, 4 ... Negative potential generation circuit, 4a ... N-type DMOS, 4b ... Capacitance, 4c ... NOR circuit, 4d ... Negative potential generation point, 5 ... Back bias potential control circuit, 5a ... N-type DMOS, 5b ... Resistor, 6 ... Internal circuit, 7 ... Aluminum parasitic MOS, 8 ... Clamp MOS.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】入出力回路部に、DMOS(デプレッショ
ン型MOSトランジスタ)を付加することを特徴とする
半導体装置。
1. A semiconductor device in which a DMOS (depletion type MOS transistor) is added to an input / output circuit section.
JP4246143A 1992-09-16 1992-09-16 Semiconductor device Pending JPH0697380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4246143A JPH0697380A (en) 1992-09-16 1992-09-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4246143A JPH0697380A (en) 1992-09-16 1992-09-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0697380A true JPH0697380A (en) 1994-04-08

Family

ID=17144128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4246143A Pending JPH0697380A (en) 1992-09-16 1992-09-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0697380A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078469A (en) * 2006-09-22 2008-04-03 Texas Instr Japan Ltd Field effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078469A (en) * 2006-09-22 2008-04-03 Texas Instr Japan Ltd Field effect transistor

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