JPH0697380A - Semiconductor device - Google Patents

Abstract

PURPOSE:To pass an electrostatic breakdown pulse to the power supply side having lower impedance by providing a conduction DMOS at an I/O circuit section thereby short-circuiting I/O terminal and a power supply. CONSTITUTION:An I/O terminal 1, a protective element 2, and other circuits 3-6 are formed on a semiconductor substrate. The protective element 2 is constituted of a P-type DMOS 2a and an N-type DMOS 2b. When a semiconductor device is not fed with power, DMOSs are conducting to short-circuit between the I/O terminal 1 and the power supply side. Consequently, an electrostatic pulse applied on the I/O terminal 1 passes through a DMOS having lower impedance and flows into the power supply thus suppressing damage of internal circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC or an LSI composed of a semiconductor, and more particularly to an invention effective for improving electrostatic breakdown resistance.

[0002]

2. Description of the Related Art A conventional electrostatic breakdown protection circuit is shown in FIG.
In the conventional circuit, the high-voltage electric pulse (electrostatic pulse) applied to the input / output terminal 1 flows to the power supply side (VCC, GND) via the aluminum parasitic MOS 7 and the clamp MOS 8 and is applied to the gate oxide film of the internal circuit. , It is designed to prevent the electrostatic pulse from reaching directly.

However, aluminum parasitic MOS and clamp MO
Since S has a high conducting voltage, there is a time delay from the application of the electrostatic pulse to the flow into the power supply side.

Therefore, there is a high possibility that the applied pulse reaches the internal circuit and the gate oxide film and the junction are destroyed or damaged.

[0005]

As described above, in the conventional semiconductor device, the internal circuit is damaged by the electrostatic pulse before the aluminum parasitic MOS for electrostatic breakdown protection and the clamp MOS reach the conductive state, and electrostatic discharge occurs. There is a possibility that the fracture resistance will decrease.

According to the present invention, the D provided in the input / output circuit section
An electrostatic pulse flows into the power supply side through the MOS,
When power is not being supplied to the semiconductor device (state in which the semiconductor device is transported or incorporated into another device, etc., is susceptible to electrostatic breakdown due to static electricity pulse), the DMOS conducts to connect to the input / output terminal. Since the power supply side is short-circuited, electrostatic pulses flow into the power supply side with low impedance. This reduces damage to internal circuits,
This is intended to improve the electrostatic breakdown resistance.

[0007]

SUMMARY OF THE INVENTION The outline of the present invention is described in CMO.
To describe S a (C omplementary M etal O xide S emiconducter) circuit as an example as follows.

The input / output circuit section has a conductive DMOS.
By providing a short circuit between the input and output terminals and the power supply,
By causing the electrostatic breakdown pulse to flow into the power supply side with low impedance, damage to the internal circuit is reduced,
This is intended to improve the electrostatic breakdown resistance.

[0009]

According to the above means, it is possible to improve the electrostatic breakdown resistance of a semiconductor device such as an IC or LSI.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an electrostatic breakdown protection circuit provided with a DMOS which is an embodiment of a semiconductor device of the present invention.

The input / output terminal 1, the protection element 2, and the other circuits (3 to 6) are not particularly limited, but are formed on one semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique. .

The protection element 2 is composed of a P-type DMOS 2a and an N-type DMOS 2b. When a protection circuit using a DMOS is provided, in a state where power is not supplied to the semiconductor device (state in which the semiconductor device is easily transported or incorporated into another device, an electrostatic pulse is likely to cause electrostatic breakdown), Since the DMOS is conducting, the input / output terminal 1 and the power supply side are short-circuited. Therefore, the electrostatic pulse applied to the input / output terminal 1 flows into the power source through the DMOS having a low impedance, and the damage to the internal circuit is reduced as compared with the conventional protection circuit shown in FIG.

When the DMOS is provided as the protection circuit and the semiconductor device is in the operating state, the DMOS of the protection element 2 shown in FIG. 1 is brought into the non-conducting state, and the input / output signal is changed to the input / output terminal 1 and the internal circuit 6. Need to be transmitted between.

In order to make the DMOS of the protection element 2 non-conductive, a negative potential is generated in the circuit composed of the oscillation circuit 3, the negative potential generation circuit 4, and the back bias potential control circuit 5.
This is applied to the DMOS substrate of the protection element 2. As a result, the threshold voltage of the DMOS is raised so that the DMOS does not conduct at the potential of the normal input / output signal, and the input / output signal can be transmitted between the input / output terminal 1 and the internal circuit 6. .

[0015]

The effects obtained by the present invention will be briefly described as follows. That is, in a semiconductor device, a DMO as an electrostatic breakdown protection element is provided in an input / output circuit section.
Providing S has the effect of improving the electrostatic breakdown withstand capability against electrostatic pulses.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, that is, a case where a DMOS is provided as an electrostatic breakdown protection element in this embodiment.

FIG. 2 is a conventional electrostatic breakdown protection circuit diagram.

[Explanation of symbols]

1 ... I / O terminal, 2 ... Protecting element, 2a ... P-type DMOS,
2b ... N-type DMOS, 3 ... Oscillation circuit, 4 ... Negative potential generation circuit, 4a ... N-type DMOS, 4b ... Capacitance, 4c ... NOR circuit, 4d ... Negative potential generation point, 5 ... Back bias potential control circuit, 5a ... N-type DMOS, 5b ... Resistor, 6 ... Internal circuit, 7 ... Aluminum parasitic MOS, 8 ... Clamp MOS.

Claims (1)

[Claims] 1. A semiconductor device in which a DMOS (depletion type MOS transistor) is added to an input / output circuit section.