1260762 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關一種靜電放電保護裝置（ESD Protection Device )的製造方法，特別是關於一種用於 月f電放電保邊電路之閘極—接地電晶體（g a t e _ g r 〇 u n d μ 〇 s )的製造方法。 【先前技術】 按’在目前的深次微米元件中，ggN/PM〇s元件係被廣 泛應用於靜電放電保護的裝置元件，ggN/pM〇S主要特徵係 在於其寄生雙極電晶體（Blpolar)元件特性，當一瞬間 向電壓發生時’其寄生雙極電晶體將被觸發而適當的引導 其间電壓所產生的高電流至vss或Vdd端。 應用ggN/PMOS元件於積體電路中作為靜電放電保護裝 置1 0之電路結構如第一圖所示，瞬間正向高電壓會啟動 NM0S 12之寄生雙極元件，使高電流導引至Vss端；瞬間反 向高電壓則啟動PM0S 14中之寄生雙極元件，使高電流導 引Vdd。此種應用原理係如第二圖所示，當一靜電放電事 件赍生在一輸入端之腳位（Pad )時，此將被觸 發（trigger)，並進入驟轉區域regi〇n)， 在此驟轉區域中，此ggN/PM〇s將夾持橫跨其本身之一低電 位電壓並維持-高電流，使此靜電放電電流可有效地導引 一當如ggNMOS元件應用於靜電放電保護裝置之結構如第 -二所不：此結構係應用在非自行對準金屬石夕化物（ ahcMde )的製程中時，其汲極接觸（drain c〇ntact )1260762 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of manufacturing an ESD protection device, and more particularly to a gate for a monthly f-electrode-distribution circuit. A method of manufacturing a grounded transistor (gate _ gr 〇und μ 〇s ). [Prior Art] According to 'in the current deep sub-micron components, ggN/PM〇s components are widely used in device components for electrostatic discharge protection. The main feature of ggN/pM〇S is its parasitic bipolar transistor (Blpolar). The component characteristics, when a voltage is generated instantaneously, its parasitic bipolar transistor will be triggered to properly direct the high current generated by the voltage between them to the vss or Vdd terminal. The ggN/PMOS device is used in the integrated circuit as the electrostatic discharge protection device. The circuit structure of the electrostatic discharge protection device 10 is as shown in the first figure. The instantaneous high voltage will activate the parasitic bipolar component of the NM0S 12 to direct the high current to the Vss terminal. The instantaneous reverse high voltage activates the parasitic bipolar element in PM0S 14 to direct the high current to Vdd. This application principle is as shown in the second figure. When an electrostatic discharge event is generated at the input terminal (Pad), this will be triggered and enter the jump region regi〇n). In this revolving region, the ggN/PM〇s will clamp a low potential voltage across itself and maintain a high current, so that the ESD current can be effectively guided when a ggNMOS component is applied to ESD protection. The structure of the device is as follows: - This structure is applied to the process of non-self-aligned metal lithium (ahcMde), its drain contact (drain c〇ntact)
第5頁 1260762 五、發明說明（2) 1 6至多晶石夕閘極（p 0 1 y g a t e ) 1 8之間有一緩衝距離充當 電阻緩衝區（Resistance Ballast)效用，使NPN電晶體 2 〇被觸發時，其高電流可相對均句（h 〇 m 〇 g e n e 〇 u s )的排 除掉。 然於深次微米的製程中，自行對準金屬矽化物2 2係應 用於包含靜電放電（ESD )結構内的多晶矽閘極1 8與源/汲 極區域2 4、1 6，如第四圖所示，此舉將造成汲極接觸1 6與 多晶矽閘極1 8之間幾乎沒有一點電阻緩衝區。當一靜電高 電壓產生，造成ESD結構中之寄生NPN (或PNP )電晶體被 觸發時，高電壓所產生的電流雖可排掉，然NPN電晶體之 集極N (Collector N，相當於ggNMOS中之汲極）沒有電阻 緩衝區’再加上其為淺接面（s h a 1 1 〇 w j u n c t i ο η )的結構 ’尚電流的流動將會不均勻（i n h 〇 m o g e n e o u s )，造成沒 極附近有局部高電流及局部加熱現象產生，導致ES])結構 潛在破壞’進而喪失靜電放電保護之功效者。 因此’本發明係在針對上述之困擾，提出一種靜電放 電保護裝置之電晶體製造方法，以有效解決前述之該等缺 失。 【發明内容】 本發明之主要目的係在提供一種靜電放電保護裝置之 電晶體製造方法，其係利用似反植入（r e t r 〇 g r a d e - 1 i k e implantation )的方式在汲極區域了方形成一延伸的自行 對準金屬矽化物阻隔區，以作為汲極接觸與多晶矽閘極之 間的電阻緩衝區，使靜電放電產生之高電流能夠有一較均Page 5 1206762 V. INSTRUCTIONS (2) 1 6 to polycrystalline slab gate (p 0 1 ygate ) 1 8 has a buffer distance acting as a resistance buffer (Resistance Ballast) effect, so that NPN transistor 2 〇 is triggered At this time, its high current can be excluded from the relative sentence (h 〇m 〇gene 〇us ). However, in the deep submicron process, the self-aligned metal telluride 2 2 is applied to the polysilicon gate 18 and the source/drain region 24, 16 in the electrostatic discharge (ESD) structure, as shown in the fourth figure. As shown, this will result in almost no resistance buffer between the drain contact 16 and the polysilicon gate 18. When a high voltage of static electricity is generated, causing the parasitic NPN (or PNP) transistor in the ESD structure to be triggered, the current generated by the high voltage can be drained, but the collector N of the NPN transistor (corresponding to ggNMOS) In the middle of the bungee, there is no resistance buffer 'plus the structure of the shallow junction (sha 1 1 〇wjuncti ο η )', the flow of current will be uneven (inh 〇mogeneous), causing locality near the pole High current and localized heating phenomena result in potential damage to the structure of ES]) and thus the effect of electrostatic discharge protection. Therefore, the present invention has been made in view of the above problems, and proposes a method of manufacturing a transistor for an electrostatic discharge protection device to effectively solve the aforementioned drawbacks. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for fabricating a transistor for an electrostatic discharge protection device, which uses an anti-injection-like method to form an extension in the region of the drain region. Self-aligning the metal halide barrier region as a resistive buffer between the drain contact and the polysilicon gate, so that the high current generated by the electrostatic discharge can have a uniform current
I26〇762 五、發明說明（3) 勻的方式將其排除掉 本务明之另一目的 電晶體製造方法，其 系在提供一種靜電放電保護裝置之 導引出去，以避免^、、及f靜電高電壓產生之高電流有效的 現象，故可有效避免靜^附近產生局部高電流與局部加熱 本發明之A 一口 @笔放電保護結構被破壞。 * J y 白勺乂么 的靜電放電保護裝置二在提供一種具有較深之汲極接面 為達到上述之目：氣晶體製造方法。 有隔離結構、摻雜井區本發明係在一半導體基底上形成 為源/汲極之重離子摻雜、f ^極結構、輕離子摻雜區以及作 底上形成一圖案化光阻屉品’、基本兀件；接著在半導體基 露出之汲極區域進行離:，並以此圖案化光阻層為罩幕對 基底中而形成一延伸的f入’以便將摻質植入至半導體 光阻層，並進行熱然後去除圖案化 在半導體基底上之多整基底内之離子；最後， 自行對準金屬矽化物。T ’、源/ ’及極區域表面形成一 更容ΐ : ϊ ΐ ί ?實施 <列配合所附的圖式詳加說明，去 =易瞭解本發明之㈣、技術内容、特點及其所達成田之 【實施方式】 本發明係揭露-種類似自行對準金屬矽化物阻隔（ Sal1C1de block)的方法，以似反植入（retagrad卜 hke linplantatlon)方式在汲極區域下方形成一延伸阻 隔區域，使汲極接觸（drain_c〇ntract )至多晶矽接面 1260762 五、發明說明（4) (P〇ly-jUnctl〇n)之間有—電阻緩衝區 ballast )，進而使靜電放電 （ -較均句的方式將其排除掉電。(底ES;= 生之高電流嶋 …，詳細說明本發明之流；下係吻電晶體（麵 第五U)圖至第五（d)圖分別為本 製作應用於靜電放電仵罐雨攸+ + 月之#乂佺貝％例在 圖·如円所_ 1= 兒路之電晶體的各步驟構造剖視 KJ ，如圖所不，本發明之制生 首务，士二 &方法係包括有下列步驟·· 百先如乐五U)圖所示進行深次 在一半導體基底3 0中摻雜开彡# D , 水之‘車衣釭， 〇〇 、，. 形成一P型摻雜井區（P-Well ) 32 ,並於P型摻雜井區32内作才L β weii ) STI ) 34，桩缽产Γ产。内开/成有數個淺溝渠隔離區域（ 以閘極結構36為罩幕，對p都松^阳矽閘極結構36，並 子植人，w έ 乜雜井區3 2進行一低濃度離 卞植入，以形成輕離子摻雜 . 侧辟会报占右^ 4 ’ σ或38 ,再於閘極結構36的二 W 土方开/成有閘極間隙劈4 〇 · t、，日日t 4 0 A W莫 #4.D , ’、 ’以閘極結構36與閘極間隙壁 40為罩幕，對p型摻雜井 一、曲也η 離子佈植，以分別形成Ρ型重；：；：-度之Ρ型與Ν型重 雜區44、46，其中，、型^ 2雜區42與Ν型重離子摻 區44你你么％ /中P1重離子摻雜區42與N型重離子摻雜 4 4係作為原極區域，而n别舌 區ϋ · &始、# / 而以型重離子摻雜區46則作為汲極 ^域，而後進行一体祙赦旧、卜各 ^ 之該等基本元件已處理’至此半導體基義上 導ρ ί ^第五（b)圖所示’利用微影姓刻製程，在半 V體基底3 0上形忐一闰安儿+ #亍 成 圖案化光阻層4 8，徒立露屮兮於达、n 極區域之Ν型重離子摻雜區4β · 便，、路出该作為汲 暮，# + ψ夕 夕雜£46，以此圖案化光阻層48為罩 幕’於路出之及極區域46中以約大於綱KeV之高能= 第8頁 1260762 五、發明說明（5) 行離子植入，將璘或坤離子之摻質以大於1 * 1 〇13 / 、 之濃度植入至半導體美麻方么为 區域5〇。 ¥ -底30中而形成-延伸的汲極重摻質 完成該延伸的汲極重摻質區域5〇之後， 該圖案以阻層48，如“⑷圖所示，隨後繼續進刻Λ 回火m以藉此重整半導體基底3() =; 子與P型離子。 里I貝的N型離 夕曰：f如第五(d)圖所示，於該半導體基底30中之該 夕日日甲亟36、P型重離子摻雜區42與所有N型重離子松雜 區44、46之矣而游士 a 丨们更離子摻雜 敕之π a ^ Ϊ 成一自行對準金屬矽化物52，此時，完 = :=S;llclde製程之編電晶體結構已完整形^ /、中 形成该自動對準Μ τ/? /u flL· U： Ο 牛驟.卢电.t m t 屬矽化物52之步驟更包括下列 :::快、亲知：3基底表面先濺鍍形成一鈦金屬I ;再進行 ΐ。二^衣程’使鈦金屬層與多晶石夕閘極及重離子摻 雜“面相接觸部份產生石夕化反應以形成石夕化鈦（ 反廍2德if # @自行對準形成金屬石夕化物；而未參與反應或 ίΐ:Γ?鈦金屬將以座银刻的方式選擇性地加以去 示 17可在半導體基底30上形成如第五（cO圖所 自行對準金屬矽化物52姓播 /风戈弟五U)園所不之 金屬之外，亦可為❺'鎳;ΐ該金屬層之材質除了為鈦 本發明係在汲極區域下方其他金屬。録 Η你A Κ从rt 一 ^下方形成一延伸的汲極重摻質區 電阻緩衝區且Γ區Ϊ ’使汲極接觸至多晶矽通道之間有- 产亦較、，罙了可^ 於咖結構之汲極接面，其接面深 度亦車乂冰可讓靜電放電產纟之高電流能有一車交均勾的方 1260762 五、發明說明（6) 式將其排除掉，不致於汲極區域附近有局部高電流產生。 因此，本發明可將靜電高電壓產生之高電流有效的導引出 去，以避免在汲極附近產生局部高電流與局部加熱現象， 故可有效避免靜電放電保護結構被破壞。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内 容並據以實施，當不能以之限定本發明之專利範圍，即大 凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵 蓋在本發明之專利範圍内。 【圖號簡單說明】I26〇762 V. INSTRUCTIONS (3) A uniform method to eliminate the transistor manufacturing method of another purpose of the present invention, which is to provide an electrostatic discharge protection device to guide out to avoid static electricity of ^, , and f The high current generated by the high voltage is effective, so that it is possible to effectively avoid local high current and local heating in the vicinity of the static electricity. The A-Pen discharge protection structure of the present invention is destroyed. * J y The electrostatic discharge protection device 2 provides a deeper junction to achieve the above objectives: a method of manufacturing a gas crystal. Isolation structure, doped well region The present invention is formed on a semiconductor substrate as a source/drain for heavy ion doping, an f^ pole structure, a light ion doped region, and a patterned photoresist wafer as a substrate. ', the basic element; then in the semiconductor region exposed to the drain region of the separation: and the patterned photoresist layer as a mask to form an extended f into the substrate to implant the dopant into the semiconductor light Resisting the layer and performing heat and then removing ions patterned in the multi-substrate on the semiconductor substrate; finally, self-aligning the metal telluride. T ', source / ' and the surface of the polar region form a more accommodative: ϊ ΐ ί ? implementation of the column with the attached drawings to explain in detail, to easily understand the (four), technical content, features and [Embodiment] The present invention discloses a method for self-aligning a metal telluride barrier (S1), forming an extended barrier region under the drain region in a re-injection-like manner (retagrad hke linplantatlon). , so that the drain contact (drain_c〇ntract) to the polysilicon junction surface 1206762 5, invention description (4) (P〇ly-jUnctl〇n) between - resistance buffer ballast), and thus electrostatic discharge (- more uniform sentence The method is to eliminate the power. (Bottom ES; = high current 生..., detailing the flow of the present invention; lower kiss crystal (surface fifth U) to fifth (d) respectively for the production Applied to electrostatic discharge 仵 攸 攸 + + 月 月 % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % The first, the second and the second method include the following steps: · Bai Xianru Le Wu U) Performing a deep doping of a semiconductor substrate 30 into the opening #D, the water of the 'garment 釭, 〇〇,,. forming a P-type doping well region (P-Well) 32, and P-type doping In the well area 32, L β weii ) STI ) 34, piled 钵 produced. There are several shallow trench isolation areas in the inner opening/forming (with the gate structure 36 as the mask, the p-dusong-yang-yang gate structure 36, and the sub-planting, w έ 乜 well area 3 2 for a low concentration away卞 implanted to form light ion doping. The side will report the right ^ 4 ' σ or 38, and then the gate W structure of the two W earth open / into the gate gap 劈 4 〇 · t,, day t 4 0 AW Mo #4.D , ', ' with the gate structure 36 and the gate spacer 40 as a mask, p-type doping wells, and also η ions implanted to form the Ρ-type weight; :::--the Ρ type and Ν type heavy miscellaneous area 44, 46, wherein, type ^ 2 hetero region 42 and Ν type heavy ion doping region 44 you% / middle P1 heavy ion doping region 42 and N The type of heavy ion doping 4 4 is used as the primary region, and the n-there is the 舌 · & initial, # / and the type heavy ion doping region 46 is used as the bungee region, and then the whole is old, These basic components of each ^ have been processed 'to this semiconductor basic sense ρ ί ^ fifth (b) shown in the 'Using the lithography surname process, on the half V body substrate 30 on the shape of a 闰 An children + #图案成 patterned photoresist layer 4 8, 立立露屮兮The 重-type heavy ion doped region of the n- and n-pole regions is 4β · 便 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In the polar region 46, the energy is greater than about KeV = page 8 1260762. 5. Description of the invention (5) Ion implantation, implanting the dopant of strontium or quinone ion at a concentration greater than 1 * 1 〇 13 / , To the semiconductor beauty side, it is the area of 5 〇. ¥ - The bottom of the 30-formed-extended bungee heavy dopant completes the extended bungee-heavy dopant region 5 ,, the pattern is a resistive layer 48, such as "(4) As shown, the tempering m is subsequently continued to thereby reform the semiconductor substrate 3() =; sub- and P-type ions. The N-type annihilation of the I-be: f as shown in the fifth (d), In the semiconductor substrate 30, the daytime 亟 36, the P-type heavy ion doped region 42 and all the N-type heavy ion doped regions 44, 46 and the 士 a are more ion doped π π a ^ Ϊ A self-aligned metal halide 52, at this time, the finished = :=S; llclde process of the crystal structure has been completely formed ^ /, the formation of the automatic alignment Μ τ /? /u flL · U: Ο Cattle. Lu. The step of tmt belonging to the telluride 52 further includes the following::: fast, knowing: 3 the surface of the substrate is first sputtered to form a titanium metal I; and then the crucible is formed. The second layer is made of a titanium metal layer and a polycrystalline stone gate. And the heavy ion doping "surface contact part produces a lithochemical reaction to form a shixi titanium (reverse 德 2 de if # @ self-aligned to form a metal lithium; not involved in the reaction or ΐ: Γ? titanium metal will Selectively shown in the form of a silver engraving can form a semiconductor on the semiconductor substrate 30 other than the metal of the fifth (the self-aligned metal telluride 52 surname / the wind gorge five U). It can also be ❺ 'nickel; 材质 the material of the metal layer except titanium is the other metal of the invention under the bungee region. Recording your A Κ from the rt ^ ^ to form an extended bungee heavy doping zone resistance buffer and the Γ zone 汲 'to make the 汲 contact between the 多 矽 之间 - - - - - - 产 产 产 产 产 产 咖 咖 咖 咖The structure of the bungee junction, the junction depth is also the car ice can make the high current of the electrostatic discharge can produce a car with a hook of the 1260762. 5, invention description (6) to exclude it, not bungee There is local high current generation near the area. Therefore, the present invention can effectively guide the high current generated by the electrostatic high voltage to avoid local high current and local heating in the vicinity of the drain, so that the electrostatic discharge protection structure can be effectively prevented from being destroyed. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention. [Simple description of the figure]
10 靜電放電保護裝置 12 NMOS 14 PM0S 16 汲極接觸（區域） 18 多晶矽閘極 20 NPN電晶體 2 2 自行對準金屬碎化物2 4 源極區域 30 半導體基底 32 P型掺雜井區 34 淺溝渠隔離區域 36 閘極結構 38 輕離子摻雜區域 40 閘極間隙壁 42 P型重離子摻雜區 44、46 N型重離子摻雜區 4 8 圖案化光阻層 50 >及極重換質區域 5 2 自行對準金屬石夕化物10 Electrostatic discharge protection device 12 NMOS 14 PM0S 16 Dipole contact (region) 18 Polysilicon gate 20 NPN transistor 2 2 Self-aligned metal fragment 2 4 Source region 30 Semiconductor substrate 32 P-type well region 34 Shallow trench Isolation region 36 gate structure 38 light ion doped region 40 gate spacer 42 P-type heavy ion doped region 44, 46 N-type heavy ion doped region 4 8 patterned photoresist layer 50 > and extremely heavy mass change Area 5 2 self-aligning metal lithium
第10頁 1260762 圖式簡單說明 第一圖為習知靜電放電保護裝置之M0S元件應用於積體電 路中之線路結構示意圖。 第二圖為發生靜電放電現象的曲線圖。 第三圖為習知M0S元件應用於靜電放電保護裝置之結構示 意圖。 第四圖為習知具有自行對準金屬矽化物之靜電放電保護裝 置的電晶體結構示意圖。 第五（a)圖至第五（d)圖分別為本發明在製作電晶體的各步 驟構造剖視圖。Page 10 1260762 Brief Description of the Drawing The first figure shows the structure of the circuit in which the MOS component of the conventional electrostatic discharge protection device is applied to the integrated circuit. The second graph is a graph of the phenomenon of electrostatic discharge. The third figure shows the structure of a conventional MOS device applied to an electrostatic discharge protection device. The fourth figure is a schematic diagram of a transistor structure of an electrostatic discharge protection device having a self-aligned metal telluride. Figs. 5(a) to 5(d) are respectively sectional views showing the steps of the steps of fabricating the transistor of the present invention.
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