TWI542272B - Manufacturing method for multi-layer circuit board - Google Patents

Description

Multilayer circuit board manufacturing method

The present invention relates to a method of fabricating a circuit board, and more particularly to a method of fabricating a multilayer circuit board.

Generally, a circuit board is mainly formed by alternately stacking a plurality of patterned conductive layers and a plurality of dielectric layers, and electrically connecting the patterned conductive layers by using a plurality of conductive vias. Floor. In addition, in terms of the process of the circuit board, the circuit board mainly includes two types of circuit boards: a laminating process and a build-up process, in which a circuit board of a lower wiring density is mostly pressed. It is legal to make it, and boards with higher wiring density are usually made by layering.

1A to FIG. 1H are schematic diagrams showing a manufacturing process of a conventional circuit board. As shown in FIG. 1A, first, a core substrate 110 is provided. The core substrate 110 includes a dielectric layer 111 and conductive layers 112 and 113 on opposite surfaces of the dielectric layer 111. As shown in FIG. 1B, a through hole 114 is then formed in the dielectric layer 111 and the conductive layers 112 and 113. As shown in FIG. 1C, it is then formed in the conductive layer 112 and the dielectric layer 111. The blind via 115 is filled with a conductive material in the blind via 115 to form a conductive via 115a (shown in FIG. 1D).

As shown in FIG. 1D, the via hole 114 is then plated to form a conductive via hole 114a, wherein a plating layer is formed on the surfaces of the conductive layers 112 and 113, respectively, while electroplating forms the conductive via hole 114a, and the two plating layers respectively belong to Conductive layers 112 and 113. That is, the thickness of the conductive layers 112 and 113 shown in FIG. 1D is slightly larger than the thicknesses of the conductive layers 112 and 113 shown in FIG. 1A. As shown in FIG. 1E, conductive layers 112 and 113 are patterned to form patterned wiring layers 112a and 113a. As shown in FIG. 1F, the stacked layers 120a and 120b are respectively formed on the patterned wiring layers 112a and 113a by a press or build-up method, wherein the stacked layer 120a includes a dielectric layer 121a and a conductive layer 122a, and the stacked layers are stacked. 120b includes a dielectric layer 121b and a conductive layer 122b.

As shown in FIG. 1G, blind vias 123a and 123b are then formed in the stacked layers 120a and 120b, respectively, and conductive materials are filled in the blind vias 123a and 123b to form conductive vias 124a and 124b. In addition, after the conductive vias 124a and 124b are formed, the surface of the conductive via 124a exposed by the conductive layer 122a and the surface of the conductive via 124b exposed by the conductive layer 122b are simultaneously formed on the surfaces of the conductive layers 122a and 122b. A plating layer is separately formed, and the two plating layers belong to the conductive layers 122a and 122b, respectively. That is, the thicknesses of the conductive layers 122a and 122b shown in FIG. 1G are slightly larger than the thicknesses of the conductive layers 112 and 113 shown in FIG. 1F. Finally, as shown in FIG. 1H, conductive layers 122a and 122b are patterned to form patterned wiring layers 125a and 125b. Generally, a solder resist layer (not shown) is formed on the patterned circuit layers 125a and 125b, respectively, and a partial patterned circuit layer is exposed to further expose a solder resist layer (not shown). to Thus, the fabrication of the circuit board 100 is substantially completed.

As far as the process requirements of the circuit board 100 are concerned, the thickness of the core substrate 110 is limited, which is disadvantageous for reducing the overall thickness of the circuit board, so that it is difficult to meet the development trend of thinning of the current circuit board. On the other hand, when the thickness of the core substrate 110 is too thin (for example, the thickness is 50 μm or less), the structural strength of the core substrate 110 is insufficient, so that the core substrate 110 is susceptible to stress during the fabrication process of the circuit board 100. Warpage. Wherein, the warped and deformed core substrate 110 is easy to interfere with the process equipment to cause the card board, and the condition of the card board needs to be eliminated manually. That is to say, the manufacturing method of the circuit board 100 is not only difficult to satisfy the trend of thinning, but it is not possible to reduce the overall thickness of the circuit board 100 while producing a finer circuit pattern, and also has a low production efficiency and a good yield. Disadvantages. In addition, the fabrication method of the circuit board 100 is also difficult to apply to the fabrication of a circuit board having an odd-numbered wiring layer.

The invention provides a manufacturing method of a multilayer circuit board, which can be applied to the manufacture of a multilayer circuit structure of an odd-numbered circuit layer and an even-numbered circuit layer at the same time, and can improve process efficiency and yield and reduce the thickness of the multilayer circuit board. Wherein, the manufacturing method of the multi-layer circuit board can produce an ultra-thin circuit board of any number of layers, and the finished product of the ultra-thin circuit board with ten layers of the circuit layer is exemplified, and the thickness thereof can be equal to or less than 500 micrometers.

The present invention further provides a method of fabricating a multilayer circuit board that can produce a finer line pattern to increase wiring density.

The present invention provides a method of fabricating a multilayer circuit board that includes the following steps. First, a metal carrier is provided. The metal carrier has a rough surface. Next, a conductive substrate layer covering the metal carrier is formed, wherein the conductive substrate layer has opposing first and second surfaces. Then, the first stacked layer is respectively pressed onto the first surface and the second surface, wherein each of the first stacked layers includes a first dielectric layer and a first conductive layer covering the first dielectric layer. Then, the second stacked layer is respectively pressed onto each of the first conductive layers, wherein each of the second stacked layers includes a second dielectric layer and a second conductive layer covering the second dielectric layer. Next, the edges of the conductive substrate layer, the respective first stacked layers, and the respective second stacked layers are cut to expose side surfaces of the metal carrier, and the conductive substrate layer is divided into two layers. Thereafter, each layer is separated from the metal carrier.

The present invention further provides a method of fabricating a multilayer circuit board comprising the following steps. First, a metal carrier is provided. The metal carrier has a rough surface. Next, a conductive substrate layer covering the metal carrier is formed, wherein the conductive substrate layer has opposing first and second surfaces. Next, a patterned film layer is formed on the first surface and the second surface, respectively, wherein each of the patterned film layers exposes a portion of the conductive substrate layer. Next, the conductive substrate layers exposed by the respective patterned film layers are plated to form build-up lines on the conductive substrate layers exposed by the respective patterned film layers. Next, each patterned film layer is removed. Then, respectively pressing the first stacked layer on the first surface and the second surface, wherein each of the first stacked layers includes a first dielectric layer and a first conductive layer covering the first dielectric layer, and each of the first dielectric layers The layer is coated with a corresponding build-up line. Next, the conductive substrate layer and the edges of the respective first stacked layers are cut to expose the side surfaces of the metal carrier, and the conductive substrate layer is divided into two layers. After that, separate the layers and metals Carrier board.

Based on the above, the method of fabricating the multilayer circuit board of the present invention first provides a metal carrier having a rough surface, and then forming two opposing multilayer wiring structures on the metal carrier, wherein the two multilayer wiring structures may have an odd layer wiring layer or Even layer circuit layer. The two-layer circuit structure can be removed from the metal carrier to facilitate subsequent processes. Compared with the conventional process of manufacturing a multilayer circuit board by using a core substrate, the manufacturing method of the multilayer circuit board of the present invention can not only improve process efficiency and yield, but also effectively reduce the thickness of the multilayer wiring structure to conform to thinning. The development trend. In addition, while reducing the overall thickness of the multilayer circuit board, a more elaborate wiring pattern can be produced by the method of fabricating the multilayer circuit board of the present invention to increase the wiring density.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧ boards

110‧‧‧ core substrate

111, 121a, 121b, 122b‧‧‧ dielectric layer

112, 113, 122a‧‧‧ conductive layer

112a, 113a, 125a, 125b‧‧‧ patterned circuit layers

114, TH‧‧‧through hole

114a, TH1‧‧‧ conductive through hole

115, 123a, 123b‧‧‧ blind holes

115a, 124a, 124b, BH1, BH2, BH7‧‧‧ conductive blind holes

120a, 120b‧‧‧ stacked layers

200, 200A, 200B‧‧‧ multilayer board

210, 210a, 210b‧‧‧ metal carrier

211‧‧‧ side surface

211a‧‧‧first through hole

212a‧‧‧first conductive through hole

220‧‧‧ conductive base layer

221‧‧‧ first surface

222‧‧‧ second surface

223, 224‧‧ ‧ layered

223a‧‧‧patterned layering

230, 240‧‧‧ first stacking layer

231, 241‧‧‧ first dielectric layer

232, 242‧‧‧ first conductive layer

232a, 242a‧‧‧ first line layer

233, 243‧‧‧ alignment mark

233a, 243a‧‧‧ first through hole

233b, 243b‧‧‧ first conductive via

250, 260‧‧‧ second stack

251, 261‧‧‧ second dielectric layer

252, 262‧‧‧ second conductive layer

252a, 262a‧‧‧second circuit layer

253, 263‧‧‧ second through hole

253a, 263a‧‧‧ second conductive via

270, 280‧‧‧ third stack

271, 281‧‧‧ third dielectric layer

272, 282‧‧‧ third conductive layer

272a, 282a‧‧‧ third circuit layer

291, 292‧‧‧ patterned film

293, 294‧‧ ‧ layered lines

BH3, BH4‧‧‧ first conductive blind hole

BH5‧‧‧Second conductive blind hole

BH6‧‧‧3rd conductive blind hole

D‧‧‧diameter

TH2‧‧‧Second hole

TH3‧‧‧Second conductive through hole

1A to FIG. 1H are schematic diagrams showing a manufacturing process of a conventional circuit board.

2A to 2J are schematic diagrams showing a manufacturing process of a multilayer circuit board according to an embodiment of the present invention.

3A-3M are schematic diagrams showing a manufacturing process of a multilayer circuit board according to another embodiment of the present invention.

4A to 4J are diagrams showing a manufacturing process of a multilayer circuit board according to another embodiment of the present invention; schematic diagram.

2A to 2J are diagrams showing a manufacturing flow of a multilayer circuit board according to an embodiment of the present invention; Schematic diagram. Referring to FIG. 2A, first, a metal carrier 210 is provided. Here, the metal carrier 210 may be a stainless steel plate and is made of an acid-resistant stainless steel material (for example, SUS 304), but the present invention is not limited thereto. In other embodiments, the metal carrier 210 can also be constructed of other suitable metal materials.

In the present embodiment, the thickness of the metal carrier 210 is between about 0.1 mm and 1.2 mm. Before the metal carrier 210 is plated, the metal carrier 210 may be subjected to a brushing process so that the metal carrier 210 has a rough surface. Here, the rough surface has a center line average roughness of about 0.1 μm to 0.6 μm, and the rough surface has a ten point average roughness of about 0.5 μm to 1.5 μm, but the invention is not limited thereto.

As shown in FIG. 2B, the conductive substrate layer 220 covering the metal carrier 210 is formed, for example, by electroplating, wherein the conductive substrate layer 220 has opposite first and second surfaces 221 and 222, and the material thereof is, for example, copper. Or a conductive metal such as tin, silver or gold, which is not limited in the present invention. Since the metal carrier 210 has a rough surface, the conductive substrate layer 220 and the metal carrier 210 can be surely bonded together, but the conductive substrate layer 220 can be separated from the metal carrier 210 by applying an appropriate external force.

As shown in FIG. 2C, the first stacked layers 230 and 240 are respectively pressed into the first table. On the surface 221 and the second surface 222, wherein the first stacked layer 230 includes a first dielectric layer 231 and a first conductive layer 232 covering the first dielectric layer 231, and the first stacked layer 240 includes a first dielectric layer 241 And a first conductive layer 242 covering the first dielectric layer 241. Generally, the material of the first dielectric layers 231 and 241 may be epoxy resin or epoxy resin containing glass fibers, and the first conductive layers 232 and 242 may be made of copper or tin, silver or gold. Conductive metal, the invention is not limited thereto.

As shown in FIG. 2D, alignment marks 233 and 243 are formed on the first conductive layers 232 and 242, respectively, by exposure (for example, ultraviolet light). Next, the alignment marks 233 and 243 are used as a registration reference, and the first conductive layers 232 and 242 are patterned, for example, by lithography and etching to form the first wiring layers 232a and 242a, respectively.

As shown in FIG. 2E, the second stacked layers 250 and 260 are respectively pressed onto the patterned first conductive layers 232 and 242 (ie, the first circuit layers 232a and 242a), wherein the second stacked layer 250 includes a second dielectric layer. The electrical layer 251 and the second conductive layer 252 covering the second dielectric layer 251, and the second stacked layer 260 includes a second dielectric layer 261 and a second conductive layer 262 covering the second dielectric layer 261. Generally, the second dielectric layers 251 and 261 may be made of epoxy resin or glass fiber-containing epoxy resin, and the second conductive layers 252 and 262 may be made of copper or tin, silver or gold. Conductive metal, the invention is not limited thereto. In addition, the widths of the first dielectric layers 231 and 241 and the second dielectric layers 251 and 261 are both greater than the width of the metal carrier 210.

As shown in FIG. 2F, the conductive substrate layer 220, the first stacked layers 230 and 240, and the edges of the second stacked layers 250 and 260, that is, the conductive substrate layer 220, the first stack, are cut, for example, by grinding or laser cutting. Layers 230 and 240 and second stack The laminate 250 and 260 extend beyond the side surface 211 of the metal carrier 210 to expose the side surface 211 and divide the conductive substrate layer 220 into two layers 223 and 224.

There is a certain bonding force between the layer 223 and the metal carrier 210 and between the layer 224 and the metal carrier 210, but the layer 223 and the metal carrier 210 and the layer 223 and the metal can be applied by applying an appropriate external force. The carrier 210 is separated as shown in Fig. 2G. Thereby, after the layers 223 and 224 are removed from the metal carrier 210, the rough surface of the metal carrier 210 does not leave a residue, and the center line average roughness or the ten-point average roughness of the rough surface can still be met. The foregoing process requirements are such that the metal carrier 210 can be reused. On the other hand, before the metal carrier 210 is repeatedly used, it is also confirmed whether the surface roughness of the rough surface of the metal carrier 210 is still in compliance with the specification, for example, the metal carrier 210 may be again subjected to brushing treatment. In order to restore the surface roughness of the rough surface to the numerical range required by the aforementioned process.

As shown in FIG. 2H, a through layer 223 is formed and stacked thereon, for example, by X-ray drilling, laser drilling, or mechanical drilling. The first dielectric layer 231, the first wiring layer 232a, the second dielectric layer 251, and the through hole TH of the second conductive layer 252. Here, the through hole TH is, for example, a position penetrating the alignment mark 233 at the first wiring layer 232a, but the present invention is not limited thereto. In an embodiment not shown, the through layer 224 and the first dielectric layer 241 and the first circuit layer stacked thereon may be formed by X-ray drilling, laser drilling or mechanical drilling. 242a, the second dielectric layer 261 and the through hole of the second conductive layer 262. The following process will be a multilayer line composed of a layer 223, a first dielectric layer 231, a first wiring layer 232a, a second dielectric layer 251, and a second conductive layer 252. The structure of the circuit is further described. The fabrication flow and principle of the multilayer circuit structure formed by the layer 224, the first dielectric layer 241, the first circuit layer 242a, the second dielectric layer 261 and the second conductive layer 262 can be referred to Execution, no longer repeat them here.

As shown in FIG. 2I, a plurality of conductive blind vias BH1 electrically connecting the layer 223 and the first wiring layer 232a and a plurality of conductive blind vias BH2 electrically connecting the first wiring layer 232a and the second conductive layer 252 are formed, and The through holes TH are plated to form conductive through holes TH1. Generally, the specific implementation of the fabrication step is, for example, forming a plurality of blind holes in the layer 223 and the first dielectric layer 231 and the second dielectric layer 251 and the second conductive layer 252, respectively, and filling the conductive holes. Materials are formed in the blind vias to form the conductive vias BH1 and the conductive vias BH2, respectively. Then, while plating the through holes TH to form the conductive through holes TH1, a plating layer is also formed on the surfaces of the layer 223 and the second conductive layer 252, respectively, and the two plating layers belong to the layer 223 and the second conductive layer, respectively. 252. That is, the thickness of the layer 223 and the second conductive layer 252 shown in FIG. 2I is slightly larger than the thickness of the layer 223 and the second conductive layer 252 shown in FIG. 2H.

Thereafter, as shown in FIG. 2J, the conductive vias TH1 are used as a registration reference, for example, by lithography and etching, to pattern the layer 223 and the second conductive layer 252 to form a patterned layer 223a and a second, respectively. Circuit layer 252a. Generally, a solder resist layer (not shown) is formed on the patterned layer 223a and the second line layer 252a, respectively, and the partial patterned layer 223a and the second line layer 252a are exposed, that is, substantially completed. Fabrication of multilayer circuit board 200.

In short, the fabrication of the multi-layer circuit board 200 is exemplified by a multi-layer circuit structure in which the number of layers of the circuit layer is three, which is based on the multi-layer circuit structure. Further, a pressing or stacking method is used to fabricate a multilayer wiring structure in which the number of layers of the wiring layer is odd and larger than three. Compared with the conventional process of manufacturing a multilayer circuit board by using a core substrate, the manufacturing method of the multilayer circuit board 200 can not only improve process efficiency and yield, but also effectively reduce the thickness of the multilayer circuit structure to conform to the development of thinning. trend.

Other embodiments are listed below for illustration. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

3A-3M are schematic diagrams showing a manufacturing process of a multilayer circuit board according to another embodiment of the present invention. Referring to FIG. 3A and FIG. 3B, first, a metal carrier 210a is provided, and a first through hole 211a is formed in the metal carrier 210a, for example, by X-ray drilling, laser drilling or mechanical drilling, wherein the first through hole 211a The diameter D of the hole 211a is 3.5 ± 0.2 μm. After the conductive base layer 220 covering the metal carrier 210a is formed, for example, by electroplating, the first through hole 211a may form the first conductive through hole 212a.

As shown in FIG. 3C, the first stacked layers 230 and 240 are respectively pressed onto the first surface 221 and the second surface 222 of the conductive base layer 220, wherein the first stacked layer 230 includes a first dielectric layer 231 and covers the first The first conductive layer 232 of the dielectric layer 231, and the first stacked layer 240 includes a first dielectric layer 241 and a first conductive layer 242 covering the first dielectric layer 241. Then, the first through hole 233a penetrating the first stacked layer 230 is formed, for example, by, for example, X-ray drilling, laser drilling, or mechanical drilling. And a first through hole 243a penetrating the first stacked layer 240, wherein the first through holes 233a and 243a respectively communicate with the first conductive through hole 212a.

As shown in FIG. 3D, the first conductive vias 233a and 243a are used as alignment references, and the first conductive layers 232 and 242 are patterned, for example, by lithography and etching to form the first wiring layers 232a and 242a, respectively. Then, the first through holes 233a and 243a are plated to form first conductive vias 233b and 243b, respectively, wherein the first conductive vias 233b and 243b are electrically connected to the first conductive vias 212a, respectively.

As shown in FIG. 3E, the second stacked layers 250 and 260 are respectively pressed onto the patterned first conductive layers 232 and 242 (ie, the first circuit layers 232a and 242a), wherein the second stacked layer 250 includes the second dielectric layer. The electrical layer 251 and the second conductive layer 252 covering the second dielectric layer 251, and the second stacked layer 260 includes a second dielectric layer 261 and a second conductive layer 262 covering the second dielectric layer 261. Next, a second through hole 253 penetrating the second stacked layer 250 and a second through hole 263 penetrating the second stacked layer 260 are formed, for example, by X-ray drilling, laser drilling, or mechanical drilling, wherein the second The through hole 253 communicates with the first conductive via 233b, and the second via 263 communicates with the first conductive via 243b.

As shown in FIG. 3F, a plurality of first conductive vias BH3 electrically connecting the first circuit layer 232a and the second conductive layer 252 and a plurality of first electrodes electrically connecting the first circuit layer 242a and the second conductive layer 262 are formed. Conducting the blind vias BH4, and plating the second vias 253 and 263 to form second conductive vias 253a and 263a, respectively, wherein the second conductive vias 253a are electrically connected to the first conductive vias 233b, and the second conductive vias 263a The first conductive via 243b is electrically connected.

As shown in FIG. 3G, the second conductive vias 252a and 263a are used as alignment references, for example, by lithography and etching, to pattern the second conductive layers 252 and 262 to form the second wiring layers 252a and 262a, respectively. Next, as shown in FIG. 3H, the third stacked layers 270 and 280 are respectively pressed onto the second wiring layers 252a and 262a, wherein the third stacked layer 270 includes a third dielectric layer 271 and a third dielectric layer 271. The third conductive layer 272 includes a third dielectric layer 281 and a third conductive layer 282 covering the third dielectric layer 281.

As shown in FIG. 3I, the conductive base layer 220, the first stacked layers 230 and 240, the second stacked layers 250 and 260, and the edges of the third stacked layers 270 and 280 are cut, for example, by grinding or laser cutting, that is, a portion of the conductive substrate layer 220, the first stacked layers 230 and 240, the second stacked layers 250 and 260, and the third stacked layers 270 and 280 beyond the side surface 211 of the metal carrier 210a to expose the side surface 211, and The conductive substrate layer 220 is divided into two layers 223 and 224. Next, the layer 223 can be separated from the metal carrier 210a and the layer 223 from the metal carrier 210a by applying an appropriate external force, as shown in FIG. 3J.

As shown in FIG. 3K, the through-layer 223 and the first dielectric layer 231, the first wiring layer 232a, and the first layer formed thereon are formed, for example, by X-ray drilling, laser drilling, or mechanical drilling. The second dielectric layer 251, the second wiring layer 252a, the third dielectric layer 271, and the second through hole TH2 of the third conductive layer 272. In an embodiment not shown, the through layer 224 and the first dielectric layer 241 and the first circuit layer stacked thereon may be formed by X-ray drilling, laser drilling or mechanical drilling. 242a, second dielectric layer 261, second wiring layer 262a, third dielectric layer 281, and third conductive layer 282 Two through holes. The following process will be a plurality of layers of a layer 223, a first dielectric layer 231, a first wiring layer 232a, a second dielectric layer 251, a second wiring layer 252a, a third dielectric layer 271, and a third conductive layer 272. The circuit structure is further illustrated, wherein the layer 224, the first dielectric layer 241, the first circuit layer 242a, the second dielectric layer 261, the second circuit layer 262a, the third dielectric layer 281, and the third conductive layer 282 The manufacturing process and principle of the constructed multilayer circuit structure can be referred to for implementation, and will not be described herein.

As shown in FIG. 3L, a plurality of second conductive blind vias BH5 electrically connecting the layer 223 and the first wiring layer 232a and a plurality of third conductive blinds electrically connecting the second wiring layer 262a and the third conductive layer 272 are formed. The hole BH6 is plated and the second through hole TH2 is plated to form the second conductive through hole TH3. Thereafter, as shown in FIG. 3M, the second conductive vias TH3 are used as the alignment reference, for example, by lithography and etching, to pattern the layer 223 of the third conductive layer 272 to form the patterned layer 223a and the first layer, respectively. Two circuit layers 272a. Generally, a solder resist layer (not shown) is formed on the patterned layer 223a and the second line layer 272a, respectively, and the partial patterned layer 223a and the second line layer 272a are exposed, that is, substantially completed. Fabrication of multilayer circuit board 200A.

In short, the fabrication of the multilayer circuit board 200A is exemplified by a multi-layer circuit structure in which the number of layers of the circuit layer is four layers, and based on the multilayer circuit structure, the circuit layer can be further fabricated by using a pressing method or a build-up method. The number of layers is an even number and is greater than four layers of a multilayer circuit structure. Compared with the conventional process of manufacturing a multilayer circuit board by using a core substrate, the manufacturing method of the multilayer circuit board 200A can not only improve process efficiency and yield, but also effectively reduce the thickness of the multilayer circuit structure to conform to the development of thinning. trend. For example, the method of fabricating the multilayer circuit board can produce any number of layers The ultra-thin circuit board is exemplified by a finished product of a ten-layer ultra-thin circuit board having a thickness of 500 μm or less.

4A to 4J are schematic diagrams showing a manufacturing process of a multilayer circuit board according to another embodiment of the present invention. Referring to FIG. 4A and FIG. 4B, first, a metal carrier 210b is provided, and a conductive substrate layer 220 covering the metal carrier 210b is formed, for example, by electroplating, wherein the conductive substrate layer 220 has opposite first surfaces 221 and Two surfaces 222. Next, as shown in FIGS. 4C to 4E, a negative transfer is performed on the first surface 221 and the second surface 222, respectively. First, the patterned film layers 291 and 292 are formed on the first surface 221 and the second surface 222, respectively, wherein the patterned film layers 291 and 292 respectively expose a portion of the conductive substrate layer 220. Generally, the specific implementation of the patterned film layers 291 and 292 is performed by bonding the photosensitive dry film to the first surface 221 and the second surface 222 by a hot pressing roller, and then can be moved by exposure and development. A portion of the photosensitive dry film is defined to define patterned film layers 291 and 292. Next, the conductive base layer 220 exposed by the patterned film layers 291 and 292 is plated to form the conductive base layer 220 and the build-up layer 294 exposed by the patterned layer 291, respectively, on the patterned layer 291. 222 exposed conductive substrate layer 220. Here, the material of the build-up lines 293 and 294 may be copper or a conductive metal such as tin, silver or gold, which is not limited in the present invention. Thereafter, the patterned film layers 291 and 292 are removed, at which time the layout of the lines on the first surface 221 and the second surface 222 has been substantially completed.

As shown in FIG. 4F, the first stacked layers 230 and 240 are respectively pressed onto the first surface 221 and the second surface 222, wherein the first stacked layer 230 includes a first dielectric layer. 231 and a first conductive layer 232 covering the first dielectric layer 231 , and the first stacked layer 240 includes a first dielectric layer 241 and a first conductive layer 242 covering the first dielectric layer 241 . In addition, the first dielectric layer 231 also covers the build-up line 293, and the first dielectric layer 241 also covers the build-up line 294. Next, as shown in FIG. 4G, the conductive base layer 220 and the edges of the first stacked layers 230 and 240, that is, the conductive base layer 220 and the portions of the side surface 211 of the metal carrier 210b beyond which the first stacked layers 230 and 240 are exceeded are cut. To expose the side surface 211 and divide the conductive substrate layer 220 into two layers 223 and 224. Next, the layer 223 can be separated from the metal carrier 210a and the layer 223 from the metal carrier 210a by applying an appropriate external force, as shown in FIG. 4H.

The following process will further illustrate a two-layer circuit structure composed of a layer 223, a build-up line 293, a first dielectric layer 231, and a first conductive layer 232, wherein the layer 224, the build-up line 294, and the first layer The manufacturing process and principle of the two-layer circuit structure formed by the electrical layer 241 and the first conductive layer 242 can be referred to for implementation, and will not be described herein. As shown in FIG. 4I, a conductive via hole BH7 electrically connecting the layer 223 and the build-up line 293 is formed. Thereafter, the first conductive layer 232 and the layer 223 are patterned to form a first wiring layer 232a and a patterned layer 223a, respectively, wherein the patterned layer 223a covers a portion of the build-up layer 293, as shown in FIG. 4J. Generally, a solder resist layer (not shown) is formed on the patterned layer 223a and the first circuit layer 232a, respectively, and the partial patterned layer 223a and the first circuit layer 232a are exposed, that is, substantially completed. Fabrication of multilayer circuit board 200B.

On the other hand, in other feasible embodiments, the entire layer can be layered in the process of patterning the first conductive layer 232 and the layer 223, depending on actual design requirements. 223 is etched away, i.e., the patterned layer 223a as shown in FIG. 4J will not be present on the first dielectric layer 231 to expose all of the buildup lines 293.

In short, the fabrication of the multilayer circuit board 200B is exemplified by a two-layer circuit structure in which a double-layer circuit structure obtained by the above-described fabrication process can reduce the overall thickness and produce a finer circuit pattern to improve wiring. density. Here, the line width and line/space of the fine line pattern in the multilayer circuit board 200B may be 40 μm / 40 μm or less.

In summary, the method for fabricating the multilayer circuit board of the present invention first provides a metal carrier having a rough surface, and then forms two opposing multilayer wiring structures on the metal carrier, wherein the two multilayer wiring structures can have odd layer wiring Layer or even layer circuit layer. The two-layer circuit structure can be removed from the metal carrier to facilitate subsequent processes. Compared with the conventional multilayer circuit board manufacturing process using the core substrate, the manufacturing method of the multilayer circuit board of the present invention can not only improve the process efficiency and the yield, but also effectively reduce the thickness of the multilayer wiring structure to conform to the thin type. Development trend. In addition, while reducing the overall thickness of the multilayer circuit board, a more elaborate wiring pattern can be produced by the method of fabricating the multilayer circuit board of the present invention to increase the wiring density.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

210‧‧‧Metal carrier board

223, 224‧‧ ‧ layered

230, 240‧‧‧ first stacking layer

231, 241‧‧‧ first dielectric layer

232a, 242a‧‧‧ first line layer

233, 243‧‧‧ alignment mark

250, 260‧‧‧ second stack

251, 261‧‧‧ second dielectric layer

252, 262‧‧‧ second conductive layer

Claims (18)

A method of fabricating a multilayer circuit board, comprising: providing a metal carrier board, wherein the metal carrier board has a rough surface; forming a conductive substrate layer covering the metal carrier board, wherein the conductive substrate layer has a first one a surface and a second surface; respectively pressing a first stacked layer on the first surface and the second surface, wherein each of the first stacked layers comprises a first dielectric layer and a first dielectric layer a first conductive layer; each of the first conductive layers is patterned by using the alignment marks as a registration reference to form a first circuit layer; and a second stacked layer is respectively pressed onto each of the first conductive layers, Each of the second stacked layers includes a second dielectric layer and a second conductive layer covering the second dielectric layer; cutting the conductive base layer, each of the first stacked layers, and an edge of each of the second stacked layers To expose a side surface of the metal carrier and divide the conductive substrate into two layers; and separate each of the layers from the metal carrier. The method of fabricating a multilayer circuit board according to claim 1, wherein the rough surface has a center line average roughness of between 0.1 μm and 0.6 μm. The method of fabricating a multilayer circuit board according to claim 1, wherein the rough surface has a ten point average roughness of between 0.5 μm and 1.5 μm. A method of fabricating a multilayer circuit board according to claim 1, wherein The metal carrier plate is a stainless steel plate. The method of fabricating a multilayer circuit board according to claim 1, wherein the metal carrier has a thickness of between 0.1 mm and 1.2 mm. The method for fabricating a multilayer circuit board according to claim 1, wherein a width of each of the first dielectric layer and each of the second dielectric layers is greater than a width of the metal carrier. The method for fabricating a multilayer circuit board according to claim 1, further comprising: forming the first dielectric layer, the first circuit layer, and the second dielectric layer penetrating the layer and the layer And a plurality of conductive layers of the second conductive layer; a blind hole, and plating the through hole to form a conductive through hole; and patterning each of the layer and each of the second conductive layers by using the conductive through hole as a registration reference to form a patterned layer and a first Two circuit layers. The method for fabricating a multilayer circuit board according to claim 1, wherein the metal carrier has a first through hole, and after forming the conductive substrate layer covering the metal carrier, the first through hole Forming a first conductive via. The method of fabricating a multilayer circuit board according to claim 8, wherein the first through hole has a diameter of 3.5 ± 0.2 μm. The method for fabricating a multilayer circuit board according to claim 8, wherein before respectively pressing each of the second stacked layers on the corresponding first conductive layer, The method further includes: forming a first through hole penetrating each of the first stacked layers, wherein each of the first through holes respectively communicates with the first conductive through hole; and patterning each of the first through holes by using a reference for each of the first through holes The first conductive layer is respectively formed with a first circuit layer, and each of the first through holes is plated to form a first conductive via, wherein each of the first conductive vias is electrically connected to the first conductive via . The method for fabricating a multilayer circuit board according to claim 10, wherein before the cutting of the conductive base layer, the first stacked layer, and the edges of each of the second stacked layers, the method further comprises: forming a through a second via hole of the second stacking layer, wherein each of the second via holes is connected to the corresponding first conductive via hole; forming a plurality of first portions electrically connecting each of the first circuit layer and the corresponding second conductive layer Conducting a blind via, and plating each of the second vias to form a second conductive via, wherein each of the second conductive vias is electrically connected to the corresponding first conductive via; using each of the second conductive vias Patterning each of the second conductive layers to form a second circuit layer, and pressing a third stacked layer on each of the second circuit layers, wherein each of the third stacked layers includes a first a third dielectric layer and a third conductive layer covering the third dielectric layer, and cutting each of the third while cutting the conductive base layer, each of the first stacked layer, and an edge of each of the second stacked layers The edges of the stack. The method for fabricating a multilayer circuit board according to claim 11, wherein after separating the layers and the metal carrier, the method further comprises: Forming the first dielectric layer, the first wiring layer, the second dielectric layer, the second wiring layer, the third dielectric layer, and the third conductive layer across the layer and stacked thereon a second through hole of the layer; forming a plurality of second conductive blind holes electrically connected to the layer and the corresponding first circuit layer; and electrically connecting each of the second circuit layers and the corresponding third conductive layer a plurality of third conductive via holes, and plating the second via holes to form a second conductive via hole; and patterning each of the layer and each of the third conductive layers by using the second conductive via holes as a parity reference The layers are respectively formed into a patterned layer and a third line layer. A method of fabricating a multilayer circuit board, comprising: providing a metal carrier board, wherein the metal carrier board has a rough surface; forming a conductive substrate layer covering the metal carrier board, wherein the conductive substrate layer has a first one a surface and a second surface; respectively forming a patterned film layer on the first surface and the second surface, wherein each of the patterned film layers respectively exposes a portion of the conductive substrate layer; plating each of the patterned film layers Exposing the conductive substrate layer to form a build-up layer on the conductive substrate layer exposed by each of the patterned film layers; removing each of the patterned film layers; respectively pressing a first stacked layer On the first surface and the second surface, each of the first stacked layers includes a first dielectric layer and a first conductive layer covering the first dielectric layer, and each of the first dielectric layers is coated The build-up line; cutting the conductive base layer and the edges of each of the first stacked layers to expose the a side surface of the metal carrier, and dividing the conductive substrate layer into two layers; separating each layer from the metal carrier; forming a conductive blind hole electrically connecting each layer and the corresponding layered wiring And patterning each of the first conductive layers and each of the layers to form a first circuit layer and a patterned layer, respectively. The method of fabricating a multilayer circuit board according to claim 13, wherein the rough surface has a center line average roughness of between 0.1 μm and 0.6 μm. The method of fabricating a multilayer circuit board according to claim 13, wherein the rough surface has a ten point average roughness of between 0.5 μm and 1.5 μm. The method of fabricating a multilayer circuit board according to claim 13, wherein the metal carrier is a stainless steel plate. The method of fabricating a multilayer circuit board according to claim 13, wherein the metal carrier has a thickness of between 0.1 mm and 1.2 mm. The method of fabricating a multilayer circuit board according to claim 13, wherein a width of each of the first dielectric layers is greater than a width of the metal carrier.