CN105451471B - The preparation method of multilayer circuit board - Google Patents
The preparation method of multilayer circuit board Download PDFInfo
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- CN105451471B CN105451471B CN201410275583.9A CN201410275583A CN105451471B CN 105451471 B CN105451471 B CN 105451471B CN 201410275583 A CN201410275583 A CN 201410275583A CN 105451471 B CN105451471 B CN 105451471B
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Abstract
The present invention discloses a kind of preparation method of multilayer circuit board, and it comprises the following steps.First, there is provided there is the metal support plate of rough surface.Then, the conductive basal layer of cladding metal support plate is formed.Then, the first stack layer is pressed respectively on the first surface and second surface of conductive basal layer.Then, the second stack layer is pressed respectively on each first conductive layer.Then, the edge of conductive basal layer, each first stack layer and each second stack layer is cut, to expose the side surface of metal support plate, and conductive basal layer is divided into two layerings.Afterwards, each layering and metal support plate are separated.The present invention separately proposes a kind of preparation method of multilayer circuit board.
Description
Technical field
The present invention relates to a kind of preparation method of circuit board, and more particularly to a kind of preparation method of multilayer circuit board.
Background technology
Typically, circuit board is mainly by multi-layered patterned conductive layer (patterned conductive layer) and more
Be superimposed forms layer dielectric layer (dielectric layer), and utilizes many conductive holes (conductive via) incoming call
Connect these patterned conductive layers.In addition, if being distinguished with regard to the manufacture craft of wiring board, circuit board mainly includes pressing method
(laminating process) and two big type of Layer increasing method (build-up process) wiring board, wherein relatively low wiring is close
The circuit board of degree made with pressing method mostly, and the circuit board of higher wiring density is then generally made with Layer increasing method
Make.
Figure 1A to Fig. 1 H is the Making programme schematic diagram of existing circuit board.As shown in Figure 1A, first, there is provided core substrate
110.Core substrate 110 includes dielectric layer 111 and the conductive layer 112 and 113 of two apparent surfaces positioned at dielectric layer 111.Such as
Shown in Figure 1B, perforation (through hole) 114 is then formed in dielectric layer 111 and conductive layer 112 and 113.Such as Fig. 1 C institutes
Show, blind hole 115 is then formed in conductive layer 112 and dielectric layer 111, and insert conductive material in being led in blind hole 115 to be formed
Electric blind hole 115a (being illustrated in Fig. 1 D).
As shown in figure iD, perforation 114 is then electroplated to form conductive through hole 114a, wherein forming conductive through hole in plating
While 114a, electrodeposited coating is also formed respectively on the surface of conductive layer 112 and 113, and this two electrodeposited coating is belonging respectively to conductive layer
112 and 113.That is, the thickness of conductive layer 112 and 113 shown in Fig. 1 D slightly larger than the conductive layer 112 shown in Figure 1A with
113 thickness.As referring to figure 1E, patterned conductive layer 112 and 113, to form patterned line layer 112a and 113a.Such as Fig. 1 F
It is shown, then to press method or Layer increasing method, stack layer 120a and 120b are respectively formed in patterned line layer 112a and 113a
On, wherein stack layer 120a includes dielectric layer 121a and conductive layer 122a, and stack layer 120b includes dielectric layer 121b and conduction
Layer 122b.
As shown in Figure 1 G, blind hole 123a and 123b are then formed respectively in stack layer 120a and 120b, and insert conduction
Material in blind hole 123a and 123b to form conductive blind hole 124a and 124b.In addition, forming conductive blind hole 124a and 124b
Afterwards, what the surface for the conductive blind hole 124a that electroplated conductive layer 122a is exposed and conductive layer 122b were exposed is conductive blind
Hole 124b surface, while electrodeposited coating is formed respectively on conductive layer 122a and 122b surface, and this two electrodeposited coating is belonging respectively to
Conductive layer 122a and 122b.That is, the thickness of the conductive layer 122a and 122b shown in Fig. 1 G are slightly larger than leading shown in Fig. 1 F
The thickness of electric layer 112 and 113.Finally, as shown in fig. 1H, patterned conductive layer 122a and 122b, to form patterned line layer
125a and 125b.Typically, welding resisting layer (not illustrating) can be formed respectively in patterned line layer 125a and 125b, and is exposed
Local patterned line layer again (can not illustrate welding resisting layer).So far, that is, it is substantially completed the making of circuit board 100.
For the manufacture craft requirement of circuit board 100, the thickness of its core substrate 110 has certain limitation, and unfavorable
In the integral thickness of reduction circuit plate, therefore it is difficult to meet the development trend of circuit board slimming now.On the other hand, when core base
During the thickness excessively thin (such as thickness is less than or equal to 50 microns) of plate 110, the structural strength of core substrate 110 is more insufficient, therefore
In the manufacturing process of circuit board 100, the easily buckling deformation (warpage) by stress of core substrate 110.Wherein, warpage
The core substrate 110 of deformation is easily interferenceed with manufacture craft equipment and causes clamp, is now needed in a manual fashion come before excluding
State the situation of clamp.That is, the preparation method of circuit board 100 is not only difficult to the development trend for meeting slimming, and can not
The line pattern of more granular is produced while the integral thickness of circuit board 100 is reduced, it may have production efficiency and yield
The shortcomings of bad.In addition, the preparation method of circuit board 100 is also dfficult to apply to the system with the circuit board of odd-level line layer
Make.
The content of the invention
The present invention provides a kind of preparation method of multilayer circuit board, and it can be applied to odd-level line layer and even level simultaneously
The manufacture of the multilayer wiring structure of line layer, and manufacture craft efficiency and the thickness of yield and reduction multilayer circuit board can be improved
Degree.Wherein, the preparation method of this multilayer circuit board can produce the ultrathin circuit board of any number of plies, super as ten layers using line layer
Exemplified by the finished product of thin laminate circuit, its thickness can be equal to or less than 500 microns.
The present invention separately provides a kind of preparation method of multilayer circuit board, and it can produce the line pattern of more granular, with
Improve wiring density.
The present invention proposes a kind of preparation method of multilayer circuit board, and it comprises the following steps.First, there is provided metal support plate.
Metal support plate has rough surface.Then, the conductive basal layer of cladding metal support plate is formed, wherein conductive basal layer has relative
First surface and second surface.Then, the first stack layer is pressed respectively on first surface and second surface, wherein each the
One stack layer includes the first dielectric layer and covers the first conductive layer of the first dielectric layer.Then, the second stack layer is pressed respectively
In on each first conductive layer, wherein each second stack layer includes the second dielectric layer and covers the second of the second dielectric layer leading
Electric layer.Then, the edge of conductive basal layer, each first stack layer and each second stack layer is cut, to expose metal
The side surface of support plate, and conductive basal layer is divided into two layerings.Afterwards, each layering and metal support plate are separated.
The present invention separately proposes a kind of preparation method of multilayer circuit board, and it comprises the following steps.First, there is provided metal carries
Plate.Metal support plate has rough surface.Then, the conductive basal layer of cladding metal support plate is formed, wherein conductive basal layer has
Relative first surface and second surface.Then, patterning films are formed respectively on first surface and second surface, wherein respectively
Individual patterning films expose partially electronically conductive basalis.Then, the conductive basal layer that each patterning films are exposed is electroplated,
To form build-up circuit on the conductive basal layer that each patterning films are exposed.Then, each patterning films are removed.
Then, the first stack layer is pressed respectively on first surface and second surface, wherein each first stack layer includes the first dielectric
First conductive layer of the first dielectric layer of layer and covering, and build-up circuit corresponding to each first dielectric layer cladding.Then, cut
The edge of conductive basal layer and each first stack layer, to expose the side surface of metal support plate, and conductive basal layer is divided
For two layerings.Afterwards, each layering and metal support plate are separated.
Preparation method based on above-mentioned, of the invention multilayer circuit board provides the metal support plate with rough surface first,
Then two relative multilayer wiring structures are formed on this metal support plate, wherein this two multilayer wiring structure there can be odd number sandwich circuit
Layer or even level line layer.This two multilayer wiring structure metal support plate can be moved away from since then, in favor of the progress of subsequent manufacturing processes.
Compared to it is existing using core substrate to make the manufacture craft of multilayer circuit board for, the making of multilayer circuit board of the invention
Method can not only improve manufacture craft efficiency and yield, also can effectively reduce the thickness of multilayer wiring structure, to meet slimming
Development trend.In addition, while the integral thickness of multilayer circuit board is reduced, pass through the making of the multilayer circuit board of the present invention
Method can also produce the line pattern of more granular, to improve wiring density.
For features described above of the invention and advantage can be become apparent, special embodiment below, and it is attached appended by cooperation
Figure is described in detail below.
Brief description of the drawings
Figure 1A to Fig. 1 H is the Making programme schematic diagram of existing circuit board；
Fig. 2A to Fig. 2 J is the Making programme schematic diagram of the multilayer circuit board of one embodiment of the invention；
Fig. 3 A to Fig. 3 M are the Making programme schematic diagram of the multilayer circuit board of another embodiment of the present invention；
Fig. 4 A to Fig. 4 J are the Making programme schematic diagram of the multilayer circuit board of another embodiment of the present invention.
Symbol description
100：Circuit board
110：Core substrate
111、121a、121b、122b：Dielectric layer
112、113、122a：Conductive layer
112a、113a、125a、125b：Patterned line layer
114、TH：Perforation
114a、TH1：Conductive through hole
115、123a、123b：Blind hole
115a、124a、124b、BH1、BH2、BH7：Conductive blind hole
120a、120b：Stack layer
200、200A、200B：Multilayer circuit board
210、210a、210b：Metal support plate
211：Side surface
211a：First perforation
212a：First conductive through hole
220：Conductive basal layer
221：First surface
222：Second surface
223、224：Layering
223a：Patterning layering
230、240：First stack layer
231、241：First dielectric layer
232、242：First conductive layer
232a、242a：First line layer
233、243：Alignment mark
233a、243a：First through hole
233b、243b：First conductive through hole
250、260：Second stack layer
251、261：Second dielectric layer
252、262：Second conductive layer
252a、262a：Second line layer
253、263：Second through hole
253a、263a：Second conductive through hole
270、280：3rd stack layer
271、281：3rd dielectric layer
272、282：3rd conductive layer
272a、282a：Tertiary circuit layer
291、292：Patterning films
293、294：Build-up circuit
BH3、BH4：First conductive blind hole
BH5：Second conductive blind hole
BH6：3rd conductive blind hole
D：Diameter
TH2：Second perforation
TH3：Second conductive through hole
Embodiment
Fig. 2A to Fig. 2 J is the Making programme schematic diagram of the multilayer circuit board of one embodiment of the invention.Fig. 2A is refer to, it is first
First, there is provided metal support plate 210.Herein, metal support plate 210 can be stainless steel plate, and be the stainless steel (example of Sprouting resistance
Such as：SUS304) formed, but the invention is not restricted to this.In other embodiments, metal support plate 210 or other are appropriate
Metal material is formed.
In the present embodiment, the thickness of metal support plate 210 is about between 0.1 millimeter to 1.2 millimeters.And in plating metal
Before support plate 210, brushing (brushing) processing can be carried out to metal support plate 210, so that metal support plate 210 has coarse table
Face.Herein, the center line average roughness of rough surface is about between 0.1 micron to 0.6 micron, and 10 points of rough surface
Mean roughness is about between 0.5 micron to 1.5 microns, but the invention is not restricted to this.
As shown in Figure 2 B, such as in a manner of plating, the conductive basal layer 220 of cladding metal support plate 210 is formed, wherein leading
Electric basalis 220 has relative first surface 221 and a second surface 222, and its material is, for example, copper, or tin, silver or
The conducting metals such as gold, the present invention are not any limitation as to this.Because metal support plate 210 has rough surface, therefore conductive base can be made
Bottom 220 is positively combined together with metal support plate 210, but can be by applying appropriate external force with by conductive basal layer 220
Separated with metal support plate 210.
As shown in Figure 2 C, the first stack layer 230 and 240 is pressed respectively on first surface 221 and second surface 222, its
In the first stack layer 230 include the first dielectric layer 231 and cover the first conductive layer 232 of the first dielectric layer 231, and the first heap
Lamination 240 includes the first dielectric layer 241 and covers the first conductive layer 242 of the first dielectric layer 241.Typically, first is situated between
The material of electric layer 231 and 241 can be epoxy resin or the epoxy resin containing glass fibre, and the material of the first conductive layer 232 and 242
Matter can be copper, or the conducting metal such as tin, silver or gold, and the present invention is not any limitation as to this.
As shown in Figure 2 D, alignment mark 233 and 243 can be formed respectively in the by way of exposing (such as ultraviolet light)
One conductive layer 232 and 242.Then, it is contraposition reference using alignment mark 233 and 243, such as comes in a manner of photoetching is with etching
The first conductive layer 232 and 242 is patterned, to form first line layer 232a and 242a respectively.
As shown in Figure 2 E, press respectively the second stack layer 250 and 260 in patterning the first conductive layer 232 and 242 (also
That is first line layer 232a and 242a) on, wherein the second stack layer 250 includes the second dielectric of the second dielectric layer 251 and covering
Second conductive layer 252 of layer 251, and the second stack layer 260 includes the second dielectric layer 261 and covers the second dielectric layer 261
Second conductive layer 262.Typically, the material of the second dielectric layer 251 and 261 can be epoxy resin or the epoxy containing glass fibre
Resin, and the material of the second conductive layer 252 and 262 can be copper, or the conducting metal such as tin, silver or gold, the present invention to this not
It is any limitation as.In addition, the width of the first dielectric layer 231 and 241 and the second dielectric layer 251 and 261 is all higher than metal support plate 210
Width.
As shown in Figure 2 F, such as in a manner of grinding or be cut by laser, conductive basal layer 220, the first stack layer 230 are cut
With 240 and second stack layer 250 and 260 edge, that is, conductive basal layer 220, the first stack layer 230 and 240 and
The part of the side surface 211 for the metal support plate 210 that two stack layers 250 and 260 exceed, to expose side surface 211, and by conduction
Basalis 220 is divided to for two layerings 223 and 224.
There is certain adhesion between layering 223 and metal support plate 210 and between layering 224 and metal support plate 210,
But layering 223 and metal support plate 210 and layering 223 can be separated with metal support plate 210 by applying appropriate external force
Come, as shown in Figure 2 G.Thus, after layering 223 and 224 is removed from metal support plate 210, the rough surface of metal support plate 210 is not
Residue can be left, and the center line average roughness of rough surface or 10 mean roughness still may conform to foregoing manufacture craft
It is required that so that metal support plate 210 is reusable.On the other hand, also can be before metal support plate 210 be reused, in advance really
Whether the surface roughness for recognizing the rough surface of metal support plate 210 still conforms to specification, and such as otherwise metal support plate 210 can be applied again
Handled with brushing (brushing), so that the surface roughness of rough surface is recovered to the number range of foregoing manufacture craft requirement
It is interior.
As illustrated in figure 2h, such as with X-ray drill (X-ray drilling), laser drill (laser drilling) or machine
The mode of tool drilling (mechanical drilling), formed through layering 223 and stacked the first dielectric layer 231 thereon,
First line layer 232a, the second dielectric layer 251 and the second conductive layer 252 perforation TH.Herein, perforation TH be, for example, through pair
Position mark 233 is in first line layer 232a position, but the invention is not restricted to this.In the embodiment not illustrated, also may be used
Drilled, in a manner of laser drill or machine drilling, formed through layering 224 and stacked the first dielectric layer thereon by X-ray
241st, first line layer 242a, the second dielectric layer 261 and the second conductive layer 262 perforation.Following manufacture craft will be with layering
223rd, the multilayer wire that the first dielectric layer 231, first line layer 232a, the second dielectric layer 251 and the second conductive layer 252 are formed
Line structure is further described, wherein layering the 224, first dielectric layer 241, first line layer 242a, the second dielectric layer 261 with
And second the Making programme of multilayer wiring structure that is formed of conductive layer 262 can refer to execution with principle, just repeated no more in this.
As shown in figure 2i, electrical connection layering 223 and first line layer 232a multiple conductive blind hole BH1 are formed and are electrically connected
Multiple conductive blind hole BH2 of first line layer 232a and the second conductive layer 252 are met, and electroplate perforation TH to form conductive through hole
TH1.Typically, the embodiment of this making step be, for example, first respectively layering 223 and first in dielectric layer 231 with
And second dielectric layer 251 and the second conductive layer 252 form multiple blind holes, and insert conductive material in these blind holes with shape respectively
Into these conductive blind holes BH1 and these conductive blind holes BH2.Then, while perforation TH is electroplated to form conductive through hole TH1,
Also form electrodeposited coating respectively in layering 223 and the surface of the second conductive layer 252, and this two electrodeposited coating be belonging respectively to layering 223 and
Second conductive layer 252.That is, the thickness of the conductive layer 252 of layering 223 and second shown in Fig. 2 I is slightly larger than shown in Fig. 2 H
The thickness of the conductive layer 252 of layering 223 and second.
Afterwards, as shown in fig. 2j, it is contraposition reference using conductive through hole TH1, such as in a manner of photoetching is with etching, to scheme
Caseization layering 223 and the second conductive layer 252 are layered 223a and the second line layer 252a to form patterning respectively.Typically,
Welding resisting layer (not illustrating) can be respectively formed in patterning layering 223a and the second line layer 252a again, and expose local figure
Caseization is layered 223a and the second line layer 252a, that is, is substantially completed the making of multilayer circuit board 200.
In short, the making of multilayer circuit board 200 is illustrated by three layers of multilayer wiring structure of the number of plies of line layer
It is bright, wherein based on this multilayer wiring structure, the number of plies of line layer can be further produced using pressing method or Layer increasing method
Multilayer wiring structure for odd number and more than three layers.Compared to it is existing using core substrate to make the making work of multilayer circuit board
For skill, the preparation method of multilayer circuit board 200 can not only improve manufacture craft efficiency and yield, also can effectively reduce multilayer wire
The thickness of line structure, to meet the development trend of slimming.
Other embodiment will be enumerated below to be used as explanation.It should be noted that, following embodiments continue to use foregoing reality herein
The element numbers and partial content of example are applied, wherein adopting the identical or approximate element that is denoted by the same reference numerals, and are eliminated
The explanation of constructed content.Explanation on clipped refers to previous embodiment, and it is no longer repeated for following embodiments.
Fig. 3 A to Fig. 3 M are the Making programme schematic diagram of the multilayer circuit board of another embodiment of the present invention.Refer to Fig. 3 A with
Fig. 3 B, first, there is provided metal support plate 210a, and for example drilled by X-ray, in a manner of laser drill or machine drilling in metal support plate
210a forms the first perforation 211a, wherein the first perforation 211a diameter D is 3.5 ± 0.2 microns.And for example with the side of plating
Formula is come after forming cladding metal support plate 210a conductive basal layer 220, the first perforation 211a can form the first conductive through hole
212a。
As shown in Figure 3 C, the first stack layer 230 and 240 is pressed respectively in the first surface 221 of conductive basal layer 220 and
On two surfaces 222, wherein the first stack layer 230 includes the first dielectric layer 231 and covers the first conduction of the first dielectric layer 231
Layer 232, and the first stack layer 240 includes the first dielectric layer 241 and covers the first conductive layer 242 of the first dielectric layer 241.Connect
, such as drilled, in a manner of laser drill or machine drilling by X-ray, form the first through hole 233a through the first stack layer 230
And the first through hole 243a through the first stack layer 240, wherein first through hole 233a and 243a are respectively communicated with the first conduction and passed through
Hole 212a.
As shown in Figure 3 D, it is contraposition reference using first through hole 233a and 243a, such as comes in a manner of photoetching is with etching
The first conductive layer 232 and 242 is patterned, to form first line layer 232a and 242a respectively.Then, first through hole 233a is electroplated
With 243a to form the first conductive through hole 233b and 243b respectively, wherein the first conductive through hole 233b and 243b are electrically connected the
One conductive through hole 212a.
As shown in FIGURE 3 E, press respectively the second stack layer 250 and 260 in patterning the first conductive layer 232 and 242 (also
That is first line layer 232a and 242a) on, wherein the second stack layer 250 includes the second dielectric of the second dielectric layer 251 and covering
Second conductive layer 252 of layer 251, and the second stack layer 260 includes the second dielectric layer 261 and covers the second dielectric layer 261
Second conductive layer 262.Then, such as by X-ray drill, in a manner of laser drill or machine drilling, formation runs through the second stack layer
250 the second through hole 253 and the second through hole 263 through the second stack layer 260, wherein the second through hole 253 connection first is led
Electric through-hole 233b, and the second through hole 263 connects the first conductive through hole 243b.
As illustrated in Figure 3 F, multiple first conductive blind holes of electrical connection first line layer 232a and the second conductive layer 252 are formed
BH3 and multiple first conductive blind hole BH4 of electrical connection first line layer 242a and the second conductive layer 262, and it is logical to electroplate second
Hole 253 and 263 to form the second conductive through hole 253a and 263a respectively, wherein the second conductive through hole 253a electrical connections first are conductive
Through hole 233b, and the second conductive through hole 263a electrically connects the first conductive through hole 243b.
As shown in Figure 3 G, it is contraposition reference using the second conductive through hole 253a and 263a, such as the side with photoetching and etching
Formula, to pattern the second conductive layer 252 and 262 to form the second line layer 252a and 262a respectively.Then, as shown in figure 3h,
The 3rd stack layer 270 and 280 is pressed respectively on the second line layer 252a and 262a, wherein the 3rd stack layer 270 includes the 3rd
Dielectric layer 271 and the 3rd conductive layer 272 for covering the 3rd dielectric layer 271, and the 3rd stack layer 280 includes the 3rd dielectric layer
281 and cover the 3rd dielectric layer 281 the 3rd conductive layer 282.
As shown in fig. 31, such as in a manner of grinding or be cut by laser, conductive basal layer 220, the first stack layer 230 are cut
With the 240, second stack layer 250 and 260 and the edge of the 3rd stack layer 270 and 280, that is, conductive basal layer 220, the first heap
The side table for the metal support plate 210a that lamination 230 and 240, the second stack layer 250 and 260 and the 3rd stack layer 270 and 280 exceed
The part in face 211, to expose side surface 211, and conductive basal layer 220 is divided to for two layerings 223 and 224.Then, can lead to
Cross and apply appropriate external force so that layering 223 and metal support plate 210a and layering 223 to be separated with metal support plate 210a, such as
Shown in Fig. 3 J.
Drill, in a manner of laser drill or machine drilling, formed through layering 223 with folding as shown in Fig. 3 K, such as by X-ray
First dielectric layer 231 placed on it, first line layer 232a, the second dielectric layer 251, the second line layer 252a, the 3rd dielectric
Second perforation TH2 of the conductive layer 272 of layer 271 and the 3rd., can also X-ray drilling, laser drill in the embodiment not illustrated
Or the mode of machine drilling, formed through layering 224 and stacked the first dielectric layer 241 thereon, first line layer 242a, the
Two dielectric layers 261, the second line layer 262a, the second perforation of the 3rd dielectric layer 281 and the 3rd conductive layer 282.Make below
Technique will be to be layered the 223, first dielectric layer 231, first line layer 232a, the second dielectric layer 251, the second line layer 252a, the
The multilayer wiring structure that three dielectric layers 271 and the 3rd conductive layer 272 are formed is further described, wherein layering 224, the
One dielectric layer 241, first line layer 242a, the second dielectric layer 261, the second line layer 262a, the 3rd dielectric layer 281 and the 3rd
The Making programme for the multilayer wiring structure that conductive layer 282 is formed can refer to execution with principle, just be repeated no more in this.
As shown in figure 3l, formed electrical connection layering 223 and first line layer 232a multiple second conductive blind hole BH5 and
Electrically connect multiple 3rd conductive blind hole BH6 of the second line layer 262a and the 3rd conductive layer 272, and electroplate the second perforation TH2 with
Form the second conductive through hole TH3.Afterwards, as shown in fig.3m, it is contraposition reference using the second conductive through hole TH3, such as with photoetching
With the mode of etching, 223a and the second line layer are layered to pattern 223 the 3rd conductive layers 272 of layering to form patterning respectively
272a.Typically, welding resisting layer (not illustrating) can be respectively formed in patterning layering 223a and the second line layer 272a again, and
Local patterning layering 223a and the second line layer 272a is exposed, that is, is substantially completed multilayer circuit board 200A making.
In short, multilayer circuit board 200A making is illustrated by four layers of multilayer wiring structure of the number of plies of line layer
It is bright, wherein based on this multilayer wiring structure, the number of plies of line layer can be further produced using pressing method or Layer increasing method
Multilayer wiring structure for even number and more than four layers.Be compared to it is existing using core substrate to make the making of multilayer circuit board
For technique, multilayer circuit board 200A preparation method can not only improve manufacture craft efficiency and yield, also can effectively reduce more
The thickness of layer line line structure, to meet the development trend of slimming.For example, the preparation method of this multilayer circuit board can make
The ultrathin circuit board of any layers number is taken the post as, by taking the finished product for the ultrathin circuit board that line layer is ten layers as an example, its thickness can be equal to or small
In 500 microns.
Fig. 4 A to Fig. 4 J are the Making programme schematic diagram of the multilayer circuit board of another embodiment of the present invention.Refer to Fig. 4 A with
Fig. 4 B, first, there is provided metal support plate 210b, and for example in a manner of plating, form cladding metal support plate 210b conductive substrates
Layer 220, wherein conductive basal layer 220 have relative first surface 221 and second surface 222.Then, such as Fig. 4 C to Fig. 4 E institutes
Show, negative film transfer (subtractive transfer) is carried out respectively at first surface 221 and second surface 222.First, respectively
Patterning films 291 and 292 are formed on first surface 221 and second surface 222, wherein patterning films 291 and 292 are distinguished
Expose partially electronically conductive basalis 220.Typically, fabricating patterned film layer 291 with 292 specific embodiment party be, for example, pass through
Heat pressure roller fits in photosensitive dry film on first surface 221 and second surface 222, afterwards can using the mode of exposure imaging come
Part photosensitive dry film is removed to define patterning films 291 and 292.Then, plated pattern film layer 291 and 292 exposes
The conductive basal layer 220 gone out, to form the conductive basal layer 220 that build-up circuit 293 is exposed in patterning films 291 respectively
And the conductive basal layer 220 that build-up circuit 294 is exposed in patterning films 292.Herein, build-up circuit 293 and 294
Material can be copper, or the conducting metal such as tin, silver or gold, and the present invention is not any limitation as to this.Afterwards, patterning films are removed
291 and 292, now, first surface 221 has been substantially completed with the configuration (layout) on second surface 222.
As illustrated in figure 4f, the first stack layer 230 and 240 is pressed respectively on first surface 221 and second surface 222, its
In the first stack layer 230 include the first dielectric layer 231 and cover the first conductive layer 232 of the first dielectric layer 231, and the first heap
Lamination 240 includes the first dielectric layer 241 and covers the first conductive layer 242 of the first dielectric layer 241.In addition, the first dielectric layer
231 also coat build-up circuit 293, and the first dielectric layer 241 also coats build-up circuit 294.Then, as shown in Figure 4 G, cutting is led
The edge of the electric stack layer 230 and 240 of basalis 220 and first, that is, the stack layer 230 of conductive basal layer 220 and first with
The part of the 240 metal support plate 210b exceeded side surface 211, to expose side surface 211, and conductive basal layer 220 is divided
For two layerings 223 and 224.Then, 223 and metal support plate 210a and layering will can be layered by applying appropriate external force
223 separate with metal support plate 210a, as shown at figure 4h.
Following manufacture craft will be with layering 223, build-up circuit 293, the first dielectric layer 231 and the institute of the first conductive layer 232
The double-deck line construction of composition is further described, wherein layering 224, build-up circuit 294, the first dielectric layer 241 and the
The Making programme for the double-deck line construction that one conductive layer 242 is formed can refer to execution with principle, just be repeated no more in this.Such as figure
Shown in 4I, electrical connection layering 223 and the conductive blind hole BH7 of build-up circuit 293 are formed.Afterwards, the conductive layer 232 of patterning first with
Layering 223, to form first line layer 232a and patterning layering 223a respectively, wherein patterning layering 223a covering parts
Build-up circuit 293, as shown in fig. 4j.Typically, welding resisting layer (not illustrating) can be respectively formed in patterning layering 223a again
With first line layer 232a, and local patterning layering 223a and first line layer 232a is exposed, that is, be substantially completed multilayer
Circuit board 200B making.
On the other hand, in other feasible embodiments, also visual actual design demand, is patterning the first conductive layer
232 with layering 223 during, will entirely be layered 223 etchings removal, that is, will not have on the first dielectric layer 231 such as Fig. 4 J
Shown patterning layering 223a, so as to expose all build-up circuits 293.
In short, multilayer circuit board 200B making is for example, wherein by above-mentioned making with double-deck line construction
Double-deck line construction obtained by flow while integral thickness is reduced, can produce the line pattern of more granular, to improve
Wiring density.Here, the line width of the line pattern of granular and line-spacing (line/space) are smaller than in multilayer circuit board 200B
Equal to 40 microns/40 microns.
In summary, the preparation method of multilayer circuit board of the invention provides the metal support plate with rough surface first,
Then two relative multilayer wiring structures are formed on this metal support plate, wherein this two multilayer wiring structure there can be odd number sandwich circuit
Layer or even level line layer.This two multilayer wiring structure metal support plate can be moved away from since then, in favor of the progress of subsequent manufacturing processes.
Compared to it is existing using core substrate with the manufacture craft of the multilayer circuit board made for, the system of multilayer circuit board of the invention
Manufacture craft efficiency and yield can not only be improved by making method, also can effectively reduce the thickness of multilayer wiring structure, slim to meet
The development trend of change.In addition, while the integral thickness of multilayer circuit board is reduced, pass through the system of the multilayer circuit board of the present invention
The line pattern of more granular can also be produced by making method, to improve wiring density.
Although the present invention is disclosed with reference to above example, but it is not limited to the present invention, any affiliated technology
Have usually intellectual in field, without departing from the spirit and scope of the present invention, a little change and retouching can be made, therefore this hair
Bright protection domain should be defined by what the claim enclosed was defined.
Claims (20)
1. a kind of preparation method of multilayer circuit board, including：
A metal support plate is provided, wherein the metal support plate has a rough surface；
The conductive basal layer for coating the metal support plate is formed, the wherein conductive basal layer has relative first surface and second
Surface；
One first stack layer is pressed respectively on the first surface and the second surface, wherein respectively first stack layer includes one the
One dielectric layer and one first conductive layer for covering first dielectric layer；
One second stack layer is pressed respectively in respectively on first conductive layer, wherein respectively second stack layer include the second dielectric layer with
And cover the second conductive layer of second dielectric layer；
The conductive basal layer, respectively first stack layer and the respectively edge of second stack layer are cut, to expose metal load
The side surface of plate, and the conductive basal layer is divided into two layerings；And
Separate the respectively layering and the metal support plate.
2. the center line average roughness of the preparation method of multilayer circuit board as claimed in claim 1, the wherein rough surface
Between 0.1 micron to 0.6 micron.
3. 10 mean roughness of the preparation method of multilayer circuit board as claimed in claim 1, the wherein rough surface are situated between
Between 0.5 micron to 1.5 microns.
4. the preparation method of multilayer circuit board as claimed in claim 1, the wherein metal support plate are stainless steel plate.
5. the thickness of the preparation method of multilayer circuit board as claimed in claim 1, the wherein metal support plate between 0.1 millimeter extremely
Between 1.2 millimeters.
6. the preparation method of multilayer circuit board as claimed in claim 1, wherein respectively first dielectric layer and respectively second dielectric
The width of layer is more than the width of the metal support plate.
7. the preparation method of multilayer circuit board as claimed in claim 1, wherein pressing second stack layer respectively in respectively should
Before on first conductive layer, in addition to：
A contraposition is formed respectively is marked on respectively first conductive layer；And
Using the respectively alignment mark be contraposition reference pattern respectively first conductive layer to form a first line layer.
8. the preparation method of multilayer circuit board as claimed in claim 7, in addition to：
Formed through each layering and stacked first dielectric layer thereon, the first line layer, second dielectric layer and
One perforation of second conductive layer；
Formed electrical connection respectively the layering and the corresponding first line layer and electrical connection respectively the first line layer with it is corresponding this
Multiple conductive blind holes of second conductive layer, and the perforation is electroplated to form a conductive through hole；And
The respectively layering is patterned with respectively second conductive layer to form a pattern respectively using the conductive through hole is contraposition reference
Change layering and one second line layer.
9. the preparation method of multilayer circuit board as claimed in claim 1, the wherein metal support plate have the first perforation, and in shape
After into the conductive basal layer for coating the metal support plate, first perforation forms one first conductive through hole.
10. a diameter of the 3.5 ± 0.2 of the preparation method of multilayer circuit board as claimed in claim 9, wherein first perforation are micro-
Rice.
11. the preparation method of multilayer circuit board as claimed in claim 9, wherein press respectively respectively second stack layer in right
Before on first conductive layer answered, in addition to：
The first through hole through each first stack layer is formed, wherein respectively the first through hole is respectively communicated with first conduction and passed through
Hole；And
Using the respectively first through hole be contraposition reference come pattern respectively first conductive layer to form a first line layer respectively, and
Plating respectively the first through hole to form one first conductive through hole respectively, wherein respectively first conductive through hole be electrically connected this first
Conductive through hole.
12. the preparation method of multilayer circuit board as claimed in claim 11, wherein cut the conductive basal layer, respectively this first
Before stack layer and the respectively edge of second stack layer, in addition to：
One second through hole through respectively second stack layer is formed, wherein respectively first conduction is logical corresponding to second through hole connection
Hole；
Form multiple first conductive blind holes of electrical connection respectively the first line layer and corresponding second conductive layer, and electroplate respectively this
Second through hole to form one second conductive through hole respectively, wherein respectively first conduction is logical corresponding to second conductive through hole electrical connection
Hole；
Using respectively second conductive through hole be contraposition reference pattern respectively second conductive layer to form one second circuit respectively
Layer；And
One the 3rd stack layer is pressed respectively in respectively on second line layer, wherein respectively the 3rd stack layer include the 3rd dielectric layer with
And cover the 3rd conductive layer of the 3rd dielectric layer, and cut the conductive basal layer, respectively first stack layer and respectively this
While the edge of two stack layers, the edge of respectively the 3rd stack layer is cut.
13. the preparation method of multilayer circuit board as claimed in claim 12, wherein separating the respectively layering and the metal support plate
Afterwards, in addition to：
Formed through each layering and stacked first dielectric layer thereon, the first line layer, second dielectric layer, this
One second perforation of two line layers, the 3rd dielectric layer and the 3rd conductive layer；
Formed electrical connection respectively multiple second conductive blind holes of the layering and the corresponding first line layer and electrically connect respectively this
Multiple 3rd conductive blind holes of two line layers and corresponding 3rd conductive layer, and electroplate second perforation and led with forming one second
Electric perforation；And
The respectively layering is patterned with respectively the 3rd conductive layer to form one respectively using second conductive through hole is contraposition reference
Patterning layering and a tertiary circuit layer.
14. a kind of preparation method of multilayer circuit board, including：
A metal support plate is provided, wherein the metal support plate has a rough surface；
The conductive basal layer for coating the metal support plate is formed, the wherein conductive basal layer has relative first surface and second
Surface；
A patterning films are formed respectively on the first surface and the second surface, wherein respectively the patterning films expose respectively
Go out the part conductive basal layer；
Plating conductive basal layer that respectively patterning films are exposed, to form a build-up circuit in the respectively patterning films
On the conductive basal layer exposed；
Remove the respectively patterning films；
One first stack layer is pressed respectively on the first surface and the second surface, wherein respectively first stack layer includes one the
One dielectric layer and one first conductive layer for covering first dielectric layer, and respectively increasing layer line corresponding to first dielectric layer cladding
Road；
The conductive basal layer and the respectively edge of first stack layer are cut, to expose the side surface of the metal support plate, and will
The conductive basal layer is divided into two layerings；And
Separate the respectively layering and the metal support plate.
15. the center line average roughness of the preparation method, the wherein rough surface of multilayer circuit board as claimed in claim 14
Degree is between 0.1 micron to 0.6 micron.
16. 10 mean roughness of the preparation method of multilayer circuit board as claimed in claim 14, the wherein rough surface
Between 0.5 micron to 1.5 microns.
17. the preparation method of multilayer circuit board as claimed in claim 14, the wherein metal support plate are stainless steel plate.
18. the thickness of the preparation method of multilayer circuit board as claimed in claim 14, the wherein metal support plate is between 0.1 millimeter
To between 1.2 millimeters.
19. the preparation method of multilayer circuit board as claimed in claim 14, wherein respectively the width of first dielectric layer is more than this
The width of metal support plate.
20. the preparation method of multilayer circuit board as claimed in claim 14, wherein separation respectively the layering and metal support plate it
Afterwards, in addition to：
Form the conductive blind hole for electrically connecting the respectively layering and the corresponding build-up circuit；And
Patterning respectively first conductive layer and respectively layering, it is layered with forming a first line layer and a patterning respectively.
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