TW201228509A - Circuit board and manufacturing method thereof - Google Patents

Abstract

A method of fabricating a circuit board is provided. A carrier is provided. A first conductive layer and a second conductive layer are formed on the two corresponding surfaces of the carrier, respectively. At least a first conductive pillar and at least a second conductive pillar are formed on the first conductive layer and the second conductive layer, respectively. A first laminated structure and a second laminated structure are laminated on the first conductive layer and the second conductive layer, respectively. A portion of the first laminated structure and a portion of the second laminated structure are removed to expose the first conductive pillar and the second pillar, respectively. A third conductive layer is formed on the residual first laminated structure and the first conductive pillar, and a fourth conductive layer is formed on the residual second laminated structure and the second conductive pillar. The carrier is removed.

Description

201228509u- VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a circuit board and a process thereof, and in particular to a circuit board having a better reliability and a process thereof. [Prior Art] Currently, a wafer package carrier is one of the frequently used package components in a semiconductor process. The chip package carrier is, for example, a multilayer circuit board, which is mainly composed of a plurality of circuit layers and a plurality of dielectric layers alternately stacked, wherein the dielectric layer is disposed between any two adjacent circuit layers, and the circuit layer can be The electrodes are electrically connected to each other through a via hole (pTH) or a via hole penetrating through the dielectric layer. Since the chip package carrier has the advantages of fine wiring, compact assembly, and good performance, it has become the mainstream of the chip package structure. In general, the wiring structure of a multilayer wiring board is mostly manufactured by a buildup method or an iaminated method, and thus has a high line density and a reduced line pitch. Ultra-thin substrates must be provided with a carrier as a support carrier due to insufficient rigidity. Next, the release layer is sequentially formed on the opposite side surfaces of the carrier with the plurality of dielectric layers forming the multilayer wiring layer and alternately arranged with the wiring layer. Finally, the interface between the release layer and the circuit layer thereon is separated from the carrier and the two multilayer boards are separated from each other. In addition, if a via hole or a conductive hole is to be formed, after forming a dielectric layer, for example, by laser, 201228509

Jj / /ytwi.doc/I Drilling method to form a blind hole, and then by plating the square tape, this; | circuit layer below the electrical layer. Forming another line layer and a ^ steel layer in the blind hole and the dielectric layer, but 'there is no dielectric layer in the electroplating hole, and the blind blind hole formed by the laser drilling method The upper steel is filled with steel to plug the hole. In order to avoid the need to first increase the number of copper thick products, the existing process steps to achieve a flat frequency after the step, plus the step of reducing the thickness of the copper to increase the plating between the two: J and:: Copper syrup to slow the copper plating speed is higher by the laser coffee I and the process is also inclined (four). In addition, the process and the hole formed by the electric hole are formed by the electric (four) hole, and the density of the blind hole is not easily improved, and the shape of the blind hole is favorable for forming a linear or green bump, so the upper shape The process is not easy to reach, the signal interference isolation required for the south frequency line and the thermal function required for the high power chip. SUMMARY OF THE INVENTION The present invention provides a circuit board and a method of fabricating the same, which can improve process yield and reduce manufacturing cost, thereby increasing product reliability. The present invention provides a method of fabricating a wiring board, wherein the manufacturing method comprises the following steps. A carrier board is provided. The carrier plate includes a first release layer, a second release layer, and a core layer disposed between the first release layer and the second release layer. A first conductive layer and a second conductive layer are respectively formed on the first release layer and the second release layer of the carrier. Form at least - first

201228509 t ▼▼ a.doc/I The conductive pillar and the at least one second conductive pillar are on the first conductive layer and the second conductive layer. The first conductive pillar and the first conductive layer have a first interface, and the second conductive pillar and the second conductive layer have a second interface. A first laminate structure and a second laminate structure are respectively laminated on the first conductive layer and the second conductive layer. The first laminate structure covers the first conductive pillar and a portion of the first conductive layer, and the second laminate structure covers the second conductive pillar and a portion of the second conductive layer. A portion of the first laminate structure and a portion of the second laminate structure are separately removed to expose the first conductive pillar and the second conductive pillar. A third conductive layer and a fourth conductive layer are respectively formed on the remaining first stacked structure and the first conductive pillar and on the remaining second laminated structure and the second conductive pillar. The third conductive layer and the first conductive pillar have a third interface, and the fourth conductive layer and the second conductive pillar have a fourth interface. The carrier plate is removed by a stripping force to separate the interface between the first conductive layer and the first release layer and the interface between the second conductive layer and the second release layer. In an embodiment of the invention, the first laminate structure comprises a first insulating layer, a first thin metal layer and a first thick metal layer. The first thin metal layer is between the first insulating layer and the first thick metal, and the first insulating layer covers the first conductive pillar and a portion of the first conductive layer. The second laminate structure includes a second insulating layer, a second thin metal layer, and a second thick metal layer. The second thin metal layer is between the second insulating layer and the second thick metal, and the second insulating layer covers the second conductive pillar and a portion of the second conductive layer. In one embodiment of the invention, the step of removing a portion of the first laminate structure and a portion of the second laminate structure includes the following steps. Removing the first thick metal layer and the second thick metal layer to expose the first thin metal layer

Aoc/I 201228509 and second thin metal layer. Removing a portion of the first thin metal layer and a portion of the second thin metal layer to expose the first conductive pillar and the second conductive pillar to respectively form a first annular conductive layer surrounding the first conductive pillar and the second conductive pillar; a second annular conductive layer. In one embodiment of the invention, the above method of removing the first thick metal layer and the second thick metal layer includes a lift-off method. In one embodiment of the invention, the method of forming a portion of the first thin metal layer and a portion of the second thin metal layer comprises a grinding process. In one embodiment of the invention, the method of forming the first conductive pillar and the second conductive pillar includes electroplating. In an embodiment of the invention, the first laminate structure includes a first insulating layer and a first thin metal layer. The first thin metal layer is on the first insulating layer, and the first insulating layer covers the first conductive pillar and a portion of the first conductive layer. The second laminate structure includes a second insulating layer and a second thin metal layer. The second thin metal layer is on the second insulating layer, and the second insulating layer covers the second conductive pillar and a portion of the second conductive layer. In an embodiment of the invention, the step of removing a portion of the first laminate structure and a portion of the second laminate structure includes removing a portion of the first thin metal layer and a portion of the second thin metal layer to expose The first conductive pillar and the second conductive pillar respectively form a first annular conductive layer and a second annular conductive layer surrounding the first conductive pillar and the second conductive pillar. In one embodiment of the invention, the method of forming a portion of the first thin metal layer and a portion of the second thin metal layer comprises a grinding process. In an embodiment of the invention, the first release layer and the second separation

• doc/I 201228509 The shape of the layer is made of conductive paste or cut non-conductive glue. In the embodiment of the present invention, the material of the first release layer and the second release layer is recorded, and the material of the core layer is copper or stainless steel. In the embodiment of the present invention, the method for fabricating the above-mentioned circuit board further comprises: prior to removing the carrier plate, the fine layer is formed on the laminated structure and the second laminated structure. In the present invention, in the above method (4), the first conductive layer and the second conductive layer formed on the carrier-the first release layer and the second release layer are a (four) conductive layer. And patterning the third conductive layer before separating the carrier plate by separating the force channel to separate the interface between the first conductive layer and the first release layer and the interface between the second conductive layer and the second release layer And a fourth conductive layer to form a third patterned conductive layer and a fourth patterned conductive layer. In the present invention, the method for fabricating the above-mentioned circuit board further includes separating the interface between the first conductive layer and the first release layer and the second conductive layer and the second release layer by peeling the force path After the interface is removed, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are patterned to form a first patterned conductive layer and a second patterned conductive layer. a layer, a second patterned conductive layer and a fourth patterned conductive layer. The present invention provides a circuit board comprising a first patterned conductive layer, a conductive pillar, a tantalum insulating layer and a second patterned conductive layer. The conductive iridium is disposed on the first patterned conductive layer, wherein the conductive pillar and the first patterned conductive layer have a first interface. The insulating layer is disposed on the first patterned conductive layer and encloses the side of the conductive pillar. The second patterned conductive layer is disposed on

A〇c/I 201228509 The conductive pillar and the insulating layer, wherein the second patterned conductive layer and the conductive main body have a second interface, and the second patterned conductive layer is electrically connected to the 图案 patterned conductive layer through the conductive 桎. In an embodiment of the invention, the circuit board further includes a conductive layer disposed around the conductive pillar and located between the insulating layer and the first pattern “layer. The conductive layer is based on the above, the circuit board of the present invention is The conductive layer is electrically connected to the conductive layer 284, and then the laminated structure is further pressed and the partial stack is removed; the conductive pillar is formed, and then the conductive layer is formed by means of electric ore, which is earlier than the prior art. A blind via is formed in the dielectric layer, and then a via hole is formed in the blind via and a wiring layer is formed on the dielectric layer. The method for fabricating the wiring board of the present invention can improve the conductive layer and the conductive layer. The yield is reduced and the production cost is reduced, thereby increasing the reliability of the product. In addition, the invention can form the conductive pillar as a linear or block bump to facilitate the signal isolation and heat dissipation functions of the high frequency and high power wafer. The above features and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the invention. Referring to FIG. 1 , in the embodiment, the circuit board 100 includes a second patterned conductive layer 11G, a conductive pillar 12 〇, an insulating layer 13 ( ), and a first The conductive layer 14 is patterned. In detail, the conductive pillar 12 is disposed on the first patterned conductive layer 1U, wherein the conductive pillar 12Q and the first patterned conductive layer 110 have a first interface S1. 13〇 is disposed on the first patterned conductive layer 110 and surrounds the side of the conductive pillar 12〇. The second patterned conductive layer 140 is disposed on the conductive pillar 12〇 and the insulating layer 130, wherein the second patterned conductive layer 140 is A second interface S2 ′ is disposed between the conductive pillars 12 且 and the second patterned conductive layer M 〇 is electrically connected to the first patterned conductive layer 110 through the conductive pillars 12 。. In addition, the circuit board of the embodiment 1 〇〇 Furthermore, an annular conductive layer 150 ′ is disposed, wherein the annular conductive layer 15 is disposed around the conductive pillar 120 and located between the insulating layer 13 〇 and the first patterned conductive layer 11 。. Details will be described below with reference to FIGS. 2A to 21 . The method of manufacturing the circuit board 100 will be described. In this embodiment, the same reference numerals are used to refer to the same or similar elements. FIG. 2A to FIG. 21 show the circuit board of one embodiment of the present invention in cross section. Referring to FIG. 2A, firstly, a carrier board 1 is provided, wherein the carrier board 10 includes a first release layer 12, a second release layer 14 and a first-destructive layer 12 and a first The core layer 16 between the two release layers 14. In this embodiment, the material of the first release layer 12 and the second release layer 14 is, for example, a cut conductive paste or a non-conductive paste containing material; or The material of the first and the release layer 12 and the second release layer 14 is, for example, nickel, and the material of the core layer 16 is, for example, steel or non-sense, which is not limited herein. Next, referring to FIG. 2B, a first conductive layer 110a and a second conductive layer are respectively formed on the (four) plane 0 of the carrier board 1G, wherein the first conductive layer 110a covers the first release layer 12, and the second conductive layer is wide. U〇b 201228509

/ / yiwi.doc / I covers the second release layer 14 . In the present embodiment, the method of forming the first conductive layer u〇a and the second conductive layer 10b is, for example, an electroplating method. It should be noted that the present invention does not limit the structural form of the first conductive layer 11a and the second conductive layer U〇b, although the first conductive layer 110a and the second conductive layer 11 mentioned herein are b is embodied to completely cover the first release layer 12 and the first release layer 14. However, in other embodiments not shown, the first conductive layer 110a and the second conductive layer 11B may only partially cover the first and second release layers 12 and 14. That is, the first conductive ϋΞ second conductive layer 110b is a patterned conductive layer, respectively. Therefore, the structural forms of the first conductive layer U0a and the second conductive layer 110b illustrated in FIG. 2A are merely illustrative and are not limited thereto. Next, please refer to FIG. 2C, respectively forming at least one first conductive pillar 12〇a (only one schematically in FIG. 2C) and at least one second conductive pillar 120b (only one schematically in FIG. 2C). A conductive layer 1 is on the upper and second conductive layers 11b. In particular, in the embodiment, the first conductive layer 12a has a first interface si between the first conductive layer n〇a, and the second conductive pillar 120b and the second conductive layer 110b have a first interface Second interface =. In addition, in the embodiment, the step of forming the first conductive pillars 12 amp & and the second voltaic pillars 120 b includes forming a patterned photoresist layer (not shown) by exposure and development, and then performing the electroplating method. Electroplating a conductive layer / not shown on the first conductive layer 11a and the second conductive layer ii 〇 b, and then removing the patterned photoresist layer to complete the first conductive pillar 12 〇 a and the second V Production of electric column 12〇b. In particular, the embodiment does not limit the shape of the first conductive pillar 120a and the second conductive pillar, and may be, for example, a line or a block.

Aoc/I 201228509 = can reduce the isolation and interconnection required for 1^ frequency and high power wafers, 'please refer to FIG. 2D to provide a first stacked structure 130a and a second and second layer structure 13Gb at the first conductive In the layer_upper and second conductive layers, the first stacked structure 130a includes a first insulating layer: a first thin metal layer 134a and a first thick metal layer 136a' Z / a metal layer 13 The first insulating layer 132a is between the first thick gold 3. The second stacked structure 13Gb includes a second insulating layer, a first thin metal layer 134b, and a second thick metal layer (36), and the second thin metal layer (10) is located between the second insulating layer 132b/the second thick metal layer. In the present embodiment, the first insulating layer 132a and the second insulating thin metal can be provided because the first four-layer structure 13Aa has the first thick metal layer and the third metal layer 13Gb respectively. The layer (10) and the second thin metal layer (10) have sufficient supporting force. % exhibition H please participate in the phase 2E, the way of the Wei face combination, respectively press the first layer 4 coffee and the second layer structure (10) on the first conductive layer ^ - the conductive layer UGb, wherein the first layer structure 13 For example, the conductive pillar is applied to a portion of the first conductive layer u〇a, and the second laminate is covered with a second conductive pillar 12% and a portion of the second conductive layer u〇b. The body 3 says that the first insulating layer 132a covers the first conductive layer and the portion of the first conductive layer l1Ga, and the second insulating layer 21 applies a portion of the second conductive layer (10). The first thin metal layer ^ thick metal layer 136a is conformally disposed on the first insulating layer, and the second 12 201228509 JJ I /^iwi.doc / l thin metal layer 134b is conformally formed with the second thick metal layer 136b It is disposed on the second insulating layer 132b.

It should be noted that the present invention does not limit the configuration of the first laminate structure 130a and the second laminate structure 130b. In other embodiments not shown, the first laminate structure 13A and The second stacked structure 130b may also not have the first thick metal layer i36a and the second thick metal layer 136b. That is, the first stacked structure 13A may also include only the first insulating layer 132a and the first thin metal layer 134a, wherein the first thin metal layer 134a is located on the first insulating layer 132a, and the first insulating layer 132a The first conductive pillar 120a and a portion of the first conductive layer 11〇a are covered. The second laminated structure 13b may also include only the second insulating layer 132b and the second thin metal layer 13, wherein the second thin metal layer 134b is located on the second insulating layer 1321), and the second insulating layer 132b covers the second The two conductive pillar legs are partially hidden from the second conductive layer. The structure of the first laminated structure (10) and the one-two laminated structure 13Gb shown in FIG. 2D and FIG. 2E is only a scale, and is not referred to as 'Please refer to FIG. 2E and FIG. 2F at the same time. Remove part of the first and layer, respectively,. The structure 130a and a part of the second laminated structure 13%::electric f12〇a and the second conductive column-..., the step of the flute, firstly, by, for example, lift-off, the first thick metal The layer 136a and the second thick metal layer 136b expose the first thin metal layer 134a and the second thin metal layer mb. Then, a part of the first thin metal layer 134b is removed to expose the first conductive pillar 120a and the second conductive pillar by a grinding method (for example, a brushing method) to remove a portion of the thin metal 134a and the portion 13 201228509 120b, to respectively form a first annular conductive layer 15Aa and a second annular conductive layer 150b surrounding the first conductive pillars u〇a and the second conductive pillars 120b. Next, referring to FIG. 20, a third conductive layer 140a is formed by electroplating on the remaining first stacked structures 13A (that is, the first insulating layer 132a and the first-shaped conductive layer 15A). a first conductive pillar 12 〇 & and a fourth conductive layer 14 〇 b formed on the second stacked structure 13 〇 b (that is, the first insulating layer 132 b and the second annular conductive layer 15 〇 b) Two conductive columns 12〇b. In particular, in the present embodiment, the third conductive layer 140a and the first conductive pillar 120a have a third interface S3, and the fourth conductive layer 140b and the second conductive pillar 12% have a fourth interface. 4. Next, referring to FIG. 2H, a peeling force is used to separate the interface between the first conductive layer 11Ga and the first-away layer 12 and the interface between the second conductive layer 1) 〇b and the first-to-four (four) 14. Removing the carrier board ^ to form mutually separated ones - the first circuit board unit 10a and the second circuit board unit secrets - wherein the first circuit board formed after removing the carrier board is π 100a and the second line The board unit is a symmetrical structure. More specifically, the first circuit board unit 10a sequentially includes a first conductive layer 110a, a first conductive pillar 120a, and a ^32 surrounding the side of the first conductive pillar 12A. It is located on the first insulating layer (10) and surrounds the first conductive pillar; the applied conductive layer 15Ga and the first annular conductive layer 15〇a = the second conductive layer 140a. The second circuit board unit 1_ sequentially includes a second conductive layer 11Gb, a second conductive pillar, and a second conductive pillar hidden side 201228509

a second insulating layer 132b on the IIP iwx.doc/I surface, a first annular conductive layer 15〇b on the second insulating layer 132b and surrounding the first conductive surface 120b, and a second on the second annular conductive layer 150b Four conductive layers 140b. Next, referring to FIG. 21, the first conductive layer 丨1〇a, the second conductive layer 110b, the second conductive layer 14A, the fourth conductive layer i4〇b, the first annular conductive layer 150a, and the second are patterned. The annular conductive layer is 15% to form a first patterned conductive layer 110a, a second patterned conductive layer u〇b, a third patterned conductive layer 140a', and a fourth patterned conductive layer yob. The first patterned annular conductive layer 15A, and the second patterned annular conductive layer 50b are hereby formed into a circuit board 10a', i〇〇b.

It is worth mentioning that the present invention does not limit the step of patterning the conductive layer after the carrier board 10 is removed. In other embodiments not shown, before the carrier board 1G is removed, the third is The conductive layer 14Qa and the fourth conductive layer 140b are patterned to form a third patterned conductive layer 140a' and a fourth patterned conductive layer 14%. Of course, before the carrier board 1 is removed, the fabrication of the build-up wiring layer is further performed on the third conductive layer 140a and the fourth conductive layer 14B. That is to say, the above-mentioned embodiments are merely illustrative and are not limited thereto. Of course, in other embodiments not shown, the user may also choose to increase the number of conductive layers and conductive pillars as mentioned in the above embodiments, and those skilled in the art can refer to the above implementation. For the description of the example, according to the actual S, the component is turned over to make the required technical effect. In summary, the circuit board of the present invention is plated directly on the conductive layer.

201228509 ~i.doc/I Over-current 2:::::Board r method: reduce the column - determine and reduce the cost of production σ. In addition, the present invention utilizes the board to produce two thin-plate lines in a single-process process. The L ΪΙ circuit board causes a yield loss due to the instability of the carrier board when the thin board is fabricated. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. 2A to 21 are cross-sectional views showing a method of fabricating a circuit board according to an embodiment of the present invention. [Description of main component symbols] 10. Carrier plate 12. First release layer 14: Second release layer 201228509

Jj i /^iwi.doc/I 16 : core layer 100, 100a', 100b': circuit board 100a · circuit board unit 100b: circuit board unit 110: first patterned conductive layer 110a: first conductive layer 110a' The first patterned conductive layer 110b: the second conductive layer - 110b': the second patterned conductive layer 120: the conductive pillar 120a: the first conductive pillar 120b: the second conductive pillar 130: the insulating layer 130a: the first laminated structure 130b: second stacked structure 132a: first insulating layer • 132b: second insulating layer 134a • first thin metal layer 134b: second thin metal layer 136a: first thick metal layer 136b: second thick metal layer 140 : second patterned conductive layer 140a : third conductive layer 140 a ′ : third patterned conductive layer 17 201228509

/ / yiwi.doc / I 140b: fourth conductive layer 140b': fourth patterned conductive layer 150: annular conductive layer 150a: first annular conductive layer 150b: second annular conductive layer 150a': first pattern The annular conductive layer 150b': the second patterned annular conductive layer 51, S1': the first interface 52, S2': the second interface 53: the third interface 54: the fourth interface

18

Claims (1)

.oc/1 201228509 VII. Scope of application for patents: 1. A method for fabricating a circuit board, comprising: a fresh f-bearing board' the money board includes - a "transfer layer", a - a - slave - configuration in the correction - off-shape The layer and the second release layer respectively form a first conductive; the first-de-shaped layer of the potential-channel plate and the second layer of the electrical layer respectively form at least a first-conductive pillar and At least—the first conductive layer and the second conductive layer have a 1-interface between the “:=first conductive layer, and a second interface between the second conductive layer and the second conductive layer; a pillar, a first-two-layer-stacked structure, and a second stacked structure on the top and the far second conductive layer, wherein the first stacking cost = two points =: the first a conductive layer, and the "3~jna-〇A^-a conductive pillar and a portion of the second conductive layer; respectively removing a portion of the first-stacked structure and a portion of the second ', 'construction' to the exposed (four)- And a second conductive layer and a fourth conductive layer respectively formed on the remaining side-layer structure and the first conductive pillar And a structure of the second conductive pillar, wherein the third conductive layer has a third interface between the fourth conductive layer and the fourth conductive layer and the fourth conductive layer; and a peeling force is used Separating the interface between the first conductive layer and the first conductive layer and the surface of the second conductive layer and the second conductive layer between the second conductive layer and the second conductive layer The method of manufacturing the circuit board according to the first aspect of the invention, wherein the first laminated structure comprises a first insulating layer, a first thin metal layer and a first thick metal layer, a first thin metal layer is disposed between the first insulating layer and the first thick metal, and the first insulating layer covers the first conductive pillar and a portion of the first conductive layer, and the second stacked structure includes a second An insulating layer, a second thin metal layer, and a second thick metal layer, the second thin metal layer is between the second insulating layer and the second thick metal, and the second insulating layer covers the second conductive pillar And a portion of the second conductive layer. 3. The circuit board according to claim 2 The manufacturing method, wherein the step of removing a portion of the first laminate structure and a portion of the second laminate structure comprises: 10 the first thick metal layer and the second thick metal layer to expose the first germanium metal layer And the second thin metal layer; and the first conductive pillar of the first conductive pillar, and the second annular conductive layer of the second annular conductive layer, and the fourth method, wherein Removing the first thick metal layer includes a lift-off method. 5. The method according to claim 3, wherein the portion of the first-thin metal layer method comprises a grinding method, the maker of the circuit board described in the item, and the second thick metal The manufacturer of the circuit board described in the method of the layer and the side of the second thin metal layer 201228509 / / ^iwi.d〇c / I port of the patent application described in the first paragraph of the patent range = The method of forming the first-conductor and the second conductive pillar includes: a method 7 of applying a circuit as described in the patent application, and the first laminated structure includes a first An insulating layer and a first thin metal layer, the first thin metal layer is located A first insulating layer, and a second insulating layer covering the first - and the portion of the first conductive pillar The second insulating layer and the second thin metal layer are disposed on the second insulating layer, and the second insulating layer covers the second conductive pillar and a portion of the second conductive layer. 8. The method of fabricating a circuit board according to claim 7, wherein the step of removing a portion of the first laminate structure and a portion of the second laminate structure comprises: Forming a thin metal layer and a portion of the second thin metal layer to detect the second conductive pillar to form a first annular conductive layer surrounding the V-electrode and the second conductive pillar, and a A second annular conductive layer. 9. The method of fabricating a circuit board as described in claim 8 of the invention or the method of removing a portion of the first thin metal layer and a portion of the second thin metal layer comprises a grinding method. 10. The manufacturer of the circuit board according to item 1 of the patent application scope is characterized in that the first release layer and the second release layer are made of a conductive paste containing bismuth or a non-conductive paste containing bismuth. . The method for manufacturing a circuit board according to claim 1, wherein the first release layer and the second release layer are made of nickel, and the core layer is made of nickel. Copper or not steel. 12. The method of fabricating the circuit board of claim 1, further comprising: forming a build-up wiring layer on the first laminate structure and the second laminate before removing the carrier plate Structurally. 13. The method of fabricating a circuit board according to claim 1, wherein the first conductive layer and the second conductive layer formed on the first release layer and the second release layer of the carrier plate The layers are respectively a patterned conductive layer, and the separation between the first conductive layer and the first release layer and the second conductive layer and the second release layer are separated by the stripping force The third conductive layer and the fourth conductive layer are patterned to form a third patterned conductive layer and a fourth patterned conductive layer before the carrier is removed. 14. The method of fabricating a circuit board according to claim 1, further comprising: separating the interface between the first conductive layer and the first release layer and the second conductive layer by the peeling force After the interface between the second release layer and the second release layer is removed, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are patterned to form a first a patterned conductive layer, a second patterned conductive layer, a third patterned conductive layer and a fourth patterned conductive layer. 15. A circuit board comprising: a first patterned conductive layer; 22 201228509 " w * I / such as t.doc/I a conductive pillar disposed on the first patterned conductive layer, wherein the conductive pillar Between the first patterned conductive layer and a first interface; an insulating layer disposed on the first patterned conductive layer and surrounding the side of the conductive pillar; and a second patterned conductive layer disposed on The conductive pillar and the insulating layer, wherein the second patterned conductive layer and the conductive pillar have a second interface, and the second patterned conductive layer is electrically transmitted through the conductive pillar and the first patterned conductive layer The circuit board of claim 15, further comprising an annular conductive layer disposed around the conductive pillar and located between the insulating layer and the first patterned conductive layer.