TWI532164B - 整流器 - Google Patents

整流器 Download PDF

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TWI532164B
TWI532164B TW103102972A TW103102972A TWI532164B TW I532164 B TWI532164 B TW I532164B TW 103102972 A TW103102972 A TW 103102972A TW 103102972 A TW103102972 A TW 103102972A TW I532164 B TWI532164 B TW I532164B
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rectifier
diffusion region
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epitaxial layer
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陳偉梵
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南亞科技股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

整流器
本發明是有關於一種整流器,且特別是有關於一種用於縮短反向恢復時間(reverse recovery time,TRR)的整流器。
在習知的技術領域中,至少部分包含例如快速恢復二極體(Fast Recovery Diode,FRD)、金屬氧化物半導體場效應電晶體(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)和絕緣閘極雙極性電晶體(Insulated Gate Bipolar Transistor,IGBT)等二極體結構的電力半導體裝置在電力供應電路中用作開關。為了實現快速開關且減小開關損耗,需要電力半導體裝置具有較短反向恢復時間(TRR)的開關。在現有技術中,可通過使用低摻雜的N型或P型雜質半導體裝置以在電力半導體裝置處於順向偏壓時減少電子和電洞的供應和聚集來縮短TRR。另一方面,N型和P型雜質的減少導致接觸電阻顯著提高,且接觸電阻的提高影響電力半導體裝置的開關性能。此外,高濃度的N型或P型雜質則導致開關的TRR會被延長的問題。
特別是,當施加在整流器上的操作電壓的電壓電位相對較高時,TRR嚴重延長,且整流器的性能隨之降低。
本發明提供一種用於縮短反向恢復時間的整流器。
本發明的整流器包含N型磊晶層、多個P型擴散區域和多個N型擴散區域。所述P型擴散區域設置在所述N型磊晶層中,且所述N型擴散區域分別設置在所述P型擴散區域中。其中,所述P型擴散區域電耦接到所述N型擴散區域。
在本發明的一實施例中,所述整流器更包含覆蓋層。所述覆蓋層覆蓋所述N型磊晶層、所述P型擴散區域和所述N型擴散區域,且所述N型磊晶層、所述P型擴散區域和所述N型擴散區域通過所述覆蓋層而電耦接以成為所述整流器的陽極。
在本發明的一實施例中,所述N型磊晶層形成所述整流器的陰極。
在本發明的一實施例中,所述覆蓋層為金屬層或金屬矽化物層。
在本發明的一實施例中,所述相鄰P型擴散區域中的兩者之間的距離介於預定範圍之間。
在本發明的一實施例中,所述整流器更包含至少一個P型保護擴散區域。所述第一P型保護擴散區域設置在所述N型磊晶層中且圍繞所述P型擴散區域,其中所述第一P型保護擴散區域為浮動的。
在本發明的一實施例中,所述整流器更包含至少一個第二P型保護擴散區域。所述第二P型保護擴散區域設置在所述N型磊晶層中且 圍繞所述第一P型保護擴散區域,其中所述第二P型保護擴散區域電耦接到所述N型擴散區域。
在本發明的一實施例中,所述整流器更包含氧化矽層。所述氧化矽層設置在所述第一P型保護擴散區域和所述第二P型保護擴散區域上且覆蓋所述第一P型保護擴散區域和所述第二P型保護擴散區域。
在本發明的一實施例中,所述整流器更包含N型基底層。所述N型磊晶層設置在所述N型基底層上,且所述N型磊晶層覆蓋所述N型基底層。
在本發明的一實施例中,所述N型磊晶層、所述P型擴散區域中的每一者和所述對應N型擴散區域形成雙極性電晶體。
基於上述,本本發明提供多個N型擴散區域,所述多個N型擴散區域分別設置在所述P型擴散區域中以在所述整流器中形成多個雙極性電晶體。因此,當整流器處於反向偏壓時,整流器的矽中不存在殘餘電洞電荷。即使整流器正在高操作電壓下工作,也可縮短反向恢復時間。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
100‧‧‧整流器
110‧‧‧N型基底層
120‧‧‧N型磊晶層
130‧‧‧覆蓋層
141~143‧‧‧P型擴散區域
151~153‧‧‧N型擴散區域
400‧‧‧整流器
410‧‧‧N型基底層
420‧‧‧N型磊晶層
430‧‧‧覆蓋層
441~44N‧‧‧P型擴散區域
461‧‧‧氧化矽層
4511~45NM‧‧‧N型擴散區域
D1~D2‧‧‧肖特基二極體
IF‧‧‧電流
R1~R3‧‧‧保護環/P型保護擴散區域
T1~T3‧‧‧雙極性電晶體
圖1為根據本發明的實施例的整流器的結構圖。
圖2為根據本發明的實施例的整流器100的等效電路圖。
圖3A為整流器100處於正向偏壓時的框圖。
圖3B為整流器100處於反向偏壓時的框圖。
圖4為根據本發明的實施例的整流器的俯視圖。
圖5為沿著圖4中的截面線A到A'截取的整流器400的橫截面圖。
請參照圖1,圖1為根據本發明的實施例的整流器的結構圖。整流器100包含N型基底層110、N型磊晶層120、多個P型擴散區域141到143、多個N型擴散區域151到153和覆蓋層130。N型磊晶層120設置在N型基底層110上,且N型磊晶層120覆蓋N型基底層110。P型擴散區域141到143設置在N型磊晶層120中,且N型擴散區域151到153分別設置在P型擴散區域141到143中。
覆蓋層130設置在N型磊晶層120上,且覆蓋層130覆蓋N型磊晶層120、P型擴散區域141到143和N型擴散區域151到153。在此實施例中,P型擴散區域141到143可通過覆蓋層130而分別耦接到N型擴散區域151到153,且P型擴散區域141到143可通過覆蓋層130而耦接到一起以形成整流器100的陽極。
覆蓋層130可為金屬層或金屬矽化物層,且覆蓋層130可為由金(Au)、鉑(Pt)、鎢(W)、鉬(Mo)、鉻(Cr)、鎳(Ni)、錫(Ti)或其他金屬形成的金屬層。此外,覆蓋層130可用於形成矽化物,且接著在沉積接觸層之前繼之以擴散阻障,例如,TiW、TiN或其他層。針對導線結合的實施方式,接觸層可由Al形成,或針對焊接的實施方式,則可由銀(Ag) 或Au來形成。
另一方面,N型磊晶層120可用於形成整流器100的陰極。也就是說,導線可通過與N型磊晶層120或N型基底層110接觸而連接到整流器100的陰極。
整流器100的陰極的電極可設置在N型基底層110上,且整流器100的陰極的電極接觸N型基底層110。整流器100的陽極的電極可設置在覆蓋層130上,且整流器100的陽極的電極接觸覆蓋層130以電性耦接到P型擴散區域141到143和N型擴散區域151到153。
此外,P型擴散區域141到143中的每一者不相互接觸。此外,相鄰P型擴散區域141到143中的兩者之間的距離介於預定範圍之間。所述預定範圍可由整流器100的設計者設置,且所述預定範圍可根據整流器100的操作電壓和整流器100的製程參數來設置。此外,P型擴散區域的數目不受限制,圖1中設置在整流器100中的三個P型擴散區域141到143僅為實例。
請參照圖2,圖2為根據本發明的實施例的整流器100的等效電路圖。此處請注意,N型磊晶層120、P型擴散區域141到143中的每一者和分別對應的N型擴散區域151到153形成雙極性電晶體T1到T3。N型擴散區域151到153分別形成雙極性電晶體T1到T3的發射極,P型擴散區域141到143分別形成雙極性電晶體T1到T3的基極,且N型磊晶層120形成雙極性電晶體T1到T3的集電極。雙極性電晶體T1到T3為NPN型雙極性電晶體,且雙極性電晶體T1到T3的發射極為多晶矽發射極(poly emitter)。另一方面,肖特基二極體D1和D2可由覆蓋層130和N型磊晶 層120形成。肖特基二極體D1和D2的陽極可耦接到雙極性電晶體T1到T3的發射極和基極,且肖特基二極體D1和D2的陰極耦接到雙極性電晶體T1到T3的集電極。
此外,關於雙極性電晶體T1到T3的發射極,通過從多晶矽擴散來形成淺接面(shallow junction)。多晶矽可通過原位多晶摻雜(in-situ doping poly)來製成。原位多晶摻雜的載子濃度可為N型摻雜劑的1E18到1E21。
在整流器的操作中,請參照圖3A和圖3B,圖3A為整流器100處於正向偏壓時的框圖,且圖3B為整流器100處於反向偏壓時的框圖。在圖3A中,當整流器100處於正向偏壓(也就是說,第一電壓施加到整流器100的陽極,且第二電壓施加到整流器100的陰極,且第一電壓的電壓電位大於第二電壓的電壓電位)時,電流IF通過由雙極性電晶體T1到T3形成的電流通道而從整流器100的陽極流動到N型磊晶層120和N型基底層110。因為由N型磊晶層120和P型擴散區域141到143形成的P-N結的深度減小,所以其少數載子濃度可在N型磊晶層120和N型基底層110中顯著降低。因此,正向接通電壓減小,且因此整流器100的開關速度可提高。
在圖3B中,當整流器100處於反向偏壓(也就是說,第一電壓施加到整流器100的陽極,且第二電壓施加到整流器100的陰極,且第一電壓的電壓電位小於第二電壓的電壓電位)時,耗盡層形成而延伸到P型擴散區域141到143,且電流通道關閉,以使得整流器100切斷。由於雙極性電晶體T1到T3,N型磊晶層120中不存在殘餘空穴電荷,且反向恢復時間(TRR)可得到改進。
整體來說,請參照圖3A和圖3B,整流器100在P型擴散區域 141到143與N型磊晶層120之間提供淺接面結構,以在接面結構用於改進反向崩潰電壓且降低漏電流時降低內建電位。此外,雙極性電晶體T1到T3的發射極在整流器100的陽極與整流器100的半導體結構之間建立歐姆接觸。因此,大部分電流流經整流器100的接面結構,且瞬時速度和反向恢復電荷(reverse recovery charge,QRR)可進一步減小。
請參照圖4,圖4為根據本發明的實施例的整流器的俯視圖。在圖4中,整流器400包含保護環R1到R3、P型擴散區域441到44N和N型擴散區域4511到45NM。N型擴散區域4511到45NM佈置成陣列,且P型擴散區域中的每一者(例如,P型擴散區域411)具有多個N型擴散區域(例如,N型擴散區域4511到451M)。保護環R1到R3圍繞P型擴散區域441到44N,且與保護環R1相鄰的P型擴散區域441和44N的面積大於其他P型擴散區域。設置在P型擴散區域441和44N中的N型擴散區域的面積也可大於設置在P型擴散區域441和44N外的N型擴散區域的面積。
請參照圖5,圖5為沿著圖4中的截面線A到A'截取的整流器400的橫截面圖。在圖5中,整流器400包含N型基底層410、N型磊晶層420、覆蓋層430、P型擴散區域441到44N、N型擴散區域4511到45N1、氧化矽層461和P型保護擴散區域R1到R3。P型保護擴散區域R1到R3設置在整流器400的邊緣中,且P型擴散區域441到44N由P型保護擴散區域R1到R3圍繞。更具體地說,P型保護擴散區域R1和R2為電性浮接的。P型保護擴散區域R3則可耦接到P型擴散區域441到44N。
氧化矽層461設置在N型磊晶層420中,且氧化矽層461覆蓋N型磊晶層420的一部分、P型保護擴散區域R1到R3的全部、P型擴散區 域441到44N的一部分和N型擴散區域4511到45N1的一部分。P型保護擴散區域R1到R3可用以作為整流器400的終端結構,以改進反向崩潰電壓且減小漏電流。
綜上所述,本發明提供設置在N型磊晶層中以形成淺P-N接面結構的多個P型擴散區域。整流器的內建電位可降低。此外,本揭露通過在P型擴散區域中的每一者中設置多個N型擴散區域而提供多個雙極性電晶體。當整流器被反向偏壓時,N型磊晶層中的電洞電荷可得以消除,且反向恢復時間(TRR)可縮短。也就是說,根據本發明時施例,整流器的性能可被改進。
100‧‧‧整流器
110‧‧‧N型基底層
120‧‧‧N型磊晶層
130‧‧‧覆蓋層
141~143‧‧‧P型擴散區域
151~153‧‧‧N型擴散區域

Claims (10)

  1. 一種整流器,包括:一N型磊晶層;多個P型擴散區域,設置在所述N型磊晶層中;多個N型擴散區域,分別設置在所述P型擴散區域中;以及一覆蓋層,直接覆蓋所述P型擴散區域和所述N型擴散區域,其中,所述P型擴散區域透過所述覆蓋層而電耦接到所述N型擴散區域。
  2. 如申請專利範圍第1項所述的整流器,其中所述覆蓋層更直接覆蓋所述N型磊晶層,且所述N型磊晶層、所述P型擴散區域和所述N型擴散區域通過所述覆蓋層而電耦接以成為所述整流器的陽極。
  3. 如申請專利範圍第2項所述的整流器,其中所述N型磊晶層形成所述整流器的陰極。
  4. 如申請專利範圍第2項所述的整流器,其中所述覆蓋層為金屬層或金屬矽化物層。
  5. 如申請專利範圍第1項所述的整流器,其中所述相鄰P型擴散區域中的兩者之間的距離介於預定範圍之間。
  6. 如申請專利範圍第1項所述的整流器,更包括:至少一個第一P型保護擴散區域,設置在所述N型磊晶層中且圍繞所述P型擴散區域,其中所述第一P型保護擴散區域為浮動的。
  7. 如申請專利範圍第6項所述的整流器,更包括:至少一第二P型保護擴散區域,設置在所述N型磊晶層中且圍繞所述第一P型保護擴散區域,其中所述第二P型保護擴散區域電耦接到所述N型擴散區域。
  8. 如申請專利範圍第7項所述的整流器,更包括:一氧化矽層,設置在所述第一P型保護擴散區域和所述第二P型保護擴散區域上且覆蓋所述第一P型保護擴散區域和所述第二P型保護擴散區域。
  9. 如申請專利範圍第1項所述的整流器,更包括:一N型基底層,其中所述N型磊晶層設置在所述N型基底層上,且所述N型磊晶層覆蓋所述N型基底層。
  10. 如申請專利範圍第1項所述的整流器,其中所述N型磊晶層、所述P型擴散區域中的每一者和所述對應N型擴散區域形成雙極性電晶體。
TW103102972A 2013-11-08 2014-01-27 整流器 TWI532164B (zh)

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Publication number Priority date Publication date Assignee Title
US3725683A (en) * 1971-02-03 1973-04-03 Wescom Discrete and integrated-type circuit
US4412376A (en) * 1979-03-30 1983-11-01 Ibm Corporation Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation
US4300152A (en) * 1980-04-07 1981-11-10 Bell Telephone Laboratories, Incorporated Complementary field-effect transistor integrated circuit device
JP3637069B2 (ja) 1993-03-12 2005-04-06 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5557127A (en) * 1995-03-23 1996-09-17 International Rectifier Corporation Termination structure for mosgated device with reduced mask count and process for its manufacture
US6448160B1 (en) * 1999-04-01 2002-09-10 Apd Semiconductor, Inc. Method of fabricating power rectifier device to vary operating parameters and resulting device
US6486524B1 (en) 2000-02-22 2002-11-26 International Rectifier Corporation Ultra low Irr fast recovery diode
US6261874B1 (en) 2000-06-14 2001-07-17 International Rectifier Corp. Fast recovery diode and method for its manufacture
US8901699B2 (en) * 2005-05-11 2014-12-02 Cree, Inc. Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection
US7880166B2 (en) 2006-05-10 2011-02-01 Ho-Yuan Yu Fast recovery reduced p-n junction rectifier
US8669554B2 (en) * 2006-05-10 2014-03-11 Ho-Yuan Yu Fast recovery reduced p-n junction rectifier
US8193559B2 (en) * 2009-01-27 2012-06-05 Infineon Technologies Austria Ag Monolithic semiconductor switches and method for manufacturing

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