TWI532137B - 半導體裝置封裝體及其形成方法 - Google Patents
半導體裝置封裝體及其形成方法 Download PDFInfo
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- TWI532137B TWI532137B TW102143707A TW102143707A TWI532137B TW I532137 B TWI532137 B TW I532137B TW 102143707 A TW102143707 A TW 102143707A TW 102143707 A TW102143707 A TW 102143707A TW I532137 B TWI532137 B TW I532137B
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- Prior art keywords
- microbump
- layer
- interposer
- wafer
- line
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- 238000000034 method Methods 0.000 title claims description 55
- 239000004065 semiconductor Substances 0.000 title claims description 50
- 235000012431 wafers Nutrition 0.000 claims description 133
- 239000012212 insulator Substances 0.000 claims description 88
- 229910052751 metal Inorganic materials 0.000 claims description 73
- 239000002184 metal Substances 0.000 claims description 73
- 229910000679 solder Inorganic materials 0.000 claims description 39
- 239000010949 copper Substances 0.000 claims description 38
- 229910052802 copper Inorganic materials 0.000 claims description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 263
- 239000000758 substrate Substances 0.000 description 38
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 36
- 230000008569 process Effects 0.000 description 29
- 229910052759 nickel Inorganic materials 0.000 description 18
- 239000011135 tin Substances 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 8
- 229920002577 polybenzoxazole Polymers 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 229910052718 tin Inorganic materials 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 230000008054 signal transmission Effects 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 229910007637 SnAg Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229920000265 Polyparaphenylene Polymers 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- -1 polyphenylene Polymers 0.000 description 2
- 230000005070 ripening Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2224/1308—Plural core members being stacked
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Description
本發明主要是關於一種半導體封裝裝置及其形成方法,特別是關於一種方法與裝置,其適用於使用一微凸塊層在一中介層上形成一半導體裝置封裝體。
自發明了積體電路(integrated circuit;IC)以來,由於在各種電子構件(例如電晶體、二極體、電阻器、電容器等)的積集密度(integration density)的方面的持續改善,半導體工業歷經了快速的成長。在大多數情況下,此一在積集密度的方面的改善是來自在最小特徵尺寸方面的不斷的縮減,而允許將更多的構件整合在一既定面積內。這些較小的電子構件亦需要使用較小的封裝體,此較小的封裝體的面積比以往的封裝體的面積還小。用於半導體裝置的某些較小型的封裝體包含四面扁平封裝(quad flat pack;QFP)裝置、針柵陣列(pin grid array;PGA)裝置、球柵陣列(ball grid array;BGA)裝置、覆晶(flip chips;FC)裝置、三維積體電路(three dimensional integrated circuits;3DICs)裝置、晶圓級封裝(wafer level package;WLP)裝置以及封裝體立體堆疊(package on package;PoP)裝置。
三維積體電路技術亦被稱作是垂直互聯封裝技術(vertical interconnect packaging technology),因為此技術利用
晶片的垂直的維度來減少互聯長度,而達成較大的積集效率。用於三維積體電路封裝體的互連的技術包含銲線接合(wire-bonding)、微凸塊(micro-bumps)、貫穿孔(through-vias)等等。可使用矽的中介層來形成三維積體電路封裝體,其中上述中介層是對安裝於此中介層上的晶片提供晶片對晶片的互連。例如,二個晶片可彼此上下相接,其中下方的晶片是藉由微凸塊等的連接物與上述中介層耦合。另一種情況,亦可將多個晶片並列而安裝於一中介層的上方,並藉由微凸塊等的連接物使這些晶片耦合於上述中介層。
訊號積集度對封裝技術而言,是一項重要的議題。關於形成於一中介層上的三維積體電路封裝體,其是使用此中介層內部的金屬層而在三維積體電路封裝體中的晶片之間傳輸訊號,此類的三維積體電路封裝體面臨相當的挑戰。
有鑑於此,本發明的一實施例是提供一種半導體裝置封裝體,包含一中介層(interposer)、一第一晶片與一第二晶片以及一微凸塊層。上述中介層具有一表面與一第一接觸墊,上述表面是由一絕緣體層形成,上述第一接觸墊覆蓋上述絕緣體層的一第一開口並與上述中介層中的一金屬層接觸。上述第一晶片與上述第二晶片是在上述中介層的上方。上述微凸塊層具有一第一微凸塊線與一微凸塊,上述第一微凸塊線是在上述中介層的上述絕緣體層的上方,上述微凸塊是在上述中介層的上述第一接觸墊的上方,其中上述第一微凸塊線是電性連接上述第一晶片與上述第二晶片,上述微凸塊是將上述第一晶
片電性連接於上述中介層中的上述金屬層。
在上述之半導體裝置封裝體中,上述絕緣體層包含一材料,上述材料較好是選自下列物質組成之族群:氮化矽(SiN)、二氧化矽(SiO2)、氧氮化矽(SiON)、聚醯亞胺(polyimide;PI)、苯並環丁烯(benzocyclobutene;BCB)、聚苯噁唑(polybenzoxazole;PBO)或上述之組合。
在上述之半導體裝置封裝體中,上述微凸塊與上述第一微凸塊線較好是由相同材料形成。
在上述之半導體裝置封裝體中,上述微凸塊與上述第一微凸塊線較好是具有實質上相同的高度。
在上述之半導體裝置封裝體中,較好為:上述第一微凸塊線包含一銅層與一軟銲材料層。
在上述之半導體裝置封裝體中,較好為:上述第一微凸塊線更包含一鎳層,上述鎳層位於上述銅層與上述軟銲材料層之間。
在上述之半導體裝置封裝體中,上述微凸塊層的高度較好為5μm-50μm。
在上述之半導體裝置封裝體中,較好為:上述微凸塊層更包含一第二微凸塊線,上述第二微凸塊線是在上述絕緣體層的上方,並電性連接在上述中介層上方的複數個晶片。
在上述之半導體裝置中封裝體,較好為:更包含一凸塊下金屬(under bump metal;UBM)層,上述凸塊下金屬層是在上述絕緣體層與上述第一微凸塊線之間。
在上述之半導體裝置封裝體中,較好為:上述微
凸塊層更包含一第三微凸塊線,上述第三微凸塊線是在上述絕緣體層的上方並連接於一第二接觸墊與一第三接觸墊,其中上述第二接觸墊覆蓋上述絕緣體層的一第二開口並與上述中介層中的上述金屬層接觸,上述第三接觸墊覆蓋上述絕緣體層的一第三開口並與上述中介層中的上述金屬層接觸。
在上述之半導體裝置封裝體中,較好為:中介層更包含一鈍化層與一重分佈層(redistribution layer)。
在上述之半導體裝置封裝體中,較好為:藉由一連接物而使上述第一微凸塊線連接於上述第一晶片,且一底填充物(underfill)是填充上述第一微凸塊線與上述第一晶片之間的間隙。
本發明的又一實施例是提供一種半導體裝置封裝體的形成方法,包含下列步驟:提供一中介層(interposer),上述中介層具有一表面與一接觸墊,上述表面是由一絕緣體層形成,上述接觸墊覆蓋上述絕緣體層的一開口並與上述中介層中的一金屬層接觸;在上述中介層的上方形成一微凸塊層,其中上述微凸塊層具有一第一微凸塊線與一微凸塊,上述第一微凸塊線是在上述中介層的上述絕緣體層的上方,上述微凸塊是電性連接於上述中介層的上述接觸墊;將一第一晶片置於上述第一微凸塊線的上方,在上述第一晶片的一第一位置將上述第一晶片電性連接電性連接於上述第一微凸塊線,並在上述第一晶片之不同於上述第一位置的一第二位置將上述第一晶片電性連接電性連接於上述微凸塊;以及將一第二晶片置於上述第一微凸塊線的上方,並將上述第二晶片電性連接於上述第一微凸
塊線。
在上述之半導體裝置封裝體的形成方法中,上述第一微凸塊線與上述微凸塊較好是同時形成。
在上述之半導體裝置封裝體的形成方法中,上述微凸塊與上述第一微凸塊線較好是具有實質上相同的高度。
在上述之半導體裝置封裝體的形成方法中,形成上述微凸塊層的步驟較好為包含:形成一銅層;然後在上述銅層的上方形成一軟銲材料層。
本發明的又另一實施例是提供一種半導體裝置封裝體,其包含一中介層(interposer)、一晶片以及一微凸塊層。上述中介層的一表面是由一絕緣體層形成,上述中介層具有一第一接觸墊、一第二接觸墊與一第三接觸墊,上述第一接觸墊覆蓋上述絕緣體層的一第一開口,上述第二接觸墊覆蓋上述絕緣體層的一第二開口,上述第三接觸墊覆蓋上述絕緣體層的一第三開口。上述晶片是在上述中介層的上方。上述微凸塊層具有一第一微凸塊線與一微凸塊,上述第一微凸塊線是在上述中介層的上述絕緣體層的上方,上述微凸塊是在上述中介層的上述第一接觸墊的上方,其中上述第一微凸塊線是電性連接上述第二接觸墊與上述第三接觸墊,上述微凸塊是將上述晶片電性連接於上述中介層中的上述第一接觸墊。
在上述之半導體裝置封裝體中,上述絕緣體層包含一材料,上述材料較好是選自下列物質組成之族群:氮化矽(SiN)、二氧化矽(SiO2)、氧氮化矽(SiON)、聚醯亞胺(polyimide;PI)、苯並環丁烯(benzocyclobutene;BCB)、聚苯
噁唑(polybenzoxazole;PBO)或上述之組合。
在上述之半導體裝置封裝體中,上述微凸塊與上述第一微凸塊線較好是由相同材料形成。
在上述之半導體裝置封裝體中,上述微凸塊與上述第一微凸塊線較好是具有實質上相同的高度。
10‧‧‧中介層
30‧‧‧基板
32‧‧‧接觸墊
34‧‧‧鈍化層
36‧‧‧絕緣體層
37‧‧‧絕緣體層
38‧‧‧重分佈層
40‧‧‧微凸塊層
42‧‧‧微凸塊線
46‧‧‧微凸塊線
48‧‧‧微凸塊
54‧‧‧連接物
56‧‧‧第一晶片
57‧‧‧底填充物
58‧‧‧第二晶片
100‧‧‧半導體裝置封裝體
303‧‧‧貫穿孔
305‧‧‧裝置
390‧‧‧凸塊下金屬層
391‧‧‧凸塊下金屬墊
421‧‧‧銅層
423‧‧‧軟銲凸塊
425‧‧‧鎳層
第1(a)-1(d)圖是一系列的剖面圖與俯視圖,顯示本發明某些實施例之具有使用一微凸塊層的中介層之封裝體、以及上述微凸塊層的細節。
第2(a)-2(b)圖是一系列的剖面圖,顯示本發明某些實施例之具有使用一微凸塊層的中介層之封裝體。
第3(a)~3(d)圖是一系列之剖面圖,顯示本發明某些額外的實施例之具有使用一微凸塊層的中介層之封裝體的形成方法。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例,以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例,以求簡化發明的說明。當然,這些特定的範例並非用以限定本發明。例如,若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方,即表示其包含了所形成的上述
第一特徵與上述第二特徵是直接接觸的實施例,亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間,而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外,本說明書以下的揭露內容可能在各個範例中使用重複的元件符號,以使說明內容更加簡化、明確,但是重複的元件符號本身不會使不同的實施例及/或結構之間產生關聯。
如以下所述,本發明揭露一種方法與裝置,適用於使用一微凸塊層在一中介層上形成一半導體裝置封裝體。上述微凸塊層可包含微凸塊與微凸塊線,其中一微凸塊是用於一晶片與上述中介層之間的一垂直連接,而一微凸塊線是用於位在上述中介層的上方的不同晶片之間的信號傳輸所使用的水平連接。此外,形成於上述中介層的上方的上述微凸塊線也同樣地可用來傳遞此中介層中的訊號。與上述中介層內的金屬線相比,上述微凸塊線具有較低的線路密度與更低的電阻,因此可減少線路間的干擾(interference)與串音(crosstalk),而增加訊號強度。上述微凸塊線可以與上述微凸塊同時形成,具有低成本或未增加成本。
如第1(a)圖所示,為一簡化的俯視圖,顯示形成於一中介層10上的一半導體裝置封裝體100。一第一晶片56與一第二晶片58是在中介層10的上方被封裝,並連接於中介層10。一微凸塊層40是提供第一晶片56與第二晶片58之間的水平連接。如第1(a)圖所示,微凸塊層40具有複數個微凸塊線42。雖然第1(a)圖未繪示,微凸塊層40亦可包含複數個微凸塊與複數個微凸塊線,而傳輸中介層10中的訊號。可直接經由微凸塊層
40內的微凸塊線42等的微凸塊線,在第一晶片56與第二晶片58之間傳輸第二晶片58訊號,而不需要通過中介層10。與導電路徑形成於中介層10內的情況相比,微凸塊線42為第一晶片56與第二晶片58之間的訊號傳輸提供較短的路徑,且微凸塊線42具有較低的電阻與較低的線路密度,因此減少線路間的干擾(interference)與串音(crosstalk),而增加、改善晶片間的訊號強度。
中介層10可包含一基板(未繪示),並在上述基底內形成有貫穿孔與裝置。如第1(b)圖所示,微凸塊線42可在上述基板的上方更包含複數個接觸墊、複數個鈍化層、例如聚合物層等的複數個絕緣體層、複數個重分佈層(redistribution layer;RDL)以及一凸塊下金屬層(under bump metal;UBM)。此外,一封裝基板可用來取代前述的中介層10,其中上述封裝基板不具前述貫穿孔或裝置、前述的任何或所有的各層。
第一晶片56與第二晶片58可以是由一半導體晶圓形成的積體電路晶片,第一晶片56與第二晶片58可以是適用於一特定用途的任何適當的積體電路晶片。例如,第一晶片56與第二晶片58分別可以是一記憶體晶片或一邏輯電路晶片,上述記憶體例如為動態隨機存取記憶體(dynamic random access memory;DRAM)、靜態隨機存取記憶體(static random access memory;SRAM)、非揮發性隨機存取記憶體(non-volatile random-access memory;NVRAM)等。
微凸塊層40的更詳細的部分是如剖面圖之第1(b)-1(d)圖所示。微凸塊層40可包含如第1(b)圖所示的一微凸
塊48、如第1(c)圖所示的一微凸塊線42以及如第1(d)圖所示的一微凸塊線46。在更詳細地顯示半導體裝置封裝體100的第2(a)與2(b)圖中,會繪示微凸塊48、微凸塊線42、微凸塊線46的使用情形。微凸塊層40可更包含複數個上述的微凸塊48、微凸塊線42以及微凸塊線46,但第1(b)-1(d)圖僅分別繪示出其中的一個微凸塊48、一個微凸塊線42以及一個微凸塊線46。微凸塊線42、微凸塊線46可以與微凸塊48同時形成,具有低成本或未增加成本,並可具有同樣的高度,且可以由同樣的材料形成。可藉由微凸塊48的高度或微凸塊線42、微凸塊線46的高度來定義微凸塊層40的高度,這些高度可由使用於此封裝體的技術決定。例如在目前的技術,微凸塊層40的高度可在5μm至50μm的範圍內,例如為27μm。
如第1(b)圖所示,微凸塊48可包含形成於一銅層421的上方的一軟銲凸塊423。可視需求選用的一鎳層425可位於軟銲凸塊423與銅層421之間。軟銲凸塊423可包含一具導電性的軟銲材料,例如Sn、Ni、Au、Ag、Cu、Bi、上述之合金或上述成分與其他導電材料的組合。例如,軟銲凸塊423可以是一Cu/SnAg軟銲凸塊。微凸塊48可藉由以下步驟來依序形成,各層之形成使採用相同或類似的方法:(1)先經由例如濺鍍、蒸鍍、電鍍、印刷、軟銲料轉移或植球等方法,將一銅層421形成至例如約15μm的厚度;(2)接下來,形成一鎳層425;(3)接下來最後是形成一軟銲層,例如為無鉛軟銲料SnAg。然後,施行一重流(reflow)步驟,使上述軟銲層的形狀成為如如第1(b)圖所示的軟銲凸塊423的凸塊形狀。微凸塊48的形成不限
於上述方法,上述方法可由任何適用於微凸塊48的製造的方法來取代。例如,可使用塌陷高度控制晶片連接新製程(controlled collapse chip connection new process;C4NP)來製造微凸塊48。
可將微凸塊48置於如第1(a)圖所示的中介層10的一凸塊下金屬墊391上。微凸塊48是提供一晶片與中介層10之間、經由凸塊下金屬墊391的一垂直連接,在本說明書中有時會將凸塊下金屬墊391稱為接觸墊。凸塊下金屬墊391可填滿或局部填充例如一絕緣體層37等的一絕緣體層的一開口。凸塊下金屬墊391可進一步連接於中介層10內、凸塊下金屬墊391的下方的一金屬層或一接點。微凸塊48的高度可以是5μm至50μm。隨著特徵尺寸與封裝尺寸的持續縮減,本發明各實施例中的微凸塊48的尺寸可小於前述的尺寸。另一方面,微凸塊48的尺寸可大於前述的尺寸,例如與一覆晶凸塊或一封裝體凸塊的尺寸一般的尺寸,隨著使用者愛好的特定用途而定。
如第1(c)圖所示,可將微凸塊線42置於一凸塊下金屬層390上,凸塊下金屬層390是形成於絕緣體層37的上方,而絕緣體層37是第1(a)圖所示的中介層10的一部分。微凸塊線42可為中介層10的上方的不同晶片之間的訊號傳輸,提供一水平的連接。經由微凸塊線42傳輸的電性訊號不會通過中介層10。在凸塊下金屬層390與微凸塊線42下方的絕緣體層37並非導電性,因此微凸塊線42中的訊號不會傳入或穿透中介層10。微凸塊線42可具有形成於一銅層421的上方的一軟銲凸塊423,可視需求選用的一鎳層425可位於軟銲凸塊423與銅層421之間。
此外,如第1(d)圖所示,可形成一微凸塊線46而將
二個凸塊下金屬墊391連接在一起,其中二個凸塊下金屬墊391都在第1(a)圖所示的中介層10內。微凸塊線46可對從中介層10的一部分傳輸到中介層10的另一部分的訊號,提供一連接。與在中介層內作訊號傳輸的情況相比,這樣的微凸塊線46可具有較低的電阻與較低的線路密度,因此減少線路間的干擾與串音,而增加、改善在中介層10內傳輸的訊號之訊號強度。微凸塊線46可具有形成於一銅層421的上方的一軟銲凸塊423,可視需求選用的一鎳層425可位於軟銲凸塊423與銅層421之間。此處可具有形成於絕緣體層37的上方與銅層421的下方的一凸塊下金屬層390,凸塊下金屬層390可以與凸塊下金屬墊391同時形成。
可以有複數個微凸塊線是與第1(c)圖所示的微凸塊線42類似,其是形成於凸塊下金屬層390的上方,並水平地連接不同晶片。同樣地,可以有複數個微凸塊線是與第1(d)圖所示的微凸塊線46類似,傳輸中介層10內的訊號。形成微凸塊線42、微凸塊線46的材料,可以與形成微凸塊48的材料實質上相同。微凸塊線42、微凸塊線46可包含複數層。例如,在凸塊下金屬層390上方的是一銅層421,在銅層421上方的可以是可依需求選用的一鎳層425,而在鎳層425上方的是一軟銲凸塊423,其中軟銲凸塊423可以是無鉛軟銲凸塊,例如SnAg,其中Ag含量為1%至2%、Sn含量為99%至98%。銅層421、鎳層425以及軟銲凸塊423三層的高度可相同或不同,其可依據不同的需求而變化。例如,銅層421、鎳層425、無鉛的軟銲凸塊423的高度比可為15/1.5/10左右。微凸塊線42的總高度可在5μm至
50μm的範圍內,例如為27μm。
微凸塊線42、微凸塊線46的形狀可以是矩形,其寬度可為5μm至100μm,微凸塊線42、微凸塊線46的寬度可相同。微凸塊線42、微凸塊線46可具有寬的、窄的或一端逐漸變細的形狀,而微凸塊線42、微凸塊線46的本體可具有實質上為常數的厚度。微凸塊線42、微凸塊線46亦可以是其他形狀,例如在俯視圖表現為圓形、八邊形、在伸長的相對二端具有梯形之伸長的六邊形、卵形、鑽石形等等。
如第1(b)-1(d)圖所示,在形成微凸塊48時,藉由依序鍍製銅層421、依需求選用的鎳層425與例如為SnAg的無鉛軟銲凸塊423,可一起形成微凸塊線42、微凸塊線46與微凸塊48。此後,可對無鉛軟銲凸塊423進行重流。上述重流的製程改變軟銲凸塊423的形狀,成為圓弧形,但不會影響軟銲凸塊423下方的銅層421之形狀。用於微凸塊線42、微凸塊線46的銅層421的長度可以比用於微凸塊48的銅層421的長度還長,因為微凸塊線42、微凸塊線46是用來作為二個晶片之間或二個接觸墊之間的水平連接,而微凸塊48是用來在一個位置將一晶片連接於中介層10。微凸塊線42、微凸塊線46、微凸塊48各層的形成可使用一沉積製程,例如濺鍍、蒸鍍、電鍍、印刷、軟銲料轉移等等。
第1(a)圖所示的半導體裝置封裝體100的更詳細的結構,是以剖面圖的形式繪示於第2(a)、2(b)圖中。如第2(a)圖所示,一半導體裝置封裝體100是形成於一中介層10上。中介層10可包含:一基板30,具有複數個貫穿孔(through vias;
TV)303與複數個裝置305;複數個接觸墊32、一鈍化層34、一絕緣體層36、一重分佈層38、另一個絕緣體層37、一凸塊下金屬層390以及一凸塊下金屬墊391,其中凸塊下金屬墊391覆蓋絕緣體層37上的複數個開口。
微凸塊層40可形成於中介層10的上方,其中微凸塊層40包含微凸塊線42與微凸塊48。微凸塊線42是在中介層10的凸塊下金屬層390上。然而,在微凸塊線42的下方的凸塊下金屬層390仍在一絕緣體層例如絕緣體層37的上方,因此藉由微凸塊線42傳輸的訊號不會傳入中介層10。另一方面,微凸塊48是連接於凸塊下金屬墊391,而凸塊下金屬墊391是進一步連接於中介層10的內部的裝置與金屬層。可在中介層10的上方放置第一晶片56與第二晶片58,其中第一晶片56與第二晶片58是藉由連接於微凸塊線42與微凸塊48的連接物54而連接於微凸塊層40。一底填充物(underfill)57是填充於中介層10與第一晶片56、第二晶片58之間的間隙,並覆蓋微凸塊線42、微凸塊48與連接物54。以上討論的各個結構,會在後續的段落中作更詳細的討論。
此外,在第2(b)圖中,微凸塊層40微凸塊層40具有微凸塊線46與微凸塊48,可形成一微凸塊線46而將二個凸塊下金屬墊391連接在一起,其中二個凸塊下金屬墊391都在中介層10內。微凸塊線46可對從中介層10的一部分傳輸到中介層10的另一部分的訊號,提供一連接。與在中介層內作訊號傳輸的情況相比,這樣的微凸塊線46亦可具有較低的電阻與較低的線路密度,因此減少線路間的干擾與串音,而增加、改善在中介層
10內傳輸的訊號之訊號強度。可在中介層10的上方放置第一晶片56與第二晶片58,第一晶片56與第二晶片58是藉由連接於微凸塊線46與微凸塊48的連接物54而連接於微凸塊層40。一底填充物57是填充於中介層10與第一晶片56、第二晶片58之間的間隙,並覆蓋微凸塊線46、微凸塊48與連接物54。
如第2(a)、2(b)圖所示,中介層10可包含一基板30。在基板30的一表面,形成有一導電層來作為接觸墊32,在基板30的上方可以有複數個接觸墊32。可形成穿透基板30的複數個貫穿孔303,複數個裝置305(無論是主動裝置或被動裝置)也可同樣地形成於基板30內。中介層10可更包含一鈍化層34、一絕緣體層36、一重分佈層38以及另一個絕緣體層37。一凸塊下金屬層390與一凸塊下金屬墊391是形成於絕緣體層37上,其中凸塊下金屬墊391是覆蓋開口並位於絕緣體層37上。
用於中介層10的基板30可以是例如已摻雜或未摻雜一矽基板、或是一絕緣層上覆矽(silicon-on-insulator;SOI)基板的一主動層,用來對中介層10提供支持。然而,基板30亦可以是一玻璃基板、一陶瓷基板、一聚合物基板或其他任何可以提供一適當的保護及/或互連功能的基板,這些與其他適合的材料亦可用來作為基板30,取代上述的矽。
在基板30內,可形成有複數個裝置305。對於本發明所屬技術領域中具有通常知識者而言,可以理解各式各樣的主動裝置與被動裝置例如電晶體、電容器、電阻器、電感器等等,可用來滿足用於中介層10的設計所需的結構性與功能性的需求。可使用任何適當的方法,將裝置305形成於基板30內、
甚至形成於基板30的表面上。
然而,對於本發明所屬技術領域中具有通常知識者而言,可以理解上述具有裝置305的基板30並非唯一可使用的基板,亦可使用其他替代性的基板,例如一封裝基板或其內不具裝置305的一中介層。這些基板及其他適用的基板可相互替換使用,且應包含於本實施例的範疇內。
可形成穿透基板30的複數個貫穿孔303。貫穿孔303的形成,可藉由塗佈一適合的光阻並使其顯影,然後蝕刻基板30以產生貫穿孔的開口。用於貫穿孔303的開口形成後,可進一步延伸到基板30內並達到一深度,此深度至少要大於最終所需的高度。因此,上述深度可以是在基板30上的表面以下1μm至700μm,這些用於貫穿孔303的開口的直徑可為1μm至100μm。然後,可以藉由一阻障層與一導電材料來填充這些用於貫穿孔303的開口,用於填充的製程例如為化學氣相沉積(chemical vapor deposition;CVD)製程、電漿增益化學氣相沉積(plasma enhanced chemical vapor deposition;PECVD)製程、濺鍍製程或有機金屬化學氣相沉積(metal organic chemical vapor deposition;MOCVD)製程。在這些用於貫穿孔303的開口的外側的多餘的阻障層,可經由例如化學機械研磨(chemical mechanical polish;CMP)等的研磨製程來移除。此後,可藉由一平坦化製程例如化學機械研磨或蝕刻,而從基板30的第二側進行薄化,以曝露出這些用於貫穿孔303的開口,而形成導電材料構成的貫穿孔303,此貫穿孔303的延伸是穿透基板30。
可在基板30上形成複數個接觸墊32,接觸墊32可
使用鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他導電材料來製造。接觸墊32的沉積是使用電解電鍍(electrolytic plating)製程、濺鍍製程、物理氣相沉積(physical vapor deposition;PVD)製程或非電化學鍍(electroless plating)製程。圖中所示的接觸墊32的尺寸、形狀、位置,僅止於圖示的目的,不應用以限縮本實施例的範圍及申請專利範圍。複數個接觸墊32的尺寸可以相同或不同。
一鈍化層34可形成在基板30的表面的上方與接觸墊32的上方,作為結構上的支撐與物理上的隔離。鈍化層34可由氮化矽(SiN)、二氧化矽(SiO2)、氧氮化矽(SiON)、聚醯亞胺(polyimide;PI)、苯並環丁烯(benzocyclobutene;BCB)、聚苯噁唑(polybenzoxazole;PBO)或其他絕緣材料所製造。可使用一罩幕定義光阻蝕刻製程(mask-defined photoresist etching process),移除鈍化層34的一部分,以形成鈍化層34的開口來曝露出接觸墊32。上述開口的尺寸、形狀、位置,僅僅止於圖示的目的,不應用以限縮本實施例的範圍及其所支持之申請專利範圍。
可形成一絕緣體層例如一聚合物的絕緣體層36,絕緣體層36可形成於鈍化層34的上方與鈍化層34的開口的上方,以覆蓋接觸墊32。可形成絕緣體層36的開口,以曝露出接觸墊32。可使用一罩幕定義光阻蝕刻製程(mask-defined photoresist etching process),移除絕緣體層36的一部分,以形成絕緣體層36的開口來曝露出接觸墊32。上述開口的尺寸、形狀、位置,僅止於圖示的目的,不應用以限縮本實施例的範圍
及申請專利範圍。
然後,可沿著並反映絕緣體層36的輪廓,形成一重分佈層38,重分佈層38可以是連續的,並覆蓋曝露的接觸墊32。儘管繪示於第1(c)圖的重分佈層38是單層介電層與單層內連線的結構,重分佈層38亦可以是由數個交互層疊的介電層與導電材料層所形成,並可經由任何適當的製程(例如沉積法、鑲嵌製程、雙鑲嵌製程等)來形成。重分佈層38可由例如鋁、銅或銅合金來製造,重分佈層38並可藉由電解電鍍製程、濺鍍製程、物理氣相沉積製程或非電化學鍍製程來製造。重分佈層38可以是由單層或多層結構來製造,上述多層結構是使用一黏著層例如為Ti、TiW、TaN、Ta或Cr。中介層10可包含數個重分佈層,以形成層間互連的網路,其可根據半導體裝置的功能而重分佈層38電性連接於接觸墊32。
另一個絕緣體層37可形成於重分佈層38上,絕緣體層37可作為中介層10的頂層與表面層,並可形成絕緣體層37的開口,以曝露出重分佈層38。可使用一罩幕定義光阻蝕刻製程(mask-defined photoresist etching process),移除絕緣體層37的一部分,以形成絕緣體層37的開口來曝露出重分佈層38。上述開口的尺寸、形狀、位置,僅止於圖示的目的,不應用以限縮本實施例的範圍及申請專利範圍。絕緣體層37可由氮化矽(SiN)、二氧化矽(SiO2)、氧氮化矽(SiON)、聚醯亞胺(polyimide;PI)、苯並環丁烯(benzocyclobutene;BCB)、聚苯噁唑(polybenzoxazole;PBO)或其他絕緣材料所製造,絕緣體層37的形成方法包含旋轉塗佈法或其他通常使用的方法。絕緣
體層37的厚度可例如是5μm至30μm,但前述的尺寸僅僅是用於舉例,上述尺寸會隨著積體電路的尺寸的縮減等情況而有所變化。
可形成一凸塊下金屬層,其包含凸塊下金屬墊391與凸塊下金屬層390。凸塊下金屬墊391是被形成為圍繞絕緣體層37的開口,並電性連接於重分佈層38,而凸塊下金屬層390則形成於絕緣體層37上。凸塊下金屬墊391與凸塊下金屬層390可以是由銅或銅合金形成,而上述銅合金中與銅形成合金的元素可包含銀、鉻、鎳、錫、金與上述之組合。另外,在上述銅層的上方,尚可形成附加層,例如一鎳層、一無鉛的預塗軟銲料(pre-solder)層或上述之組合。凸塊下金屬墊391與凸塊下金屬層390的厚度可為1μm至20μm。
前述的中介層10僅為一實施例的一個範例,還可有許多其他不同於前文對第2(a)、2(b)圖所作敘述之中介層的變化形態。例如,絕緣體層36可不存在於某些中介層中;或是在用來形成第2(a)、2(b)圖的半導體裝置封裝體100的中介層的某些實施例中,可具有多層的鈍化層34或絕緣體層37。
可使用中介層10並經由微凸塊層40與連接物54來封裝第一晶片56與第二晶片58,而第一晶片56、第二晶片58與中介層10之間的間隙,可藉由一底填充物57來覆蓋。第一晶片56與第二晶片58是連接於連接物54,而連接物54是置於微凸塊層40上。微凸塊層40包含一微凸塊48與一微凸塊線42或微凸塊線46。關於微凸塊層40的細節,已在前文對第1(b)-1(c)圖的說明中,作了相當詳細的敘述。
連接物54可用來提供微凸塊層40與第一晶片56、第二晶片58之間的連接。連接物54可以是接觸凸塊例如為微凸塊或塌陷高度控制晶片連接(controlled collapse chip connection;C4)凸塊,其材料可包含例如錫或其他適當的材料例如銀或銅。在一實施例中,其中連接物54是錫軟銲凸塊,則此連接物54的形成,可先經由任何適合的製程例如蒸鍍、電鍍、印刷、軟銲料轉移(solder transfer)、植球等形成一錫層至約100μm的一較佳厚度。一旦在上述結構上完成錫層的形成,可施行一重流步驟,來使上述材料的形狀成為所需的凸塊形狀。
可在第一晶片56、第二晶片58與中介層10之間使用底填充物57,以強化第一晶片56、第二晶片58對中介層10的黏著力,並有助於避免熱應力破壞第一晶片56、第二晶片58與中介層10之間的連接。一般而言,選擇底填充物57所使用的材料例如有機樹脂,以控制底填充物57的熱膨脹係數與收縮率。首先,塗佈液態有機樹脂,使其流入第一晶片56、第二晶片58與中介層10的表面之間的間隙,接下來對上述液態有機樹脂進行熟化(curing),以控制發生於熟化過程中的底填充物之收縮率。
第3(a)~3(d)圖是顯示具有使用一微凸塊層的中介層之半導體裝置封裝體的形成方法的一實施例,以形成如第2(a)圖所示的裝置。本發明所屬技術領域中具有通常知識者,可輕易地使用一相似的製程來形成此處未顯示的任何其他的實施例。
第3(a)圖顯示的是已敘述於第2(a)圖的一中介層10。中介層10可包含具有貫穿孔303與裝置305的一基板30、複數個接觸墊32、一鈍化層34、一絕緣體層36、一重分佈層38、另一個絕緣體層37以及一凸塊下金屬層,上述凸塊下金屬層包含複數個凸塊下金屬墊391與一凸塊下金屬層390,上述凸塊下金屬墊391是被形成來覆蓋絕緣體層37的開口,上述凸塊下金屬層390是在絕緣體層37上。關於中介層10的每一層的細節與構件,已敘述於前文。
第3(b)圖是繪示微凸塊層40的形成,微凸塊層40是包含一微凸塊線42與一微凸塊48。微凸塊48是連接於凸塊下金屬墊391,並經由接觸墊32與重分佈層38,進一步連接於中介層10的貫穿孔303或裝置305。微凸塊線42亦被置於凸塊下金屬層390上,但在絕緣體層37,而與中介層10內的任何裝置或電性連接物絕緣。微凸塊層40可實質上同時形成,也就是微凸塊線42與微凸塊48可實質上同時形成,以節省成本。可藉由依序鍍製銅層421、鎳層425與例如為SnAg的無鉛軟銲凸塊423,一起形成微凸塊線42與微凸塊48。微凸塊線42、微凸塊48各層的形成可使用一沉積製程,例如濺鍍、蒸鍍、電鍍、印刷、軟銲料轉移等等。用於微凸塊線42的銅層421的長度可以比微凸塊48的銅層421的長度還長,因為微凸塊線42是用來作為第一晶片56的一第一位置與第二晶片58的一第二位置之間的水平連接,而微凸塊48是用來僅在一個位置將一晶片連接於中介層10。
第3(c)圖是繪示使用連接物54將第一晶片56與第
二晶片58連接於微凸塊層40以形成第2(a)圖所示的半導體裝置封裝體100。第二晶片58是置於微凸塊線42的上方,連接物54是在第二晶片58的一第一位置將第二晶片58電性連接於微凸塊線42,而另一個連接物54是在第二晶片58之異於上述第一位置的一第二位置將第二晶片58電性連接於微凸塊48。一第一晶片56是置於微凸塊線42的上方並電性連接於微凸塊線42,因此微凸塊線42是藉由連接物54的路徑將第一晶片56電性連接於第二晶片58,而不會通過中介層10。在已完成將第一晶片56與第二晶片58置於微凸塊48上與微凸塊線42上之後,可施以一重流製程。上述重流製程是改變軟銲凸塊423的形狀而使其變成圓弧形,作為微凸塊48與微凸塊線42,但上述重流製程不會影響軟銲凸塊423下方的銅層421。
第3(d)圖是繪示一底填充物57填充微凸塊線42、微凸塊48與第一晶片56、第二晶片58之間的一間隙。一般而言,選擇底填充物57所使用的材料例如有機樹脂,以控制底填充物57的熱膨脹係數與收縮率。首先,塗佈液態有機樹脂,使其流入第一晶片56、第二晶片58與中介層10的表面之間的間隙,接下來對上述液態有機樹脂進行熟化,以控制發生於熟化過程中的底填充物之收縮率。
顯示於第3(a)~3(d)圖的製程僅止於圖示的目的,不應用以限縮本實施例的範圍及申請專利範圍。還可有許多其他製程步驟與製程材料的變化形態,可被本發明所屬技術領域中具有通常知識者順利地理解。
如以上所述,本發明揭露一種方法與裝置,適用
於使用一微凸塊層在一中介層上形成一半導體裝置封裝體。上述微凸塊層可包含微凸塊與微凸塊線,其中一微凸塊是用於一晶片與上述中介層之間的一垂直連接,而一微凸塊線是用於位在上述中介層的上方的不同晶片之間的信號傳輸所使用的水平連接。此外,形成於上述中介層的上方的上述微凸塊線也同樣地可用來傳遞此中介層中的訊號。與上述中介層內的金屬線相比,上述微凸塊線具有較低的線路密度與更低的電阻,因此可減少線路間的干擾(interference)與串音(crosstalk),而增加訊號強度。上述微凸塊線可以與上述微凸塊同時形成,具有低成本或未增加成本。
本發明的一實施例是提供一種半導體裝置封裝體,包含一中介層(interposer)、一第一晶片與一第二晶片以及一微凸塊層。上述中介層具有一表面與一第一接觸墊,上述表面是由一絕緣體層形成,上述第一接觸墊覆蓋上述絕緣體層的一第一開口並與上述中介層中的一金屬層接觸。上述第一晶片與上述第二晶片是在上述中介層的上方。上述微凸塊層具有一第一微凸塊線與一微凸塊,上述第一微凸塊線是在上述中介層的上述絕緣體層的上方,上述微凸塊是在上述中介層的上述第一接觸墊的上方,其中上述第一微凸塊線是電性連接上述第一晶片與上述第二晶片,上述微凸塊是將上述第一晶片電性連接於上述中介層中的上述金屬層。
本發明的又一實施例是提供一種半導體裝置封裝體的形成方法,包含下列步驟:提供一中介層(interposer),上述中介層具有一表面與一接觸墊,上述表面是由一絕緣體層形
成,上述接觸墊覆蓋上述絕緣體層的一開口並與上述中介層中的一金屬層接觸;在上述中介層的上方形成一微凸塊層,其中上述微凸塊層具有一第一微凸塊線與一微凸塊,上述第一微凸塊線是在上述中介層的上述絕緣體層的上方,上述微凸塊是電性連接於上述中介層的上述接觸墊;將一第一晶片置於上述第一微凸塊線的上方,在上述第一晶片的一第一位置將上述第一晶片電性連接電性連接於上述第一微凸塊線,並在上述第一晶片之不同於上述第一位置的一第二位置將上述第一晶片電性連接電性連接於上述微凸塊;以及將一第二晶片置於上述第一微凸塊線的上方,並將上述第二晶片電性連接於上述第一微凸塊線。
本發明的又另一實施例是提供一種半導體裝置封裝體,其包含一中介層(interposer)、一晶片以及一微凸塊層。上述中介層的一表面是由一絕緣體層形成,上述中介層具有一第一接觸墊、一第二接觸墊與一第三接觸墊,上述第一接觸墊覆蓋上述絕緣體層的一第一開口,上述第二接觸墊覆蓋上述絕緣體層的一第二開口,上述第三接觸墊覆蓋上述絕緣體層的一第三開口。上述晶片是在上述中介層的上方。上述微凸塊層具有一第一微凸塊線與一微凸塊,上述第一微凸塊線是在上述中介層的上述絕緣體層的上方,上述微凸塊是在上述中介層的上述第一接觸墊的上方,其中上述第一微凸塊線是電性連接上述第二接觸墊與上述第三接觸墊,上述微凸塊是將上述晶片電性連接於上述中介層中的上述第一接觸墊。
雖然本發明已以較佳實施例揭露如上,然其並非
用以限定本發明,任何本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧中介層
37‧‧‧絕緣體層
40‧‧‧微凸塊層
46‧‧‧微凸塊線
390‧‧‧凸塊下金屬層
391‧‧‧凸塊下金屬墊
421‧‧‧銅層
423‧‧‧軟銲凸塊
425‧‧‧鎳層
Claims (10)
- 一種半導體裝置封裝體,包含:一中介層(interposer),具有一表面與一第一接觸墊,該表面是由一絕緣體層形成,該第一接觸墊覆蓋該絕緣體層的一第一開口並與該中介層中的一金屬層接觸;一第一晶片與一第二晶片,在該中介層的上方,其中該第一晶片被設置為橫向地相鄰於該第二晶片;以及一微凸塊層,包括:一第一微凸塊線,位於該中介層的該絕緣體層的上方,其中介於該第一晶片與該第二晶片之間的電子訊號係透過該第一微凸塊線傳輸,且其中在該第一晶片與該第二晶片之間透過該第一微凸塊線傳輸的該等電子訊號不會通過該中介層傳輸;以及一微凸塊,位於該中介層的該第一接觸墊的上方,其中該微凸塊是將該第一晶片電性連接於該中介層中的該金屬層。
- 如申請專利範圍第1項所述之半導體裝置封裝體,其中該第一微凸塊線包含一銅層與一軟銲材料層。
- 如申請專利範圍第1項所述之半導體裝置封裝體,其中該微凸塊層更包含一第二微凸塊線,該第二微凸塊線是在該絕緣體層的上方,並電性連接在該中介層上方的複數個晶片。
- 如申請專利範圍第1項所述之半導體裝置封裝體,更包含一凸塊下金屬(under bump metal;UBM)層,該凸塊下金屬層是在該絕緣體層與該第一微凸塊線之間。
- 如申請專利範圍第1項所述之半導體裝置封裝體,其中該微凸塊層更包含一第三微凸塊線,該第三微凸塊線是在該絕緣體層的上方並連接於一第二接觸墊與一第三接觸墊,其中該第二接觸墊覆蓋該絕緣體層的一第二開口並與該中介層中的該金屬層接觸,該第三接觸墊覆蓋該絕緣體層的一第三開口並與該中介層中的該金屬層接觸。
- 如申請專利範圍第1項所述之半導體裝置封裝體,其中該中介層更包含一鈍化層與一重分佈層(redistribution layer)。
- 如申請專利範圍第1項所述之半導體裝置封裝體,其中藉由一連接物而使該第一微凸塊線連接於該第一晶片,且一底填充物(underfill)是填充該第一微凸塊線與該第一晶片之間的間隙。
- 一種半導體裝置封裝體的形成方法,包含下列步驟:提供一中介層(interposer),該中介層具有一表面與一接觸墊,該表面是由一絕緣體層形成,該接觸墊覆蓋該絕緣體層的一開口並與該中介層中的一金屬層接觸;在該中介層的上方形成一微凸塊層,其中該微凸塊層具有一第一微凸塊線與一微凸塊,該第一微凸塊線是在該中介層的該絕緣體層的上方,該微凸塊是電性連接於該中介層的該接觸墊;將一第一晶片置於該第一微凸塊線的上方,在該第一晶片的一第一位置將該第一晶片電性連接於該第一微凸塊線,並在該第一晶片之不同於該第一位置的一第二位置將該第一晶片電性連接於該微凸塊;以及 將一第二晶片置於該第一微凸塊線的上方且橫向地相鄰於該第一晶片,其中介於該第一晶片與該第二晶片之間的電子訊號係透過該第一微凸塊線傳輸,且其中在該第一晶片與該第二晶片之間透過該第一微凸塊線傳輸的該等電子訊號不會通過該中介層傳輸。
- 如申請專利範圍第8項所述之半導體裝置封裝體的形成方法,其中形成該微凸塊層的步驟包含:形成一銅層;然後在該銅層的上方形成一軟銲材料層。
- 一種半導體裝置封裝體,包含:一中介層(interposer),其一表面是由一絕緣體層形成,該中介層具有一第一接觸墊、一第二接觸墊與一第三接觸墊,該第一接觸墊覆蓋該絕緣體層的一第一開口,該第二接觸墊覆蓋該絕緣體層的一第二開口,該第三接觸墊覆蓋該絕緣體層的一第三開口;一第一晶片,在該中介層的上方;一第二晶片,在該中介層的上方且橫向地相鄰於該第一晶片;以及一微凸塊層,具有一第一微凸塊線與一微凸塊,該第一微凸塊線是在該中介層的該絕緣體層的上方且橫跨該第一晶片與第二晶片,該微凸塊是在該中介層的該第一接觸墊的上方,其中該第一微凸塊線是電性連接該第二接觸墊與該第三接觸墊,該微凸塊是將該晶片電性連接於該中介層中的該第一接觸墊。
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JP2018116974A (ja) * | 2017-01-16 | 2018-07-26 | ラピスセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
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US9627223B2 (en) | 2017-04-18 |
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US20150249019A1 (en) | 2015-09-03 |
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