TWI524509B - 積體電路及製作積體電路的方法 - Google Patents

積體電路及製作積體電路的方法 Download PDF

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TWI524509B
TWI524509B TW102101493A TW102101493A TWI524509B TW I524509 B TWI524509 B TW I524509B TW 102101493 A TW102101493 A TW 102101493A TW 102101493 A TW102101493 A TW 102101493A TW I524509 B TWI524509 B TW I524509B
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integrated circuit
jfet
power mosfet
gate
drain
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TW201342582A (zh
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李鐵生
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茂力科技股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7815—Vertical DMOS transistors, i.e. VDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode

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Description

積體電路及製作積體電路的方法
本發明係有關一種電子電路，更具體地說，本發明係有關一種積體電路及製作積體電路的方法。
場效應電晶體(FET)被廣泛應用於各種電子電路中。在某些應用情況中，需要檢測場效應電晶體的汲極電壓來控制場效應電晶體的運行。例如，控制器根據該汲極電壓控制場效應電晶體的導通或者斷開。但在某些應用情況中，場效應電晶體的汲極電壓可能為高電壓。若將該汲極高電壓直接輸送至控制器，極有可能損壞控制器。
因此，本發明之目的在於解決現有技術的上述技術問題，提出一種改進的積體電路及製作積體電路的方法。
依據本發明的實施例，提出了一種積體電路，包括：功率MOSFET，具有汲極、閘極和源極；JFET，具有汲極、閘極和源極，所述JFET的汲極係耦接至所述功率 MOSFET的汲極，所述JFET和功率MOSFET共用所述積體電路的基板上的漂移區；檢測引腳，係耦接至所述JFET的源極；源極引腳，係耦接至所述功率MOSFET的源極；閘極引腳，係耦接至所述功率MOSFET的閘極；汲極引腳，係耦接至所述功率MOSFET的汲極和所述JFET的汲極。
依據本發明的實施例，還提出了一種製作積體電路的方法，包括：在基板上形成外延層；在外延層內形成垂直型MOSFET的源極和閘極；在外延層內形成垂直型JFET的源極和閘極；其中，所述垂直型JFET和垂直型MOSFET共用漂移區，所述漂移區包括所述外延層；所述基板用做為所述垂直型MOSFET的汲極和垂直型JFET的汲極。
依據本發明的實施例，還提出了一種積體電路，包括：功率MOSFET；JFET，與所述功率MOSFET共用基板上的漂移區；檢測引腳，經由所述JFET而被耦接至所述功率MOSFET的汲極，所述檢測引腳為所述積體電路的外部引腳，該檢測引腳允許外部電路檢測所述功率MOSFET的汲極電壓；閘極引腳，係耦接至功率MOSFET的閘極，所述閘極引腳為所述積體電路的外部引腳。
依據本發明之各個態樣的上述積體電路和製作積體電路的方法，透過簡單的製作程序來確保低電壓位準的控制器接收功率MOSFET的汲極高電壓。
100‧‧‧控制裝置
101‧‧‧控制器
102‧‧‧接面型場效應電晶體(JFET)
110‧‧‧分立型裝置
112‧‧‧金屬氧化物半導體場效應電晶體
201‧‧‧端子
202‧‧‧端子
203‧‧‧端子
210‧‧‧控制器
220‧‧‧積體電路
221‧‧‧端子(檢測引腳)
222‧‧‧端子(閘極引腳)
223‧‧‧端子(源極引腳)
224‧‧‧端子(汲極引腳)
225‧‧‧接面型場效應電晶體(JFET)
226‧‧‧垂直功率MOSFET
301‧‧‧N-外延層
302‧‧‧N+矽基板
303‧‧‧保護環
304‧‧‧N+型源極區(Src)
305‧‧‧閘極
306‧‧‧P型體區
307‧‧‧源極電極
308‧‧‧靜電放電(ESD)電極
309‧‧‧靜電放電(ESD)焊墊
315‧‧‧P型體區
316‧‧‧N+源極區
317‧‧‧閘極
319‧‧‧分界線
320‧‧‧汲極電極
321‧‧‧層間電介質
331‧‧‧溝槽
334‧‧‧層間電介質
335‧‧‧閘極材料
336‧‧‧閘極電介質
901‧‧‧掩膜
902‧‧‧掩膜
903‧‧‧掩膜
451‧‧‧端子(VG引腳)
452‧‧‧端子(VSS引腳)
453‧‧‧端子(PGND引腳)
454‧‧‧端子(VD引腳)
461‧‧‧偏置電壓
481‧‧‧跨導放大器(gm)
482‧‧‧比較器
483‧‧‧MOSFET開關
484‧‧‧電阻器
490‧‧‧控制器
491‧‧‧偏置電壓
圖1示意性地示出了檢測金屬氧化物半導體場效應電晶體112之汲極電壓的電路；圖2為依據本發明實施例的積體電路220的電路結構示意圖；圖3示意性地示出了依據本發明之一個實施例的積體電路220的剖面圖；圖4~15示意性地示出了依據本發明另一個實施例的積體電路220的製作流程圖；圖16為依據本發明又一實施例的採用積體電路220的電路的結構示意圖；圖17具體示出了圖16所示的採用積體電路220的電路的結構示意圖。
下面將詳細描述本發明的具體實施例，應當注意，這裏描述的實施例只用來舉例說明，並不用來限制本發明。在以下描述中，為了提供對本發明的透徹理解，闡述了大量的特定細節。然而，對於本領域普通技術人員顯而易見的是：不必採用這些特定細節來實行本發明。在其他實施例中，為了避免混淆本發明，並未具體描述公知的電路、材料或方法。
在整個說明書中，對“一個實施例”、“實施例”、“一個示例”或“示例”的提及意味著：結合該實施例或示例描 述的特定特徵、結構或特性被包含在本發明至少一個實施例中。因此，在整個說明書的各個地方出現的短語“在一個實施例中”、“在實施例中”、“一個示例”或“示例”不一定都指同一個實施例或示例。此外，可以以任何適當的組合和/或子組合而將特定的特徵、結構或特性組合在一個或多個實施例或示例中。此外，本領域普通技術人員應當理解，在此提供的附圖都是為了說明的目的，並且附圖不一定是按比例來予以繪製的。應當理解，當稱元件“係耦接到”或“係連接到”另一元件時，它可以係直接耦接或耦接到另一元件或者可以存在有中間元件。相反地，當稱元件“係直接耦接到”或“係直接連接到”另一元件時，不存在有中間元件。相同的附圖標記指示相同的元件。這裏使用的術語“和/或”包括一個或多個相關列出的專案的任何和所有組合。
圖1示意性地示出了檢測金屬氧化物半導體場效應電晶體(MOSFET)112之汲極電壓的電路。在圖1所示之實施例中，MOSFET 112為功率金屬氧化物半導體場效應電晶體，其汲極電壓可能達到30~100 V。但控制器101只能處理3~6 V的電壓。此時，控制器101透過接面型場效應電晶體(JFET)102來檢測MOSFET 112的汲極電壓，使得控制器101無需直接接收高電壓。
和典型的功率裝置一樣，MOSFET 112為獨立封裝的分立型裝置110。JFET 102和控制器101被集成在相同的裸片(bare die)上，並被封裝在一起做為控制裝置100。但 將JFET 102和控制器101集成在相同裸片上至少有2個缺點。第一，由於在某些應用情況，MOSFET 112的汲極電壓為-0.8至-1.0 V，透過JFET 102而將控制器101連接至外部MOSFET 112可能會引起基板注入；第二，製作控制器101的製程可以處理低的臨界電壓，但該製程不能處理高於30 V的電壓，從而限制了其在高電壓情況的應用。
圖2為依據本發明實施例的積體電路220的電路結構示意圖。在圖2所示之實施例中，積體電路220只包括形成在相同裸片上並封裝在一起的垂直JFET 225和垂直功率MOSFET 226。跨接在功率MOSFET 226之兩端上的二極體為功率MOSFET 226的二極體，而非獨立的分立裝置。在一個實施例中，積體電路220的封裝組件(亦即，JFET 225和功率MOSFET 226的封裝組件)為四個端子的小外型積體電路(small outline integrated circuit，SOIC)封裝組件，例如，積體電路220包括端子221(檢測引腳)、端子222(閘極引腳)、端子223(源極引腳)以及端子224(汲極引腳)。其中，端子221~224為外部引腳，透過該四個端子而允許外部電路連接至積體電路220。端子221(亦即，檢測引腳)透過長通的JFET 225而被連接至功率MOSFET 226。透過JFET 225，控制器210避免被直接連接至可能為高電壓的功率MOSFET 226的汲極。在圖2所示之實施例中，檢測引腳(端子221)係連接至JFET 225的源極；閘極引腳(端子222)、源極引腳(端子223)和汲極引 腳(端子224)分別被連接至功率MOSFET 226的閘極、源極和汲極；JFET 225的汲極係連接至功率MOSFET 226的汲極。
積體電路220可被應用於檢測汲極電壓的情況。例如，積體電路220可被使用做為理想二極體(導通壓降小於常規二極體的二極體)。當然，本領域的技術人員應當意識到，積體電路220也可應用於其他多種情況。
在一個實施例中，為了便於檢測功率MOSFET 226的汲極電壓，JFET 225和功率MOSFET 226被製作在相同的基板上以共用漂移區。漂移區包括形成在基板上的外延層，所述基板用做為JFET 225的汲極和功率MOSFET 226的汲極。由於JFET 225和MOSFET 226共用漂移區，所以兩者具有相似的電學特性，因此，JFET 225和MOSFET 226可使用允許高電壓的相同分立製作程序來予以製作。
在圖2所示之實施例中，積體電路220為控制器210的外部裝置。因此，控制器210可被製作在另外的基板上，並且無需受限於JFET 225和功率MOSFET 226的電學特性要求。在一個實施例中，控制器210可為二極體-模擬器(diode-emulator)控制器、太陽電池板控制器、電壓調整器的同步開關的控制器，等等。在一個實施例中，控制器210包括端子201、202和203，其中，端子201係連接至積體電路220的檢測引腳(端子221)，以使控制器210檢測功率MOSFET 226的汲極電壓；端子202和端子 203分別被連接至積體電路220的閘極引腳(端子222)和源極引腳(端子223)，以使控制器210控制功率MOSFET 226。
圖3示意性地示出了依據本發明之一個實施例的積體電路220的剖面圖。積體電路220將JFET 225和功率MOSFET 226一起集成在相同的N+矽基板302上。外延層301為N型(例如，磷)輕度摻雜，基板302為N型重度摻雜。在圖3所示之實施例中，虛線319示意性地表示JFET 225和功率MOSFET 226的分界線。
在圖3所示之實施例中，功率MOSFET 226為垂直型溝槽閘極金屬氧化物半導體場效應電晶體。所述功率MOSFET 226包括N+型源極區(Src)304、P型體區(Body)306、閘極305、源極電極307、閘極電極(未圖示)、汲極電極320和層間電介質321。源極電極307係電連接至源極區304和體區306，閘極電極從另一個方向(亦即，垂直於圖3所示的紙面方向)而被電連接至閘極305，汲極電極320係電連接至基板302，所述基板302用做為JFET 225的汲極和功率MOSFET 226的汲極。在圖3所述之實施例中，功率MOSFET 226還包括可選的靜電放電(ESD)焊墊309，所述ESD焊墊309透過ESD電極308而被電連接至保護環(guard ring)303。所述層間電介質321提供了形成各電極等的金屬層與金屬層下的裝置結構間的絕緣。
功率MOSFET 226的運行原理與常規垂直型溝槽閘極 MOSFET的運行原理相似。具體來說，當在功率MOSFET 226的閘極305施加大於其臨界電壓的正電壓時，功率MOSFET 226在體區306處，沿著閘極電介質而形成反型層，亦即，導電通道。相應地，電流通過N+源極區304、體區306的導電通道、漂移區(亦即，N-外延層301)而流入N+基板和汲極電極320，功率MOSFETE 226被導通。當減小施加在功率MOSFET 226的閘極電壓至小於其臨界電壓時，導電通道消失，功率MOSFET 226被斷開。
JFET 225與功率MOSFET 226共用N-外延層301和N+基板302。在圖3所示之實施例中，JFET 225為垂直型溝槽閘極接面型場效應電晶體。所述JFET 225包括N+源極區316、閘極317和P型體區315。與功率MOSFET 226相似，所述N+基板302用做為JFET 225的汲極。在圖3所示之實施例中，為了闡述清晰，JFET 225的源極電極和閘極電極未圖示出。在通常的情況下，JFET 225係處於導通狀態(亦即，長通)。若要使JFET 225斷開，則可在JFET 225的閘極317上施加電壓，使得P型體區315和N-外延層的PN接面被反偏，從而夾止源極區316的電流通路。JFET 225透過共用漂移區來檢測功率MOSFET 226的汲極電壓。
圖4~15示意性地示出了依據本發明之另一個實施例的積體電路220的製作流程圖。為了敍述簡明，對理解本發明沒有實質性作用的製作程序步驟被省略；同時，為了敍述方便，首先闡述功率MOSFET 226的製作，然後再闡 述JFET 225的製作。但是，本領域的技術人員應當意識到，這些電晶體的製作順序可以變化。此外，在同一個製作步驟中，多個JFET 225和多個功率MOSFET 226可能被同時製作。
如圖3所示，JFET 225和功率MOSFET 226被製作在相同的N+基板302和N-外延層301上。N-(亦即，N型輕度摻雜)外延層301係形成於N+(亦即，N型重度摻雜)基板302上。在一個實施例中，N+基板302包括矽基板。所述N-外延層301可透過氣相外延法而被形成。為了闡述清晰，N+基板302和汲極電極320並未在圖4~15中予以圖示出。
如圖4所示，所述製作流程包括：在N-外延層301上形成層間電介質334；在N-外延層301內形成溝槽331。所述層間電介質334包括任意合適的電介質材料，例如氧化矽、氮化矽等。所述溝槽331可透過反應離子蝕刻而被形成。
如圖5所示，所述製作流程包括：在溝槽331內形成閘極電介質336。閘極電介質336可包括一種或多種合適的電介質材料。在一個實施例中，閘極電介質包括在溝槽331之表面熱氧化所形成的氧化物。在閘極電介質336被形成之後，閘極材料335被沉積至每一個溝槽331。所述閘極材料335可包括導電材料，例如摻雜的多晶矽。
如圖6所示，所述製作流程包括：去除N-外延層301之表面多餘的閘極材料335，以使表面平坦化。在一個實 施例中，所述平坦化可透過蝕刻或者化學機械拋光來予以實現。在溝槽331內剩餘的閘極材料335用做為保護環303和閘極305。
如圖7所示，所述製作流程包括：在N-外延層301上形成ESD焊墊309。在一個實施例中，所述ESD焊墊309透過掩膜技術(例如，掩膜901)和蝕刻技術而被形成。在一個實施例中，所述ESD焊墊309為積體電路220的可選特徵。
如圖8所示，所述製作流程包括：在N-外延層301內形成P型體區306。在一個實施例中，所述P型體區306的形成包括：形成掩膜902；透過N-外延層301的曝露部分而向N-外延層301注入P型雜質(例如，硼)。
如圖9所示，所述製作流程包括：透過擴散技術或推進技術而將體區306的P型雜質推深進N-外延層301。
如圖10所示，所述製作流程包括：在N-外延層內形成N+源極區304。如圖10所示，掩膜903的位置決定了N+源極區304的位置。在圖10所示之實施例中，所述N+源極區304係形成於P型體區306內。同時，N型雜質透過掩膜903的缺口327而被注入進ESD焊墊309，以增強ESD焊墊309的導電能力，並形成ESD保護二極體堆疊PN接面的N側邊。
如圖11所示，所述製作流程包括：透過擴散技術或推進技術而將源極區304的N型雜質推深進體區306。
如圖12所示，所述製作流程包括：在N-外延層301 上形成層間電介質321；在層間電介質321內形成接觸通孔322~325，以使ESD焊墊309、保護環303、源極區304和體區306的導電部分曝露出。接觸通孔322~325可透過掩膜技術和蝕刻技術而被形成。
如圖13所示，所述製作流程包括：沉積金屬層(例如，鋁、銅、矽化物等)以形成ESD電極308、源極電極307以及汲極電極320(未圖示出)。在一個實施例中，在基板302的背面沉積金屬層，以形成汲極電極320；所述金屬層的沉積係在製作JFET 225之後。在一個實施例中，為了更高電壓位準的應用，所述製作流程進一步包括：在金屬層的頂部沉積鈍化層。
接下來，參考圖14和圖15來闡述JFET 225的製作流程。如圖14所示，所述製作流程包括：在N-外延層301內注入P型雜質以形成P型體區315。在一個實施例中，所述P型體區315的形成步驟和圖8所示P型體區306的形成步驟相同。源極區316透過向N-外延層301內的P型體區315間注入N型雜質而被形成。
如圖15所示，所述製作流程包括：在N-外延層301內形成溝槽。在所述溝槽內填充閘極電介質和閘極材料，並被平坦化。在一個實施例中，所述閘極材料包括摻雜的多晶矽。該摻雜的多晶矽的平坦化透過蝕刻或者化學機械拋光來予以實現。如圖3所示，所述閘極317透過N-外延層301內的P型體區315而被形成。可選地，適當改變製作步驟，JFET 225的溝槽和閘極電介質可與功率 MOSFET的閘極305同時被形成。
上述積體電路220可被應用於多種情況。總的來說，上述積體電路220尤其適合當控制器或者其他電路需要檢測功率MOSFET汲極電壓的情況。
圖16為依據本發明之又一實施例的採用積體電路220的電路的結構示意圖。在圖16所示實施例中，所述積體電路220用做為理想的二極體，應用在同步整流電路中。如圖16所示，所述同步整流電路包括反激式變換器，接收輸入VIN，產生輸出VOUT(VOUT+與VOUT-之差)；所述積體電路220被控制器490所控制。在一個實施例中，所述控制器490為二極體-模擬器控制器。二極體-模擬器控制器被用來控制積體電路220的一個實例為美國芯源系統有限公司生產的MP6901二極體-模擬器積體電路。可選地，所述積體電路220可用做為其他類型之二極體-模擬器控制器的外部開關。如圖16所示，積體電路220的檢測引腳(端子221)係連接至控制器490的端子454(VD引腳)，積體電路220的閘極引腳(端子222)係連接至控制器490的端子451(VG引腳)，積體電路220的源極引腳(端子223)係連接至控制器490的端子452(VSS引腳)和端子453(PGND引腳)。
控制器490調節積體電路220中功率MOSFET 226的正向導通壓降，並在所述正向導通壓降為負時斷開所述功率MOSFET 226。所述控制器490的端子454(VD引腳)係耦接至積體電路220的檢測引腳(端子221)來檢測功率 MOSFET 226的汲極電壓，進而檢測功率MOSFET 226的正向導通壓降。如前所示，積體電路220的JFET 225使控制器490無需直接連接至功率MOSFET 226的汲極高電壓。積體電路220的閘極引腳(端子222)係連接至控制器490的端子451(VG引腳)。積體電路220的源極引腳(端子223)係連接至控制器490的端子452(VSS引腳)和端子453(PGND引腳)，以形成開爾文檢測結構。
圖17具體示出了圖16所示的採用積體電路220的電路的結構示意圖。如圖17所示，所述控制器490包括：跨導放大器(gm)481、比較器482、MOSFET開關483和電阻器484。跨導放大器481的反相輸入端和比較器482的同相輸入端均透過積體電路220的檢測引腳(端子221)以檢測功率MOSFET 226的汲極電壓。如前所述，JFET 225使跨導放大器481和比較器482無需直接連接至功率MOSFET 226的汲極高電壓。偏置電壓461與偏置電壓491設定了功率MOSFET 226的正向導通壓降。在圖17所示之實施例中，偏置電壓461的電壓位準為70 mV，偏置電壓491的電壓位準為80 mV。當功率MOSFET 226的汲極電壓為負時，比較器482將MOSFET開關483導通，從而使功率MOSFET 226斷開。
前述依據本發明之多個實施例的積體電路和製作積體電路的方法，透過簡單的製作程序，確保低電壓位準的控制器可接收功率MOSFET的汲極高電壓。不同於現有技術，本發明之多個實施例的積體電路/製作積體電路的方 法，將JFET與功率MOSFET製作在相同基板上，共用漂移區，使得功率MOSFET的汲極電壓被方便地檢測出，並以低電壓位準的方式而被傳送給控制器。
雖然已參照幾個典型實施例來描述了本發明，但應當理解，所用的術語是說明和示例性、而非限制性的術語。由於本發明能夠用多種形式來予以具體實施而不脫離發明的精神或實質，所以應當理解，上述實施例不限於任何前述的細節，而應在隨附之申請專利範圍所限定的精神和範疇內被廣泛地解釋，因此落入申請專利範圍或其等效範疇內的全部變化和變型都應為隨附之申請專利範圍所涵蓋。
220‧‧‧積體電路
225‧‧‧接面型場效應電晶體(JFET)
226‧‧‧垂直功率MOSFET
301‧‧‧N-外延層
302‧‧‧N+矽基板
303‧‧‧保護環
304‧‧‧N+型源極區(Src)
305‧‧‧閘極
306‧‧‧P型體區
307‧‧‧源極電極
308‧‧‧靜電放電(ESD)電極
309‧‧‧靜電放電(ESD)焊墊
315‧‧‧P型體區
316‧‧‧N+源極區
317‧‧‧閘極
319‧‧‧分界線
320‧‧‧汲極電極
321‧‧‧層間電介質

Claims (10)

  1. 一種積體電路，包括：功率MOSFET，具有汲極、閘極和源極；JFET，具有汲極、閘極和源極，該JFET的汲極係耦接至該功率MOSFET的汲極，該JFET和該功率MOSFET共用該積體電路的基板上的漂移區；檢測引腳，係耦接至該JFET的源極；源極引腳，係耦接至該功率MOSFET的源極；閘極引腳，係耦接至該功率MOSFET的閘極；汲極引腳，係耦接至該功率MOSFET的汲極和該JFET的汲極。
  2. 如申請專利範圍第1項所述的積體電路，其中，該積體電路的封裝組件為四個端子的小外型積體電路封裝組件。
  3. 如申請專利範圍第1項所述的積體電路，其中，該積體電路只包括該JFET和該功率MOSFET。
  4. 如申請專利範圍第1項所述的積體電路，其中，該JFET和該功率MOSFET均為垂直型裝置，該積體電路的基板用做為該JFET和該功率MOSFET的汲極。
  5. 如申請專利範圍第1項所述的積體電路，其中，該JFET和該功率MOSFET的漂移區包括形成在積體電路的基板上的外延層。
  6. 一種製作積體電路的方法，包括：在基板上形成外延層； 在外延層內形成垂直型MOSFET的源極和閘極；在外延層內形成垂直型JFET的源極和閘極；其中，該垂直型JFET和該垂直型MOSFET共用漂移區，該漂移區包括該外延層；該基板用做為該垂直型MOSFET的汲極和該垂直型JFET的汲極。
  7. 如申請專利範圍第6項所述的方法，其中，該垂直型MOSFET的閘極和該垂直型JFET的閘極均為溝槽閘極。
  8. 一種積體電路，包括：功率MOSFET；JFET，與該功率MOSFET之共用基板上的漂移區；檢測引腳，經由該JFET而被耦接至該功率MOSFET的汲極，該檢測引腳為該積體電路的外部引腳，該檢測引腳允許外部電路檢測該功率MOSFET的汲極電壓；閘極引腳，係耦接至功率MOSFET的閘極，該閘極引腳為該積體電路的外部引腳。
  9. 如申請專利範圍第8項所述的積體電路，其中，該功率MOSFET和該JFET均為垂直型溝槽閘極電晶體。
  10. 如申請專利範圍第8項所述的積體電路，其中，該積體電路只包括該JFET和該功率MOSFET。
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US8723178B2 (en) 2014-05-13

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