CN103022035B - 一种集成电路及制作集成电路的方法 - Google Patents

一种集成电路及制作集成电路的方法 Download PDF

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CN103022035B
CN103022035B CN201310016877.5A CN201310016877A CN103022035B CN 103022035 B CN103022035 B CN 103022035B CN 201310016877 A CN201310016877 A CN 201310016877A CN 103022035 B CN103022035 B CN 103022035B
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power mosfet
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CN103022035A (zh
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李铁生
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本申请公开了一种集成电路及制作集成电路的方法。所述集成电路包括：功率MOSFET，具有漏极、栅极和源极；JFET，具有漏极、栅极和源极，所述JFET的漏极耦接至所述功率MOSFET的漏极，所述JFET和功率MOSFET共用所述集成电路的衬底上的漂移区；检测引脚，耦接至所述JFET的源极；源极引脚，耦接至所述功率MOSFET的源极；栅极引脚，耦接至所述功率MOSFET的栅极；漏极引脚，耦接至所述功率MOSFET的漏极和所述JFET的漏极。本申请通过简单的制作工艺保证了低电压水平的控制器可接收功率MOSFET的漏极高压。

Description

一种集成电路及制作集成电路的方法
技术领域
本发明涉及一种电子电路，更具体地说，本发明涉及一种集成电路及制作集成电路的方法。
背景技术
场效应晶体管(FET)被广泛应用于各种电子电路中。在某些应用场合，需要检测场效应晶体管的漏极电压来控制场效应晶体管的运行。例如，控制器根据该漏极电压控制场效应晶体管的导通或者断开。但在某些应用场合，场效应晶体管的漏极电压可能为高压。若将该漏极高压直接输送至控制器，极可能损坏控制器。
发明内容
因此本发明的目的在于解决现有技术的上述技术问题，提出一种改进的集成电路及制作集成电路的方法。
根据本发明的实施例，提出了一种集成电路，包括：功率MOSFET，具有漏极、栅极和源极；JFET，具有漏极、栅极和源极，所述JFET的漏极耦接至所述功率MOSFET的漏极，所述JFET和功率MOSFET共用所述集成电路的衬底上的漂移区；检测引脚，耦接至所述JFET的源极；源极引脚，耦接至所述功率MOSFET的源极；栅极引脚，耦接至所述功率MOSFET的栅极；漏极引脚，耦接至所述功率MOSFET的漏极和所述JFET的漏极。
根据本发明的实施例，还提出了一种制作集成电路的方法，包括：在衬底上形成外延层；在外延层内形成一垂直型MOSFET的源极和栅极；在外延层内形成一垂直型JFET的源极和栅极；其中所述垂直型JFET和垂直型MOSFET共用漂移区，所述漂移区包括所述外延层；所述衬底做为所述垂直型MOSFET的漏极和垂直型JFET的漏极。
根据本发明的实施例，还提出了一种集成电路，包括：功率MOSFET；JFET，与所述功率MOSFET共用衬底上的漂移区；检测引脚，经由所述JFET耦接至所述功率MOSFET的漏极，所述检测引脚为所述集成电路的外部引脚，该检测引脚允许外部电路检测所述功率MOSFET的漏极电压；栅极引脚，耦接至功率MOSFET的栅极，所述栅极引脚为所述集成电路的外部引脚。
根据本发明各方面的上述集成电路和制作集成电路的方法，通过简单的制作工艺保证了低电压水平的控制器接收功率MOSFET的漏极高压。
附图说明
图1示意性地示出了检测一金属氧化物半导体场效应晶体管112漏极电压的电路；
图2为根据本发明一实施例的集成电路220的电路结构示意图；
图3示意性地示出了根据本发明一个实施例的集成电路220的剖面图；
图4～15示意性地示出了根据本发明另一个实施例的集成电路220的制作流程图；
图16为根据本发明又一实施例的采用集成电路220的电路的结构示意图；
图17具体示出了图16所示的采用集成电路220的电路的结构示意图。
具体实施方式
下面将详细描述本发明的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本发明。在以下描述中，为了提供对本发明的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本发明。在其他实例中，为了避免混淆本发明，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本发明至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。应当理解，当称元件“耦接到”或“连接到”另一元件时，它可以是直接耦接或耦接到另一元件或者可以存在中间元件。相反，当称元件“直接耦接到”或“直接连接到”另一元件时，不存在中间元件。相同的附图标记指示相同的元件。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所有组合。
图1示意性地示出了检测一金属氧化物半导体场效应晶体管(MOSFET)112漏极电压的电路。在图1所示实施例中，MOSFET 112为功率金属氧化物半导体场效应晶体管，其漏极电压可能达到30～100V。但控制器101只能处理3～6V的电压。此时，控制器101通过一结型场效应晶体管(JFET)102来检测MOSFET 112的漏极电压，使得控制器101无需直接接收高压。
和典型功率器件一样，MOSFET 112为独立封装的分立型器件110。JFET 102和控制器101被集成在相同裸片上，并被封装在一起作为控制器件100。但将JFET 102和控制器101集成在相同裸片上至少有2个缺点。第一，由于在某些应用场合，MOSFET 112的漏极电压为-0.8至-1.0V，通过JFET 102将控制器101连接至外部MOSFET112可能引起衬底注入；第二，制作控制器101的工艺可以处理低的门限电压，但该工艺不能处理高于30V的电压，从而限制了其在高压场合的应用。
图2为根据本发明一实施例的集成电路220的电路结构示意图。在图2所示实施例中，集成电路220只包括形成在相同裸片并封装在一起的垂直JIFET 225和垂直功率MOSFET 226。跨接在功率MOSFET226两端的二极管为功率MOSFET 226的体二极管，而非独立的分立器件。在一个实施例中，集成电路220的封装(即JFET 225和功率MOSFET 226的封装)为四端子的小外型集成电路(small outlineintegrated circuit，SOIC)封装，如集成电路220包括端子221(检测引脚)、端子222(栅极引脚)、端子223(源极引脚)以及端子224(漏极引脚)。其中端子221～224为外部引脚，通过该四端子允许外部电路连接至集成电路220。端子221(即检测引脚)通过长通的JFET 225连接至功率MOSFET 226。通过JFET 225，控制器210避免直接连接至可能为高压的功率MOSFET 226的漏极。在图2所示实施例中，检测引脚(端子221)连接至JFET 225的源极；栅极引脚(端子222)、源极引脚(端子223)和漏极引脚(端子224)分别连接至功率MOSFET226的栅极、源极和漏极；JFET 225的漏极连接至功率MOSFET 226的漏极。
集成电路220可被应用于检测漏极电压的场合。如集成电路220可被用做理想二极管(导通压降小于常规二极管的二极管)。当然，本领域的技术人员应当意识到，集成电路220也可应用于其他多种场合。
在一个实施例中，为便于检测功率MOSFET 226的漏极电压，JFET 225和功率MOSFET 226被制作在相同的衬底上以共用漂移区。漂移区包括形成在衬底上的外延层，所述衬底作为JFET 225的漏极和功率MOSFET 226的漏极。由于JFET 225和MOSFET 226共用漂移区，两者具有相似的电学特性，因此，JFET 225和MOSFET 226可用允许高压的相同分立制作工艺制作。
在图2所示实施例中，集成电路220为控制器210的外部器件。因此，控制210可在另外的衬底上制作，并且无需受限于JFET 225和功率MOSFET 226的电学特性要求。在一个实施例中，控制器210可为二极管-模拟器(diode-emulator)控制器、太阳电池板控制器、电压调整器的同步开关的控制器，等等。在一个实施例中，控制器210包括端子201、202和203，其中端子201连接至集成电路220的检测引脚(端子221)，以使控制器210检测功率MOSFET 226的漏极电压；端子202和端子203分别连接至集成电路220的栅极引脚(端子222)和源极引脚(端子223)，以使控制器210控制功率MOSFET 226。
图3示意性地示出了根据本发明一个实施例的集成电路220的剖面图。集成电路220将JFET 225和功率MOSFET 226一起集成在相同的N+硅衬底302上。外延层301为N型(如磷)轻掺杂，衬底302为N型重掺杂。在图3所示实施例中，虚线319示意性地表征JFET 225和功率MOSFET 226的分界线。
在图3所示实施例中，功率MOSFET 226为垂直型沟槽栅金属氧化物半导体场效应晶体管。所述功率MOSFET 226包括N+型源极区(Src)304、P型体区(Body)306、栅极305、源极电极307、栅极电极(未图示)、漏极电极320和层间电介质321。源极电极307电连接至源极区304和体区306，栅极电极从另一个方向(即垂直于图3所示的纸面方向)电连接至栅极305，漏极电极320电连接至衬底302，所述衬底302作为JFET 225的漏极和功率MOSFET 226的漏极。在图3所述实施例中，功率MOSFET 226还包括可选的静电释放(ESD)焊盘309，所述ESD焊盘309通过ESD电极308电连接至保护环(guardring)303。所述层间电介质321提供了形成各电极等的金属层与金属层下的器件结构间的绝缘。
功率MOSFET 226的运行原理与常规垂直型沟槽栅MOSFET的运行原理相似。具体来说，当在功率MOSFET 226的栅极305施加大于其门限电压的正电压时，功率MOSFET 226在体区306处，沿着栅极电介质形成反型层，即导电沟道。相应地，电流通过N+源极区304、体区306的导电沟道、漂移区(即N-外延层301)流入N+衬底和漏极电极320，功率MOSFETE 226被导通。当减小施加在功率MOSFET226的栅极电压至小于其门限电压时，导电沟道消失，功率MOSFET226被断开。
JFET 225与功率MOSFET 226共用N-外延层301和N+衬底302。在图3所示实施例中，JFET 225为垂直型沟槽栅结型场效应晶体管。所述JFET 225包括N+源极区316、栅极317和P型体区315。与功率MOSFET 226相似，所述N+衬底302作为JFET 225的漏极。在图3所示实施例中，为阐述清晰，JFET 225的源极电极和栅极电极未图示。通常情况下，JFET 225处于导通状态(即长通)。若要断开JFET 225，则可在JFET 225的栅极317上施加电压，使得P型体区315和N-外延层的PN结被反偏，从而夹断源极区316的电流通路。JFET 225通过共用漂移区检测功率MOSFET 226的漏极电压。
图4～15示意性地示出了根据本发明另一个实施例的集成电路220的制作流程图。为了叙述简明，对理解本发明没有实质性作用的制作工艺步骤被省略；同时，为了叙述方便，首先阐述功率MOSFET 226的制作，然后再阐述JFET 225的制作。但是，本领域的技术人员应当意识到，这些晶体管的制作顺序可以变化。此外，在同一个制作步骤中，多个JFET 225和多个功率MOSFET 226可能被同时制作。
如图3所示，JFET 225和功率MOSFET 226被制作在相同的N+衬底302和N-外延层301上。N-(即N型轻掺杂)外延层301形成于N+(即N型重掺杂)衬底302上。在一个实施例中，N+衬底302包括硅衬底。所述N-外延层301可通过气相外延法形成。为阐述清晰，N+衬底302和漏极电极320未在图4～15中图示。
如图4所示，所述制作流程包括：在N-外延层301上形成层间电介质334；在N-外延层301内形成沟槽331。所述层间电介质334包括任意合适的电介质材料，如氧化硅、氮化硅等。所述沟槽331可通过反应离子刻蚀形成。
如图5所示，所述制作流程包括：在沟槽331内形成栅极电介质336。栅极电介质336可包括一种或多种合适的电介质材料。在一个实施例中，栅极电介质包括在沟槽331表面热氧化形成的氧化物。在栅极电介质336形成之后，栅极材料335被淀积至每个沟槽331。所述栅极材料335可包括导电材料，如掺杂的多晶硅。
如图6所示，所述制作流程包括：去除N-外延层301表面多余的栅极材料335，使表面平坦化。在一个实施例中，所述平坦化可通过刻蚀或者化学机械抛光实现。在沟槽331内剩余的栅极材料335作为保护环303和栅极305。
如图7所示，所述制作流程包括：在N-外延层301上形成ESD焊盘309。在一个实施例中，所述ESD焊盘309通过掩膜技术(如掩膜901)和刻蚀技术形成。在一个实施例中，所述ESD焊盘309为集成电路220的可选特征。
如图8所示，所述制作流程包括：在N-外延层301内形成P型体区306。在一个实施例中，所述P型体区306的形成包括：形成掩膜902；通过N-外延层301的曝露部分向N-外延层301注入P型杂质(如硼)。
如图9所示，所述制作流程包括：通过扩散技术或推进技术将体区306的P型杂质推深进N-外延层301。
如图10所示，所述制作流程包括：在N-外延层内形成N+源极区304。如图10所示，掩膜903的位置决定了N+源极区304的位置。在图10所示实施例中，所述N+源极区304形成于P型体区306内。同时，N型杂质通过掩膜903的缺口327被注入进ESD焊盘309，以增强ESD焊盘309的导电能力，并形成ESD保护二极管堆栈PN结的N侧边。
如图11所示，所述制作流程包括：通过扩散技术或推进技术将源极区304的N型杂质推深进体区306。
如图12所示，所述制作流程包括：在N-外延层301上形成层间电介质321；在层间电介质321内形成接触通孔322～325，以曝露ESD焊盘309、保护环303、源极区304和体区306的导电部分。接触通孔322～325可通过掩膜技术和刻蚀技术形成。
如图13所示，所述制作流程包括：淀积金属层(如铝、铜、硅化物等)以形成ESD电极308、源极电极307以及漏极电极320(未图示)。在一个实施例中，在衬底302的背面淀积金属层，以形成漏极电极320；所述金属层的淀积在制作JFET 225之后。在一个实施例中，为了更高电压水平的应用，所述制作流程进一步包括：在金属层的顶部淀积钝化层。
接下来，参考图14和图15阐述JFET 225的制作流程。如图14所示，所述制作流程包括：在N-外延层301内注入P型杂质形成P型体区315。在一个实施例中，所述P型体区315的形成步骤和图8所示P型体区306的形成步骤相同。源极区316通过向N-外延层301内的P型体区315间注入N型杂质形成。
如图15所示，所述制作流程包括：在N-外延层301内形成沟槽。所述沟槽内填充栅极电介质和栅极材料，并被平坦化。在一个实施例中，所述栅极材料包括掺杂的多晶硅。该掺杂的多晶硅的平坦化通过刻蚀或者化学机械抛光实现。如图3所示，所述栅极317通过N-外延层301内的P型体区315形成。可选地，适当改变制作步骤，JFET 225的沟槽和栅极电介质可与功率MOSFET的栅极305同时形成。
上述集成电路220可被应用于多种场合。总的来说，上述集成电路220尤其适合当控制器或者其他电路需要检测一功率MOSFET漏极电压的场合。
图16为根据本发明又一实施例的采用集成电路220的电路的结构示意图。在图16所示实施例中，所述集成电路220作为理想的二极管，应用在同步整流电路中。如图16所示，所述同步整流电路包括反激式变换器，接收输入VIN，产生输出VOUT(VOUT+与VOUT-之差)；所述集成电路220被控制器490控制。在一个实施例中，所述控制器490为二极管-模拟器控制器。二极管-模拟器控制器被用来控制集成电路220的一个实例为美国芯源系统有限公司生产的MP6901二极管-模拟器集成电路。可选地，所述集成电路220可作为其他类型二极管-模拟器控制器的外部开关。如图16所示，集成电路220的检测引脚(端子221)连接至控制器490的端子454(VD引脚)，集成电路220的栅极引脚(端子222)连接至控制器490的端子451(VG引脚)，集成电路220的源极引脚(端子223)连接至控制器490的端子452(VSS引脚)和端子453(PGND引脚)。
控制器490调节集成电路220中功率MOSFET 226的正向导通压降，并在所述正向导通压降为负时断开所述功率MOSFET 226。所述控制器490的端子454(VD引脚)耦接至集成电路220的检测引脚(端子221)来检测功率MOSFET 226的漏极电压，进而检测功率MOSFET226的正向导通压降。如前所示，集成电路220的JFET 225使控制器490无需直接连接至功率MOSFET 226的漏极高压。集成电路220的栅极引脚(端子222)连接至控制器490的端子451(VG引脚)。集成电路220的源极引脚(端子223)连接至控制器490的端子452(VSS引脚)和端子453(PGND引脚)，以形成开尔文检测结构。
图17具体示出了图16所示的采用集成电路220的电路的结构示意图。如图17所示，所述控制器490包括：跨导放大器(gm)481、比较器482、MOSFET开关483和电阻484。跨导放大器481的反相输入端和比较器482的同相输入端均通过集成电路220的检测引脚(端子221)检测功率MOSFET 226的漏极电压。如前所述，JFET 225使跨导放大器481和比较器482无需直接连接至功率MOSFET 226的漏极高压。偏置电压461与偏置电压491设定了功率MOSFET 226的正向导通压降。在图17所示实施例中，偏置电压461的电压水平为70mV，偏置电压491的电压水平为80mV。当功率MOSFET 226的漏极电压为负时，比较器482将MOSFET开关483导通，从而断开功率MOSFET 226。
前述根据本发明多个实施例的集成电路和制作集成电路的方法，通过简单的制作工艺，保证了低电压水平的控制器可接收功率MOSFET的漏极高压。不同于现有技术，本发明多个实施例的集成电路/制作集成电路的方法，将JFET与功率MOSFET制作在相同衬底上，共用漂移区，使得功率MOSFET的漏极电压被方便地检测，并以低电压水平的方式传送给控制器。
虽然已参照几个典型实施例描述了本发明，但应当理解，所用的术语是说明和示例性、而非限制性的术语。由于本发明能够以多种形式具体实施而不脱离发明的精神或实质，所以应当理解，上述实施例不限于任何前述的细节，而应在随附权利要求所限定的精神和范围内广泛地解释，因此落入权利要求或其等效范围内的全部变化和改型都应为随附权利要求所涵盖。

Claims (8)

1.一种集成电路，包括：
功率MOSFET，具有漏极、栅极和源极；
JFET，具有漏极、栅极和源极，所述JFET的漏极耦接至所述功率MOSFET的漏极，所述JFET和功率MOSFET共用所述集成电路的衬底上的漂移区；
检测引脚，耦接至所述JFET的源极；
源极引脚，耦接至所述功率MOSFET的源极；
栅极引脚，耦接至所述功率MOSFET的栅极；
漏极引脚，耦接至所述功率MOSFET的漏极和所述JFET的漏极。
2.如权利要求1所述的集成电路，其中所述集成电路的封装为四端子的小外型集成电路封装。
3.如权利要求1所述的集成电路，其中所述集成电路只包括所述JFET和所述功率MOSFET。
4.如权利要求1所述的集成电路，其中所述JFET和所述功率MOSFET均为垂直型器件，所述集成电路的衬底作为所述JFET和所述功率MOSFET的漏极。
5.如权利要求1所述的集成电路，其中所述JFET和所述功率MOSFET的漂移区包括形成在集成电路的衬底上的外延层。
6.一种集成电路，包括：
功率MOSFET；
JFET，与所述功率MOSFET共用衬底上的漂移区；
检测引脚，经由所述JFET耦接至所述功率MOSFET的漏极，所述检测引脚为所述集成电路的外部引脚，该检测引脚允许外部电路检测所述功率MOSFET的漏极电压；
栅极引脚，耦接至功率MOSFET的栅极，所述栅极引脚为所述集成电路的外部引脚。
7.如权利要求6所述的集成电路，其中所述功率MOSFET和所述JFET均为垂直型沟槽栅晶体管。
8.如权利要求6所述的集成电路，其中所述集成电路只包括所述JFET和所述功率MOSFET。
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CN103022035A (zh) 2013-04-03
US20130187160A1 (en) 2013-07-25
TW201342582A (zh) 2013-10-16
US8723178B2 (en) 2014-05-13

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