TWI516644B - Electroplating method - Google Patents

Electroplating method Download PDF

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TWI516644B
TWI516644B TW100148564A TW100148564A TWI516644B TW I516644 B TWI516644 B TW I516644B TW 100148564 A TW100148564 A TW 100148564A TW 100148564 A TW100148564 A TW 100148564A TW I516644 B TWI516644 B TW I516644B
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substrate
plating
current
pulse
anode
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TW201231738A (en
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荒木裕二
齋藤信利
藤方淳平
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荏原製作所股份有限公司
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/06Suspending or supporting devices for articles to be coated
    • C25D17/08Supporting racks, i.e. not for suspending
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02Anodisation
    • C25D11/024Anodisation under pulsed or modulated current or potential
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/004Sealing devices
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/005Contacting devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
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  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Automation & Control Theory (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

電鍍方法Plating method

本發明係有關於一種電鍍方法用以同時鍍覆基板的正、反面,該基板有垂直穿過其內部的穿孔(through-hole),以將金屬(例如,銅或其類似物)的鍍覆膜填入該穿孔。The present invention relates to an electroplating method for simultaneously plating the front and back sides of a substrate having a through-hole vertically passing through the inside thereof to plate a metal (for example, copper or the like). The membrane is filled with the perforations.

形成垂直穿過基板之複數個金屬通孔(through-via)的技術習知為電性連接由數個基板(例如,半導體基板)組成之多層堆疊中之諸層的方法。習慣上是藉由同時鍍覆有穿孔垂直穿過其內部之基板的正、反面來製作基板的垂直通孔,藉此將金屬的鍍覆膜填入穿孔。A technique of forming a plurality of metal through-vias vertically through a substrate is conventionally a method of electrically connecting layers in a multilayer stack composed of a plurality of substrates (e.g., semiconductor substrates). It is customary to form a vertical through hole of a substrate by simultaneously plating the front and back surfaces of the substrate through which the perforations are vertically passed, thereby filling the metal plating film into the perforations.

已知有一種用於製作通孔的電鍍設備(參考日本專利第4138542號)。此電鍍設備包括基板固持件用以固持基板同時暴露正、反面上的某些區域以及密封在該等某些區域四周的周圍區域,以及將一對陽極配置成分別與被基板固持件固持之基板的正、反面面對面。被基板固持件固持的基板與該等陽極浸入鍍覆液,然後在該基板、該等陽極之間施加電壓以同時鍍覆有垂直穿孔定義於其中之基板的正、反面,這可嵌入金屬(例如,銅)於穿孔中。There is known an electroplating apparatus for making a through hole (refer to Japanese Patent No. 4138542). The electroplating apparatus includes a substrate holder for holding the substrate while exposing certain areas on the front and back sides, and surrounding areas surrounding the certain areas, and a pair of anodes respectively configured to be held by the substrate holding member Face to face, face to face. The substrate held by the substrate holding member and the anode are immersed in the plating solution, and then a voltage is applied between the substrate and the anode to simultaneously plate the front and back surfaces of the substrate defined by the vertical perforations, which can be embedded in the metal ( For example, copper) is in the perforation.

第1A圖至第1D圖所示的製程步驟序列係圖解說明用以將鍍覆膜填入定義於基板之穿孔以於其中形成通孔的方法(參考日本專利第4248353號)。The sequence of process steps shown in Figs. 1A to 1D illustrates a method for filling a plating film into a perforation defined in a substrate to form a via hole therein (refer to Japanese Patent No. 4248353).

如第1A圖所示,預備基板W,其係包含有垂直穿孔100a定義於其中的基部100,以及由鈦或其類似物製成的阻障層(barrier layer)102與用作饋電層(electric feed layer)及覆蓋基部100之所有表面(包括穿孔100a的內表面)的種子層104。同時鍍覆基板W的正、反面以沉積金屬(例如,銅或其類似物)的鍍覆膜106於基板W的正、反面上及穿孔100a中,如第1B圖所示。穿孔100a中的鍍覆膜106沿著深度方向在中央處有最大厚度。然後,如第1C圖所示,成長鍍覆膜106直到已由穿孔100a壁面長成之鍍覆膜106層的尖端在穿孔100a沿著深度方向的中央處相互連結。穿孔100a沿著深度方向的中央因而被鍍覆膜106阻塞,而在封閉區的上下方形成凹處108。進一步繼續該鍍覆製程以在凹處108中成長鍍覆膜106直到鍍覆膜106填滿凹處108,如第1D圖所示。以此方式,在基板W中產生由鍍覆膜106構成的通孔。As shown in FIG. 1A, a preliminary substrate W includes a base 100 in which a vertical through hole 100a is defined, and a barrier layer 102 made of titanium or the like and used as a feed layer ( An electric feed layer) and a seed layer 104 covering all surfaces of the base 100, including the inner surface of the perforations 100a. At the same time, the plating film 106 of the metal (for example, copper or the like) is deposited on the front and back sides of the substrate W on the front and back surfaces of the substrate W and the perforations 100a as shown in FIG. 1B. The plating film 106 in the perforation 100a has a maximum thickness at the center in the depth direction. Then, as shown in FIG. 1C, the growth plating film 106 is connected to each other at the center of the perforation 100a in the depth direction up to the tip end of the plating film 106 layer which has been formed by the wall surface of the perforation 100a. The center of the perforation 100a along the depth direction is thus blocked by the plating film 106, and a recess 108 is formed above and below the closed area. The plating process is further continued to grow the plating film 106 in the recess 108 until the plating film 106 fills the recess 108 as shown in FIG. 1D. In this way, a through hole composed of the plating film 106 is generated in the substrate W.

已有人提出一種用金屬鍍覆膜填滿定義於基板之穿孔的電鍍方法(參考日本專利早期公開案第2008-513985號)。根據此電鍍方法,供給正向脈衝電流以在作為陰極的基板、陽極之間流動,以及也供給流動方向與正向脈衝電流相反的反向脈衝電流以在該基板、該陽極之間流動,藉此完全或實質完全填滿穿孔的中央。A plating method in which a perforation defined on a substrate is filled with a metal plating film has been proposed (refer to Japanese Patent Laid-Open Publication No. 2008-513985). According to this plating method, a forward pulse current is supplied to flow between a substrate as a cathode, an anode, and a reverse pulse current having a flow direction opposite to a forward pulse current is also supplied to flow between the substrate and the anode, This completely or substantially completely fills the center of the perforation.

已有人也提出一種用以在用銅鍍覆印刷線路板或其類似物時防止晶鬚(whisker)產生的方法(參考參考日本專利早期公開案第2010-95775號)。根據此方法,用以施加直流電壓於陰極、陽極之間的直流電源有可逆極性。在交替的正常直流電壓、反向直流電壓下電鍍印刷線路板,亦即,交替地使用印刷線路板用作陰極的正常電解周期,以及印刷線路板用作陽極的逆向電解周期。A method for preventing whisker generation when plating a printed wiring board or the like with copper has also been proposed (refer to Japanese Patent Laid-Open Publication No. 2010-95775). According to this method, the DC power source for applying a DC voltage between the cathode and the anode has a reversible polarity. The printed wiring board is electroplated under alternating normal DC voltages, reverse DC voltages, that is, the normal electrolysis period in which the printed wiring board is used as a cathode alternately, and the reverse electrolysis period in which the printed wiring board is used as an anode.

為了在基板中形成無例如,空洞(voids)或其類似物之缺陷鍍覆膜形式的通孔,如第1A圖至第1D圖所示,理想的方式是在穿孔沿著深度方向的中央處優先成長鍍覆膜直到穿孔100a的中央被鍍覆膜106阻塞,然後再繼續該鍍覆製程。不過,實務上大體難以企圖滿足理想的要求同時有效率地將鍍覆膜填入穿孔以縮短完成鍍覆製程所需時間。換言之,習知電鍍製程未能實現在鍍覆期間用較高的平均鍍覆電流理想地將鍍覆膜填入穿孔以及有效率地將鍍覆膜填入穿孔兩者。In order to form a through hole in the form of a defect-free plating film of, for example, voids or the like in the substrate, as shown in FIGS. 1A to 1D, it is desirable that the perforation is at the center in the depth direction. The plating film is preferentially grown until the center of the perforation 100a is blocked by the plating film 106, and then the plating process is continued. However, in practice, it is generally difficult to attempt to meet the desired requirements while efficiently filling the plating film into the perforations to shorten the time required to complete the plating process. In other words, the conventional electroplating process fails to achieve a high average plating current during plating, ideally filling the perforated film with the plating film and efficiently filling the plating film into both of the perforations.

鑑於上述情形,已做出本發明。因此,本發明的目標是要提供一種電鍍方法用以在鍍覆期間用較高的平均鍍覆電流有效率地將鍍覆膜填入穿孔以縮短完成鍍覆製程所需時間以及也理想地將鍍覆膜填入穿孔。The present invention has been made in view of the above circumstances. Accordingly, it is an object of the present invention to provide an electroplating method for efficiently filling a plating film into a perforation with a higher average plating current during plating to shorten the time required to complete the plating process and also desirably The plated film is filled with perforations.

為了達成上述目標,本發明提供一種電鍍方法,其係包含下列步驟:將有一穿孔定義於其中的基板浸入在鍍覆槽中的鍍覆液;將在該鍍覆槽之該鍍覆液中的一對陽極配置成分別與在該鍍覆液中之該基板的正、反面面對面;對於該基板的正、反面,藉由各自供給脈衝電流於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間,進行各自持續一預定時段的複數個鍍覆製程;以及在該等鍍覆製程的相鄰製程之間對於該基板的正、反面,藉由各自供給與該等鍍覆製程之脈衝電流相反的電流於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間,進行一逆向電解製程。In order to achieve the above object, the present invention provides a plating method comprising the steps of: dipping a substrate having a perforation defined therein into a plating solution in a plating bath; and being in the plating solution of the plating tank. a pair of anodes are disposed to face the front and back sides of the substrate in the plating solution, respectively; for the front and back sides of the substrate, the pulse current is supplied to the front surface of the substrate and the anodes Between one of the front sides of the substrate, and between the opposite side of the substrate and the other of the opposite sides of the substrate facing the substrate, performing a plurality of plating processes each continuing for a predetermined period of time; Between the adjacent processes of the plating process, the positive and negative faces of the substrate are respectively supplied to the substrate in the front surface of the substrate and the anodes by supplying currents opposite to the pulse currents of the plating processes. A reverse electrolysis process is performed between one of the front faces and between the opposite side of the substrate and the other of the opposite sides of the anode facing the substrate.

由於對於該基板的正、反面,藉由各自供給脈衝電流於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間,進行各自持續一預定時段的複數個鍍覆製程,因此有可能用遞增的平均電流值有效率地將鍍覆膜填入穿孔,從而縮短完成鍍覆製程所需時間。執行於該等鍍覆製程之間的逆向電解製程可有效地溶解沉積於穿孔角落的鍍覆膜。因此,藉由在穿孔沿著深度方向的中央處優先成長鍍覆膜有可能理想地將鍍覆膜填入穿孔。For the positive and negative sides of the substrate, by supplying a pulse current between the front surface of the substrate and one of the front faces of the substrate facing the substrate, and the opposite side of the substrate and the anodes Between the other of the opposite sides of the substrate, a plurality of plating processes each continuing for a predetermined period of time are performed, so that it is possible to efficiently fill the plating film with the perforation with an increasing average current value, thereby shortening the finish plating. The time required to overwrite the process. The reverse electrolysis process performed between the plating processes effectively dissolves the plating film deposited on the corners of the perforations. Therefore, it is possible to ideally fill the perforation with the plating film by preferentially growing the plating film at the center of the perforation in the depth direction.

在本發明的一較佳態樣中,該等脈衝電流中之每一包含以正向流動電流與反向流動電流之交替重覆呈現的PR脈衝電流(PR pulsed current)。In a preferred aspect of the invention, each of the pulse currents comprises a PR pulsed current that is represented by an alternating repetition of a forward flow current and a reverse flow current.

在使用PR脈衝電流的鍍覆製程之間重覆執行該逆向電解製程,藉此防止異常沉積於鍍覆膜微觀表面上所產生的精細不規則性從而防止鍍覆膜形成因精細不規則性而引起的精細空洞。The reverse electrolysis process is repeatedly performed between plating processes using PR pulse currents, thereby preventing fine irregularities generated by abnormal deposition on the microscopic surface of the plating film to prevent the formation of the plating film due to fine irregularities. The fine holes caused.

在本發明的一較佳態樣中,該等脈衝電流中之每一包含以供給及不供給正向流動鍍覆電流之交替重覆呈現的開/關脈衝電流。In a preferred aspect of the invention, each of the pulsed currents comprises an on/off pulse current presented in alternating repetitions of supply current and no supply of forward flow plating current.

由於開/關脈衝電流在鍍覆製程中提供不供給鍍覆電流的非鍍覆時段(non-plating period),穿孔內鍍覆液的金屬離子濃度會在非鍍覆時段恢復藉此鍍覆膜形成缺陷,例如,空洞或其類似物。Since the on/off pulse current provides a non-plating period in the plating process that does not supply the plating current, the metal ion concentration of the plating solution in the perforation is restored during the non-plating period by the plating film. Defects are formed, for example, voids or the like.

在本發明的一較佳態樣中,該等脈衝電流中之每一包含以有不同電流值之兩個脈衝電流之一組合呈現的組合脈衝電流。In a preferred aspect of the invention, each of the pulsed currents comprises a combined pulse current presented in combination of one of two pulsed currents having different current values.

由於在有該組合脈衝電流的該鍍覆製程中,該鍍覆膜會繼續成長,因此該鍍覆製程可防止該鍍覆膜溶入該鍍覆液。Since the plating film continues to grow in the plating process having the combined pulse current, the plating process prevents the plating film from being dissolved in the plating solution.

在本發明的一較佳態樣中,一起執行該等鍍覆製程及該逆向電解製程以隨著基板的鍍覆進展來逐漸增加平均電流密度。In a preferred aspect of the invention, the plating process and the reverse electrolysis process are performed together to gradually increase the average current density as the plating of the substrate progresses.

當鍍覆製程使穿孔逐漸填滿鍍覆膜時,穿孔的實質高深寬比也跟著改變。當穿孔的實質高深寬比改變時,藉由遞增鍍覆製程的平均電流密度有可能以與穿孔的實質高深寬比變化匹配的方式來有效率地將鍍覆膜填入穿孔。結果,可進一步縮短鍍覆基板所需要的時間。When the plating process causes the perforations to gradually fill the plating film, the substantial aspect ratio of the perforations also changes. When the substantial high aspect ratio of the perforations is changed, it is possible to efficiently fill the perforations with the plating film by increasing the average current density of the plating process in a manner that matches the substantially high aspect ratio of the perforations. As a result, the time required to plate the substrate can be further shortened.

在本發明的一較佳態樣中,在正向供給脈衝電流的正常電解周期之前及之後多次執行該逆向電解製程。In a preferred aspect of the invention, the reverse electrolysis process is performed a plurality of times before and after the normal electrolysis cycle of the forward supply pulse current.

例如,用在-30至-40 ASD之間的負值陰極電流密度、以0.1至10毫秒之間的脈衝間距,來執行該逆向電解製程。取決於定義於該基板之穿孔的高深寬比,根據脈衝間距小於1.0毫秒的逆向電解製程,優先在穿孔沿著深度方向的中央處理想地填入鍍覆膜也許不可能。不過,如果在正向供給脈衝電流的正常電解周期之前及之後,以小於1.0毫秒的脈衝間距重覆多次執行該逆向電解製程,則有可能理想地將鍍覆膜填入該穿孔。For example, the reverse electrolysis process is performed with a negative cathode current density between -30 and -40 ASD with a pulse spacing of between 0.1 and 10 milliseconds. Depending on the high aspect ratio of the perforations defined on the substrate, it may not be possible to preferentially fill the plating film in the center of the perforation along the depth direction according to the reverse electrolysis process with a pulse pitch of less than 1.0 msec. However, if the reverse electrolysis process is repeated a plurality of times at a pulse pitch of less than 1.0 msec before and after the normal electrolysis cycle of supplying the pulse current in the forward direction, it is possible to desirably fill the perforation with the plating film.

根據本發明,如上述,對於該基板的正、反面,藉由各自供給脈衝電流於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間,進行各自持續一預定時段的複數個鍍覆製程。因此,有可能以遞增的平均電流值有效率地將鍍覆膜填入穿孔藉此縮短完成鍍覆製程所需時間。執行於該等鍍覆製程之間的逆向電解製程可有效地溶解沉積於穿孔角落的鍍覆膜。因此,藉由在穿孔沿著深度方向的中央處優先成長鍍覆膜有可能理想地將鍍覆膜填入穿孔。According to the present invention, as described above, the positive and negative sides of the substrate are respectively supplied with a pulse current between the front surface of the substrate and one of the front surfaces of the anode facing the substrate, and the substrate Between the reverse side and the other of the anodes facing the opposite side of the substrate, a plurality of plating processes each continuing for a predetermined period of time are performed. Therefore, it is possible to efficiently fill the plating film into the perforations with increasing average current values, thereby shortening the time required to complete the plating process. The reverse electrolysis process performed between the plating processes effectively dissolves the plating film deposited on the corners of the perforations. Therefore, it is possible to ideally fill the perforation with the plating film by preferentially growing the plating film at the center of the perforation in the depth direction.

由以下說明及舉例說明本發明較佳實施例的附圖可明白以上及其他的本發明目標、特徵及優點。The above and other objects, features and advantages of the present invention will become apparent from the description of the appended claims.

此時用附圖描述本發明的較佳具體實施例。第2圖的垂直剖面正視圖示意圖示用於實施本發明電鍍方法的電鍍設備50。如第2圖所示,電鍍設備50包含保存鍍覆液Q於其中的鍍覆槽51,以及固持基板W(例如,半導體晶圓片或其類似物)且垂直懸吊於鍍覆液Q之中的基板固持件10。有基板固持件10浸在其中的鍍覆液Q在鍍覆槽51上端有水平面L,如第2圖所示。各自支撐於陽極固持器58上的兩個不溶陽極52在鍍覆槽51中配置成分別與由基板固持件10固持之基板W的兩面(亦即,正、反面)面對面。如第3圖所示,基板固持件10包含有圓孔11a定義於其中的第一固持構件11與有圓孔12a定義於其中的第二固持構件12。第一固持構件11與第二固持構件12用來固持基板W於其間。不溶陽極52為圓形以及尺寸與第一及第二固持構件11、12的圓孔11a、12a實質相同。Preferred embodiments of the present invention will now be described with reference to the drawings. The vertical cross-sectional front view of Fig. 2 schematically shows an electroplating apparatus 50 for carrying out the electroplating method of the present invention. As shown in FIG. 2, the plating apparatus 50 includes a plating tank 51 in which the plating solution Q is stored, and a holding substrate W (for example, a semiconductor wafer or the like) and vertically suspended in the plating liquid Q. The substrate holder 10 in the middle. The plating solution Q in which the substrate holder 10 is immersed has a horizontal plane L at the upper end of the plating tank 51 as shown in Fig. 2. The two insoluble anodes 52 each supported on the anode holder 58 are disposed in the plating tank 51 to face the both faces (i.e., the front and back sides) of the substrate W held by the substrate holding member 10, respectively. As shown in Fig. 3, the substrate holder 10 includes a first holding member 11 in which the circular hole 11a is defined and a second holding member 12 in which the circular hole 12a is defined. The first holding member 11 and the second holding member 12 are used to hold the substrate W therebetween. The insoluble anode 52 is circular and has substantially the same size as the circular holes 11a, 12a of the first and second holding members 11, 12.

由絕緣材料製成的兩個調整板60在鍍覆槽51中配置於基板固持件10與各自的不溶陽極52之間。調整板60各有定義於其中的圓孔而形狀與第一及第二固持構件11、12之圓孔11a、12a的類似。不溶陽極52電氣各自連接至延伸自鍍覆電源53之端子的電線61a,鍍覆電源53各自能夠改變供給電流的方向從而也改變電流值。鍍覆電源53有各自電性連接至電線61b的另一端子,電線61b各自連接至基板固持件10的端子板27、28(參考第3圖)。鍍覆電源53也電性連接至個別控制鍍覆電源53的控制器59。Two adjustment plates 60 made of an insulating material are disposed between the substrate holder 10 and the respective insoluble anodes 52 in the plating tank 51. The adjustment plates 60 each have a circular hole defined therein and have a shape similar to that of the circular holes 11a, 12a of the first and second holding members 11, 12. The insoluble anodes 52 are electrically connected to respective electric wires 61a extending from the terminals of the plating power source 53, each of which can change the direction of the supply current and thereby also change the current value. The plating power source 53 has the other terminal electrically connected to the electric wire 61b, and the electric wires 61b are each connected to the terminal plates 27, 28 of the substrate holder 10 (refer to Fig. 3). The plating power source 53 is also electrically connected to the controller 59 that individually controls the plating power source 53.

兩個攪拌漿62在鍍覆槽51中配置於由基板固持件10固持的基板W與各自的調整板60之間。攪拌漿62可與由基板固持件10固持之基板W平行地來回運動用以攪拌鍍覆液Q。電鍍設備50也包含配置於鍍覆槽51四周的外槽57用以保存溢出鍍覆槽51的鍍覆液Q。溢出鍍覆槽51進入外槽57的鍍覆液Q藉由鍍覆液循環泵54通過恆溫單元55及濾器56由底部循環回到鍍覆槽51。The two agitating pastes 62 are disposed between the substrate W held by the substrate holder 10 and the respective adjustment plates 60 in the plating tank 51. The agitating paddle 62 is movable back and forth in parallel with the substrate W held by the substrate holder 10 to agitate the plating solution Q. The plating apparatus 50 also includes an outer tank 57 disposed around the plating tank 51 for holding the plating liquid Q overflowing the plating tank 51. The plating solution Q that has overflowed the plating tank 51 into the outer tank 57 is circulated from the bottom portion back to the plating tank 51 by the plating liquid circulation pump 54 through the constant temperature unit 55 and the filter 56.

第3圖為基板固持件10的正視圖。第4圖為基板固持件10的平面圖。第5圖為基板固持件10的仰視圖。第6圖為沿著第3圖之直線K-K繪出的橫截面圖。第7圖圖示以第6圖之箭頭A為視線繪出的基板固持件10。第8圖圖示以第6圖之箭頭B為視線繪出的基板固持件10。第9圖圖示以第6圖之箭頭C為視線繪出的基板固持件10。第10圖為沿著第7圖之直線D-D繪出的橫截面圖。第11圖為沿著第7圖之直線E-E繪出的橫截面圖。第12圖為沿著第3圖之直線F-F繪出的橫截面圖。第13圖為沿著第7圖之直線G-G繪出的橫截面圖。第14圖為沿著第8圖之直線H-H繪出的橫截面圖。FIG. 3 is a front view of the substrate holder 10. 4 is a plan view of the substrate holder 10. FIG. 5 is a bottom view of the substrate holder 10. Fig. 6 is a cross-sectional view taken along line K-K of Fig. 3. Fig. 7 is a view showing the substrate holder 10 drawn with the arrow A of Fig. 6 as a line of sight. Fig. 8 is a view showing the substrate holder 10 drawn with the arrow B of Fig. 6 as a line of sight. Fig. 9 is a view showing the substrate holder 10 drawn with the arrow C of Fig. 6 as a line of sight. Figure 10 is a cross-sectional view taken along line D-D of Figure 7. Figure 11 is a cross-sectional view taken along line E-E of Figure 7. Fig. 12 is a cross-sectional view taken along line F-F of Fig. 3. Figure 13 is a cross-sectional view taken along line G-G of Figure 7. Fig. 14 is a cross-sectional view taken along line H-H of Fig. 8.

如第3圖所示,基板固持件10的第一固持構件11及第二固持構件12(各自呈平面形)各自有用樞接機構(hinge mechanism)13可樞轉地相互耦合的下端。樞接機構13有由合成樹脂(例如,HTPVC)製成且固定於第二固持構件12的兩個鉤13-1。鉤13-1用由不鏽鋼(例如,SUS 303)製成的鉤銷(hook pin)13-2可角度運動地支撐於第一固持構件11的下端上。第一固持構件11由合成樹脂(例如,HTPVC)製成以及呈實質五角形。圓孔11a定義於第一固持構件11的中央,如第7圖所示。如第3圖所示,由合成樹脂(例如,HTPVC)製成的T形掛架14與第一固持構件11的上端整體成形。第二固持構件12由合成樹脂(例如,HTPVC)製成以及呈實質五角形。圓孔12a定義於第二固持構件12的中央。As shown in FIG. 3, the first holding member 11 and the second holding member 12 (each in a planar shape) of the substrate holder 10 are each pivotally coupled to each other with a lower end of a hinge mechanism 13. The pivoting mechanism 13 has two hooks 13-1 made of synthetic resin (for example, HTPVC) and fixed to the second holding member 12. The hook 13-1 is angularly movably supported on the lower end of the first holding member 11 by a hook pin 13-2 made of stainless steel (for example, SUS 303). The first holding member 11 is made of a synthetic resin (for example, HTPVC) and has a substantially pentagonal shape. The circular hole 11a is defined in the center of the first holding member 11, as shown in Fig. 7. As shown in FIG. 3, a T-shaped hanger 14 made of a synthetic resin (for example, HTPVC) is integrally formed with the upper end of the first holding member 11. The second holding member 12 is made of a synthetic resin (for example, HTPVC) and has a substantially pentagonal shape. The circular hole 12a is defined in the center of the second holding member 12.

當第一固持構件11與第二固持構件12以樞接機構13為中心轉成相互重疊時,亦即,當基板固持件10關閉時,第一固持構件11與第二固持構件12用左、右夾鉗15、16夾在一起。各由合成樹脂(例如,HTPVC)製成的左、右夾鉗15、16,各自有凹槽15a、16a用以容納相互重疊之第一固持構件11與第二固持構件12的兩側邊緣於其中。左、右夾鉗15、16的下端各自藉由插銷17、18而可角度運動地支撐於第一固持構件11之兩對邊的下端上。When the first holding member 11 and the second holding member 12 are rotated to overlap each other with the pivoting mechanism 13 as the center, that is, when the substrate holding member 10 is closed, the first holding member 11 and the second holding member 12 are left, The right clamps 15, 16 are clamped together. The left and right clamps 15, 16 each made of a synthetic resin (for example, HTPVC) each have a recess 15a, 16a for accommodating the both side edges of the first holding member 11 and the second holding member 12 which are overlapped with each other. among them. The lower ends of the left and right clamps 15, 16 are each angularly movably supported by the lower ends of the opposite sides of the first holding member 11 by the pins 17, 18.

如第7圖所示,密封環19裝在第一固持構件11中面對第二固持構件12的表面上,以及繞著孔11a延伸。如第9圖所示,密封環20裝在第二固持構件12中面對第一固持構件11的表面上,以及繞著孔12a延伸。密封環19、20由橡膠製成,例如,矽氧樹脂橡膠(silicone rubber)。O環29裝在第二固持構件12中面對第一固持構件11的表面上,以及繞著密封環20延伸。As shown in Fig. 7, the seal ring 19 is mounted on the surface of the first holding member 11 facing the second holding member 12, and extends around the hole 11a. As shown in Fig. 9, the seal ring 20 is mounted on the surface of the second holding member 12 facing the first holding member 11, and extends around the hole 12a. The seal rings 19, 20 are made of rubber, for example, silicone rubber. The O-ring 29 is mounted on the surface of the second holding member 12 facing the first holding member 11, and extends around the sealing ring 20.

各有矩形橫截面形狀的密封環19、20各自有由其內周緣徑向向內突出及延伸的隆脊19a、20a。當第一固持構件11與第二固持構件12在有基板W介於其間下相互重疊時,隆脊19a、20a各自壓著基板W的表面以及與其保持緊密接觸,這在O環29與徑向在孔11a、12a之外的隆脊19a、20a之間定義無鍍覆液Q的水密空間。如第7圖及第10圖所示,用於定位基板W的8個基板導銷21係裝在第一固持構件11中面對第二固持構件12的表面上,徑向在孔11a之外,以及突出穿過密封環19。The seal rings 19, 20 each having a rectangular cross-sectional shape each have ridges 19a, 20a projecting and extending radially inward from the inner periphery thereof. When the first holding member 11 and the second holding member 12 overlap each other with the substrate W interposed therebetween, the ridges 19a, 20a each press the surface of the substrate W and maintain close contact therewith, which is in the O-ring 29 and the radial direction. A watertight space free of the plating solution Q is defined between the ridges 19a, 20a outside the holes 11a, 12a. As shown in FIGS. 7 and 10, eight substrate guide pins 21 for positioning the substrate W are attached to the surface of the first holding member 11 facing the second holding member 12, radially outside the hole 11a. And protruding through the seal ring 19.

如第7圖、第11圖及第12圖所示,6個導電板22繞著孔11a裝在第一固持構件11中面對第二固持構件12的表面上。如第11圖所示,6個導電板22中有3個通過導電針腳(conductive pin)23與基板W中之一面(例如,正面)上的種子層104(參考第1A圖至第1D圖)保持電接觸。如第12圖所示,其他3個導電板22通過導電針腳23與在基板W之另一面(例如,反面)上的種子層104保持電接觸。As shown in Figs. 7, 11, and 12, six conductive plates 22 are mounted around the hole 11a in the first holding member 11 facing the surface of the second holding member 12. As shown in FIG. 11, three of the six conductive plates 22 pass through the conductive pin 23 and the seed layer 104 on one side (for example, the front surface) of the substrate W (refer to FIGS. 1A to 1D). Keep electrical contact. As shown in Fig. 12, the other three conductive plates 22 are in electrical contact with the seed layer 104 on the other side (e.g., the reverse side) of the substrate W via the conductive pins 23.

與基板W中之一面(例如,正面)上的種子層104保持電接觸3個導電板22通過延伸穿過電線插槽25(參考第13圖)的絕緣包覆電線26各自電性連接至設於掛架14之端子板27上的電極端子27a、27b、27c(參考第4圖)。與在基板W之另一面(例如,反面)上的種子層104保持電接觸的其他3個導電板22通過延伸穿過電線插槽25(參考第13圖)的絕緣包覆電線26各自電性連接至設於掛架14之另一端子板28上的電極端子28a、28b、28c(參考第4圖)。如第7圖及第13圖所示,絕緣包覆電線26用由合成樹脂(例如,PVC)製成的電線夾持器30固定。Maintaining electrical contact with the seed layer 104 on one of the sides (eg, the front side) of the substrate W. The three conductive plates 22 are electrically connected to each other by the insulated covered wires 26 extending through the wire slots 25 (refer to FIG. 13). The electrode terminals 27a, 27b, and 27c on the terminal block 27 of the pylon 14 (refer to Fig. 4). The other three conductive plates 22 that are in electrical contact with the seed layer 104 on the other side (e.g., the reverse side) of the substrate W are electrically connected by the insulated covered wires 26 extending through the wire slots 25 (refer to Fig. 13). It is connected to the electrode terminals 28a, 28b, 28c provided on the other terminal plate 28 of the pylon 14 (refer to FIG. 4). As shown in Figs. 7 and 13, the insulated covered electric wire 26 is fixed by a wire holder 30 made of a synthetic resin (for example, PVC).

基板固持件10的操作如下:當第一固持構件11與第二固持構件12以樞接機構13為中心轉動而相互分開時,亦即,當基板固持件10打開時,基板W位於第一固持構件11上被8個基板導銷21包圍的區域中。基板W此時固定在第一固持構件11上。第一固持構件11與第二固持構件12以樞接機構13為中心轉向對方,亦即,基板固持件10關閉。然後,左、右夾鉗15、16繞著插銷17、18做角運動直到第一固持構件11與第二固持構件12的兩側邊緣各自插入左、右夾鉗15、16的凹槽15a、16a。固定在第一固持構件11上的基板W此時夾在第一固持構件11與第二固持構件12之間。The operation of the substrate holder 10 is as follows: when the first holding member 11 and the second holding member 12 are rotated apart from each other with the pivoting mechanism 13 as being centered, that is, when the substrate holding member 10 is opened, the substrate W is located at the first holding The member 11 is in a region surrounded by eight substrate guide pins 21. The substrate W is now fixed on the first holding member 11. The first holding member 11 and the second holding member 12 are turned toward each other centering on the pivoting mechanism 13, that is, the substrate holding member 10 is closed. Then, the left and right clamps 15, 16 are angularly moved about the pins 17, 18 until the side edges of the first and second holding members 11 and 12 are inserted into the grooves 15a of the left and right clamps 15, 16 respectively. 16a. The substrate W fixed to the first holding member 11 is now sandwiched between the first holding member 11 and the second holding member 12.

O環29與密封環19、20的隆脊19a、20a一起定義在其間無鍍覆液Q的水密空間。此時,基板W的外周緣區(徑向在隆脊19a、20a之外)位於該水密空間裡,以及基板W兩面的表面區域(第一固持構件11與第二固持構件12之孔11a、12a共延)暴露於孔11a、12a。在6個導電板22中,與在基板W之一面上之種子層104保持電接觸的3個導電板22電性連接至設於掛架14之端子板27上的電極端子27a、27b、27c,以及與在基板W另一面上之種子層104保持電接觸的其他3個導電板22電性連接至設於掛架14之端子板28上的電極端子28a、28b、28c。The O-ring 29 together with the ridges 19a, 20a of the seal rings 19, 20 define a watertight space in which there is no plating solution Q therebetween. At this time, the outer peripheral edge region of the substrate W (radially outside the ridges 19a, 20a) is located in the watertight space, and the surface regions of both surfaces of the substrate W (the holes 11a of the first holding member 11 and the second holding member 12, 12a is coextensive) exposed to the holes 11a, 12a. Among the six conductive plates 22, three conductive plates 22 that are in electrical contact with the seed layer 104 on one side of the substrate W are electrically connected to the electrode terminals 27a, 27b, 27c provided on the terminal plate 27 of the pylon 14. And three other conductive plates 22 that are in electrical contact with the seed layer 104 on the other side of the substrate W are electrically connected to the electrode terminals 28a, 28b, 28c provided on the terminal block 28 of the pylon 14.

第15圖的正視圖圖示第2圖電鍍設備中固持不溶陽極52於其中的陽極固持器58,而第16圖為第15圖的橫截面圖。在此具體實施例中,為了防止陽極被鍍覆液的添加劑(或數種)溶解,使用陽極主體各由鈦構成以及塗上例如氧化銥的不溶陽極52。Fig. 15 is a front elevational view showing the anode holder 58 in which the insoluble anode 52 is held in the electroplating apparatus of Fig. 2, and Fig. 16 is a cross-sectional view of Fig. 15. In this embodiment, in order to prevent the anode from being dissolved by the additive (or several) of the plating solution, the anode bodies are each made of titanium and coated with an insoluble anode 52 such as ruthenium oxide.

如第15圖及第16圖所示,陽極固持器58中之每一包含有中心孔70a定義於其中的固持器主體70,配置於固持器主體70反面及封閉中心孔70a的封閉板72,配置於固持器主體70之中心孔70a中及保持不溶陽極52於其表面上使得不溶陽極52位於中心孔70a中的圓形支撐板74,以及裝在固持器主體70正面上及圍住中心孔70a的環形陽極遮蔽物76。支撐板74有定義於其中的通道74a,通道74a容納電性連接至延伸自鍍覆電源53之電線61a的導電板78於其中。導電板78延伸至支撐板74的中央區,在此導電板78電性連接至不溶陽極52。As shown in FIGS. 15 and 16, each of the anode holders 58 includes a holder body 70 defined therein with a center hole 70a, and a closing plate 72 disposed on the reverse side of the holder body 70 and closing the center hole 70a. a circular support plate 74 disposed in the center hole 70a of the holder main body 70 and holding the insoluble anode 52 on the surface thereof so that the insoluble anode 52 is located in the center hole 70a, and mounted on the front surface of the holder main body 70 and surrounding the center hole Annular anode shield 76 of 70a. The support plate 74 has a passage 74a defined therein, and the passage 74a houses a conductive plate 78 electrically connected to the electric wire 61a extending from the plated power source 53 therein. The conductive plate 78 extends to a central region of the support plate 74 where the conductive plate 78 is electrically connected to the insoluble anode 52.

作成為中性薄膜形式的隔離薄膜80經配置成可覆蓋不溶陽極52中位於固持器主體70之中心孔70a的表面。隔離薄膜80有被固持器主體70及陽極遮蔽物76夾住的周邊,而且固定於固持器主體70。陽極遮蔽物76用螺絲82固定於固持器主體70,以及封閉板72也用螺絲固定於固持器主體70。The separator film 80 in the form of a neutral film is configured to cover the surface of the insoluble anode 52 located at the center hole 70a of the holder body 70. The separator 80 has a periphery sandwiched by the holder body 70 and the anode shield 76, and is fixed to the holder body 70. The anode shield 76 is fixed to the holder main body 70 with a screw 82, and the closing plate 72 is also screwed to the holder main body 70.

在陽極固持器58浸入鍍覆液Q時,鍍覆液Q進入固持器主體70中心孔70a中在不溶陽極52、支撐板74之間的間隙。When the anode holder 58 is immersed in the plating solution Q, the plating solution Q enters a gap between the insoluble anode 52 and the support plate 74 in the center hole 70a of the holder main body 70.

使用不溶陽極52與隔離薄膜80的理由如下:要添加於鍍覆液Q的添加劑包含用以促進形成單價銅的組份,這會損及其他添加劑的功能,因為它造成其他添加劑氧化分解。結果,不能使用可溶陽極。在使用不溶陽極時,不溶陽極在其附近產生氧氣,產生的氧氣部份溶入鍍覆液Q,而增加溶解氧(dissolved oxygen)的濃度。溶解氧的濃度增加容易造成添加劑氧化分解。因此,合意的方式是,將形式為中性薄膜的隔離薄膜80配置成與不溶陽極52的表面呈覆蓋關係以防對於基板W附近之添加劑的組份有不利影響,即使它們在不溶陽極52附近經受氧化分解。The reason for using the insoluble anode 52 and the separator film 80 is as follows: The additive to be added to the plating solution Q contains a component for promoting formation of a monovalent copper, which may impair the function of other additives because it causes oxidative decomposition of other additives. As a result, a soluble anode cannot be used. When an insoluble anode is used, the insoluble anode generates oxygen in the vicinity thereof, and the generated oxygen is partially dissolved in the plating solution Q to increase the concentration of dissolved oxygen. An increase in the concentration of dissolved oxygen tends to cause oxidative decomposition of the additive. Therefore, it is desirable to arrange the barrier film 80 in the form of a neutral film in a covering relationship with the surface of the insoluble anode 52 to prevent adverse effects on the components of the additive near the substrate W even if they are in the vicinity of the insoluble anode 52. Subject to oxidative decomposition.

另一合意的方式是,用空氣或氮供給過孔(例如,通氣管,未圖示)使不溶陽極52附近的鍍覆液Q充滿氣泡或氣體用以防止溶解氧的濃度在不溶陽極52側不適當地上升。Another desirable way is to supply a permeate (for example, a vent tube, not shown) with air or nitrogen to fill the plating solution Q near the insoluble anode 52 with bubbles or gas to prevent the dissolved oxygen concentration from being on the insoluble anode 52 side. Not rising properly.

由於被陽極固持器58固持之不溶陽極52的表面覆蓋著隔離薄膜80而不溶陽極52係配置成允許隔離薄膜80面對被基板固持件10固持及配置於鍍覆槽51內的基板W,因此在使鍍覆液Q充滿氣泡及氣體時有可能防止氧氣在不溶陽極52附近產生以及溶入鍍覆液從而防止溶解氧在鍍覆液Q中的濃度增加。Since the surface of the insoluble anode 52 held by the anode holder 58 is covered with the separator film 80, the insoluble anode 52 is configured to allow the separator film 80 to face the substrate W held by the substrate holder 10 and disposed in the plating tank 51, When the plating solution Q is filled with bubbles and gas, it is possible to prevent oxygen from being generated in the vicinity of the insoluble anode 52 and dissolved in the plating solution to prevent an increase in the concentration of dissolved oxygen in the plating solution Q.

以此方式構成之電鍍設備50的操作如下:將固持暴露正、反面之基板W的基板固持件10放入鍍覆槽51的鍍覆液Q使得基板W之一面(例如,正面)面對不溶陽極52中之一個,以及基板W的另一面(例如,反面)面對另一個不溶陽極52。鍍覆電源53各自在基板W正面與面對基板W正面的不溶陽極52之間,以及在基板W反面與面對基板W反面的不溶陽極52之間,供給用控制器59控制的鍍覆電流,從而同時鍍覆基板W的正、反面。如果必要的話,在鍍覆基板W的正、反面時,使攪拌漿62與基板W平行地來回運動以攪拌鍍覆液Q。以此方式,如第1A圖至第1D圖所示,鍍覆膜106會在定義於基板W穿孔100a中成長。The plating apparatus 50 constructed in this manner operates as follows: the substrate holding member 10 holding the substrate W exposed to the front and the back is placed in the plating solution Q of the plating tank 51 so that one side (for example, the front surface) of the substrate W is insoluble. One of the anodes 52, and the other side of the substrate W (e.g., the reverse side) faces the other insoluble anode 52. The plating power source 53 is each provided between the front surface of the substrate W and the insoluble anode 52 facing the front surface of the substrate W, and between the reverse side of the substrate W and the insoluble anode 52 facing the reverse side of the substrate W, and the plating current controlled by the controller 59 is supplied. Thereby, the front and back sides of the substrate W are simultaneously plated. If necessary, when the front and back sides of the substrate W are plated, the stirring slurry 62 is moved back and forth in parallel with the substrate W to agitate the plating solution Q. In this manner, as shown in FIGS. 1A to 1D, the plating film 106 is grown in the substrate W perforation 100a.

第17圖至第19圖的放大橫截面圖各自圖示沿著不同橫截面繪出的另一基板固持件。圖示於第17圖至第19圖的基板固持件與上述基板固持件不同的地方如下:如第17圖所示,該基板固持件包含近端各自固定於第一固持構件11及第二固持構件12的彈性導電板90、92,而不是第11圖及第12圖的導電針腳22、23。當基板W被第一固持構件11及第二固持構件12固持時,彈性導電板90、92的遠側自由端分別有彈性地頂著基板W的正、反面與基板W之正、反面上的種子層104(參考第1A圖至第1D圖)保持電接觸。The enlarged cross-sectional views of Figs. 17 to 19 each illustrate another substrate holder drawn along different cross sections. The substrate holders shown in FIGS. 17 to 19 are different from the substrate holders as follows: As shown in FIG. 17, the substrate holders each include a proximal end fixed to the first holding member 11 and a second holding member. The resilient conductive plates 90, 92 of the member 12 are instead of the conductive pins 22, 23 of Figures 11 and 12. When the substrate W is held by the first holding member 11 and the second holding member 12, the distal free ends of the elastic conductive plates 90, 92 respectively elastically abut against the front and back surfaces of the substrate W and the front and back surfaces of the substrate W. The seed layer 104 (refer to FIGS. 1A through 1D) maintains electrical contact.

如第18圖及第19圖所示,該基板固持件也包含各自用以固持密封環19、20的密封環固持器94、96。密封環固持器94、96各自固定於第一固持構件11、第二固持構件12。密封環固持器94、96各自有由交替導齒97、98構成的陣列用以定位基板W,而不是圖示於第7圖及第10圖的基板導銷21。導齒97、98各自沿著密封環固持器94、96的周向配置於各個位置。導齒97、98在自由端附近各自有在內周面上的錐形表面97a、98a。當基板W被第一固持構件11及第二固持構件12固持時,基板W的外周緣與錐形表面97a、98a保持接觸及引導以使基板W就定位。As shown in Figures 18 and 19, the substrate holder also includes seal ring retainers 94, 96 for holding the seal rings 19, 20, respectively. The seal ring holders 94, 96 are each fixed to the first holding member 11 and the second holding member 12. The seal ring holders 94, 96 each have an array of alternating guide teeth 97, 98 for positioning the substrate W instead of the substrate guide pins 21 illustrated in Figures 7 and 10. The guide teeth 97, 98 are each disposed at each position along the circumferential direction of the seal ring holders 94, 96. The guide teeth 97, 98 each have a tapered surface 97a, 98a on the inner peripheral surface near the free end. When the substrate W is held by the first holding member 11 and the second holding member 12, the outer peripheral edge of the substrate W is kept in contact with and guided by the tapered surfaces 97a, 98a to position the substrate W.

第20圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之鍍覆電流實施例的陰極電流密度與時間關係圖。供給於基板W反面與面對基板W反面的不溶陽極52之間的鍍覆電流係與供給於基板W正面與面對基板W正面的不溶陽極52之間的鍍覆電流保持同步。不過,該等鍍覆電流彼此不需同步化,因而本發明應不受限於以上鍍覆電流是否同步。對於供給於基板W表面與面對基板W表面的不溶陽極52之間的鍍覆電流,第20圖圖示陰極電流密度與時間的關係。Figure 20 is a graph showing cathode current density versus time for an embodiment of a plating current supplied between the surface of the substrate W and the insoluble anode 52 (which is disposed to face the surface of the substrate W). The plating current supplied between the reverse side of the substrate W and the insoluble anode 52 facing the reverse side of the substrate W is synchronized with the plating current supplied between the front surface of the substrate W and the insoluble anode 52 facing the front surface of the substrate W. However, the plating currents need not be synchronized with each other, and thus the invention should not be limited to whether the above plating currents are synchronized. For the plating current supplied between the surface of the substrate W and the insoluble anode 52 facing the surface of the substrate W, Fig. 20 illustrates the relationship between the cathode current density and time.

第20圖的實施例係交替重覆以下兩種製程:鍍覆製程A,其係供給脈衝電流於基板W表面與不溶陽極52之間用以鍍覆基板W表面持續一段預定時段;以及逆向電解製程B,其供給電流方向係與在鍍覆製程A時供給於基板W表面與不溶陽極52之間的電流相反。因此,實施鍍覆製程A的預定時段在50至100毫秒的範圍內,例如,以及實施逆向電解製程B的預定時段在0.1至10毫秒的範圍內,或0.5至1毫秒的範圍內為較佳。The embodiment of Fig. 20 alternately repeats the following two processes: a plating process A for supplying a pulse current between the surface of the substrate W and the insoluble anode 52 for plating the surface of the substrate W for a predetermined period of time; and reverse electrolysis Process B, the direction of the supply current is opposite to the current supplied between the surface of the substrate W and the insoluble anode 52 during the plating process A. Therefore, the predetermined period of time during which the plating process A is performed is in the range of 50 to 100 milliseconds, for example, and the predetermined period of time for performing the reverse electrolytic process B is in the range of 0.1 to 10 milliseconds, or preferably in the range of 0.5 to 1 millisecond. .

如第20圖的虛線所示,在逆向電解製程B之後、鍍覆製程A之前可插入例如0.05毫秒的靜止期(quiescent period)C,此時在基板W表面與不溶陽極52之間沒有電流供給。靜止期C可均勻化穿孔內之鍍覆液Q的金屬離子分布用以有效率地將鍍覆膜填入穿孔。在以下所述的其他實施例中插入靜止期C是有利的。As shown by the broken line in Fig. 20, a quiescent period C of, for example, 0.05 msec can be inserted after the reverse electrolysis process B and before the plating process A, at which time there is no current supply between the surface of the substrate W and the insoluble anode 52. . The stationary phase C can homogenize the metal ion distribution of the plating solution Q in the perforations for efficiently filling the plating film into the perforations. It is advantageous to insert a stationary phase C in other embodiments described below.

在第20圖的實施例中,實施鍍覆製程A使用有以下交替重覆之周期的PR脈衝電流:正常電解周期,例如脈衝間距為P1,鍍覆電流正向流動(亦即,鍍覆方向),正值陰極電流密度D1在1至3 ASD(A/dm)之間;以及逆向電解周期,例如脈衝間距為P2,鍍覆電流逆向流動,負值陰極電流密度D2在-0.05至-4 ASD之間。例如,PR脈衝電流之逆向電解周期的脈衝間距P2為0.5毫秒。例如,逆向電解製程B用脈衝間距P3在0.1至10毫秒之間(0.5至1毫秒為較佳)以及負值陰極電流密度D3在-30至-40 ASD之間的單一脈衝實施。In the embodiment of Fig. 20, the plating process A is performed using the PR pulse current having the following alternating repetition period: a normal electrolysis cycle, for example, a pulse pitch of P 1 , and a plated current is flowing forward (ie, plating) Direction), the positive cathode current density D 1 is between 1 and 3 ASD (A/dm); and the reverse electrolysis period, for example, the pulse spacing is P 2 , the plating current flows countercurrently, and the negative cathode current density D 2 is at - Between 0.05 and -4 ASD. For example, the pulse pitch P 2 of the reverse electrolysis period of the PR pulse current is 0.5 msec. For example, the reverse electrolysis process B is carried out with a single pulse having a pulse pitch P 3 between 0.1 and 10 milliseconds (0.5 to 1 millisecond is preferred) and a negative cathode current density D 3 between -30 and -40 ASD.

由於逆向電解製程B在鍍覆製程A後用例如在-30至-40 ASD之間的負值陰極電流密度D3實施,如第21圖的虛線所示,容易沉積於穿孔100a轉角的鍍覆膜106a會溶入鍍覆液Q,從而允許鍍覆膜106優先在穿孔100a轉角沿著深度方向成長,如第21圖的實線所示。Since the reverse electrolytic process B is performed after the plating process A with a negative cathode current density D 3 of, for example, between -30 and -40 ASD, as shown by the broken line in Fig. 21, the plating is easily deposited on the corner of the perforation 100a. The film 106a is dissolved in the plating solution Q, thereby allowing the plating film 106 to preferentially grow in the depth direction at the corner of the perforation 100a as shown by the solid line in FIG.

如示意圖示於第22圖,在鍍覆製程,鍍覆膜106微觀表面上的異常沉積容易產生精細不規則性106b。不過,例如,根據第20圖的實施例,用負值陰極電流密度D2在-0.05至-4 ASD之間的逆向電解周期,可防止精細不規則性106b產生。由異常沉積引起的精細不規則性106b會以其他方式相互連結而在鍍覆膜中形成精細空洞。As shown in Fig. 22, in the plating process, abnormal deposition on the microscopic surface of the plating film 106 is liable to cause fine irregularities 106b. However, for example, according to the embodiment of Fig. 20, the fine irregularity 106b can be prevented from being generated by the reverse electrolysis period in which the negative cathode current density D 2 is between -0.05 and -4 ASD. Fine irregularities 106b caused by abnormal deposition may be interconnected in other ways to form fine voids in the plating film.

第23圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之另一鍍覆電流實施例的陰極電流密度與時間關係圖。第23圖的實施例與第20圖實施例不同的地方在於在施加正向鍍覆電流的正常電解周期之前及之後用脈衝間距P4在0.1至10毫秒之間(0.5至1.0毫秒為較佳)的兩個脈衝實施逆向電解製程B1Figure 23 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). The embodiment of Fig. 23 differs from the embodiment of Fig. 20 in that the pulse pitch P 4 is between 0.1 and 10 milliseconds before and after the normal electrolysis cycle in which the forward plating current is applied (0.5 to 1.0 msec is preferred). The two pulses of the reverse electrolysis process B 1 are performed .

負值陰極電流密度D3在-30至-40 ASD之間的逆向電解製程B,如第20圖所示,用單一脈衝實施,其脈衝間距P3在0.1至10毫秒之間。如果脈衝間距P3大於1毫秒,則如第24A圖所示,鍍覆膜106會過度溶入鍍覆液而形成過度溶解區112。如第24B圖所示,過度溶解區112使開端被封閉而容易在埋入穿孔110a的鍍覆膜106內產生貓眼空洞(cat-eyed void)114。因此,脈衝間距P3在0.1至1.0毫秒的範圍內為較佳,在0.5至1.0毫秒的範圍內更佳。The reverse electrolysis process B, in which the negative cathode current density D 3 is between -30 and -40 ASD, as shown in Fig. 20, is carried out with a single pulse with a pulse pitch P 3 of between 0.1 and 10 msec. If the pulse pitch P 3 is greater than 1 millisecond, as shown in Fig. 24A, the plating film 106 is excessively dissolved in the plating solution to form the excessive dissolution region 112. As shown in Fig. 24B, the excessive dissolution zone 112 causes the open end to be closed to easily produce a cat-eyed void 114 in the plating film 106 embedded in the perforation 110a. Therefore, the pulse pitch P 3 is preferably in the range of 0.1 to 1.0 msec, more preferably in the range of 0.5 to 1.0 msec.

不過,取決於定義於基板W之穿孔的高深寬比,根據逆向電解製程,用脈衝間距小於1.0毫秒的單一脈衝優先在穿孔中心沿著深度方向理想地嵌入鍍覆膜可能為無法實現的理想嵌入製程。如第23圖所示,藉由施加脈衝間距P4都小於1.0毫秒的兩個脈衝來實施的逆向電解製程B1使得有可能理想地將鍍覆膜填入此一穿孔。However, depending on the high aspect ratio of the perforations defined on the substrate W, it is possible to ideally embed the plating film in the depth direction of the perforation center with a single pulse having a pulse pitch of less than 1.0 msec depending on the reverse electrolysis process. Process. As shown in Fig. 23, the reverse electrolysis process B 1 which is carried out by applying two pulses each having a pulse pitch P 4 of less than 1.0 msec makes it possible to ideally fill the perforated film with the plating film.

第25圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之又一鍍覆電流實施例的陰極電流密度與時間關係圖。第25圖的實施例包括3個不同鍍覆製程,亦即,鍍覆製程(第一鍍覆製程)A1是在第一區沿著穿孔100a深度方向直到穿孔100a的鍍覆膜106在中心處實質連結,如第1A圖至第1C圖所示,鍍覆製程(第二鍍覆製程)A2是在第二區用以在穿孔100a的凹處108嵌入鍍覆膜106至預定厚度,如第1C圖與第1D圖所示,以及鍍覆製程(第三鍍覆製程)A3在第三區是在第1D圖的階段後減少夾止(pinch-off)的危險。Figure 25 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). Embodiment of FIG. 25 embodiment includes three different plating processes, i.e., the plating process (a first plating process) A 1 in the first region 100a in the depth direction along the perforation 100a through perforations 106 in the center of the plated film In the substantial connection, as shown in FIGS. 1A to 1C, the plating process (second plating process) A 2 is used in the second region to embed the plating film 106 in the recess 108 of the through hole 100a to a predetermined thickness. As shown in FIGS. 1C and 1D, and the plating process (third plating process) A 3 in the third zone is a risk of reducing pinch-off after the stage of FIG. 1D.

在第25圖中,第一鍍覆製程A1,第二鍍覆製程A2及第三鍍覆製程A3係圖示成在逆向電解製程B(參考第20圖)之前及之後各實施一次。不過,第一鍍覆製程A1,第二鍍覆製程A2及第三鍍覆製程A3中之每一實際上在逆向電解製程B之前及之後可實施數次。這也應用於以下所述的其他實施例。In Fig. 25, the first plating process A 1 , the second plating process A 2 and the third plating process A 3 are illustrated as being performed once before and after the reverse electrolysis process B (refer to Fig. 20). . However, each of the first plating process A 1 , the second plating process A 2 , and the third plating process A 3 may be performed several times before and after the reverse electrolytic process B. This also applies to other embodiments described below.

在第25圖的實施例中,第一鍍覆製程A1,第二鍍覆製程A2及第三鍍覆製程A3中之每一的實施是用開/關脈衝電流,其係交替重覆地供給及不供給正向流動(亦即,鍍覆方向)的鍍覆電流,以及有例如在1至3 ASD之間的正值陰極電流密度D1。第一鍍覆製程A1的開/關脈衝電流的脈衝間距P5小於第二鍍覆製程A2之開/關脈衝電流的脈衝間距P6(P5<P6),以及第二鍍覆製程A2之開/關脈衝電流的脈衝間距P6小於第三鍍覆製程A3之開/關脈衝電流的脈衝間距P7(P6<P7)。第一、第二及第三鍍覆製程A1、A2、A3的開/關脈衝電流有彼此相等的關機間距(downtime pitch)P8、P9、P10(P8=P9=P10)。因此,陰極電流密度的平均值逐步增加。替換地,陰極電流密度的平均值可線性遞增。In the embodiment of FIG. 25, each of the first plating process A 1 , the second plating process A 2 , and the third plating process A 3 is performed by using an on/off pulse current, which is alternately heavy. The plating current is supplied to the ground and the plating current is not supplied to the forward flow (i.e., the plating direction), and there is a positive cathode current density D 1 between, for example, 1 to 3 ASD. The pulse pitch P 5 of the on/off pulse current of the first plating process A 1 is smaller than the pulse pitch P 6 (P 5 <P 6 ) of the on/off pulse current of the second plating process A 2 , and the second plating The pulse pitch P 6 of the on/off pulse current of the process A 2 is smaller than the pulse pitch P 7 of the on/off pulse current of the third plating process A 3 (P 6 <P 7 ). The on/off pulse currents of the first, second, and third plating processes A 1 , A 2 , and A 3 have equal downtime pitches P 8 , P 9 , and P 10 (P 8 = P 9 = P 10 ). Therefore, the average value of the cathode current density is gradually increased. Alternatively, the average value of the cathode current density can be linearly increased.

由於開/關脈衝電流提供整個鍍覆製程不供給鍍覆電流的非鍍覆時段,穿孔內鍍覆液的金屬離子濃度會在非鍍覆時段恢復,從而防止鍍覆膜形成諸如空洞之類的缺陷。在鍍覆製程中,隨著穿孔逐漸填滿鍍覆膜,穿孔的實質高深寬比也跟著改變。當穿孔的實質高深寬比改變時,藉由遞增鍍覆製程的平均陰極電流密度有可能以與穿孔的實質高深寬比變化匹配的方式來有效率地將鍍覆膜填入穿孔。結果,可進一步縮短鍍覆基板所需要的時間。Since the on/off pulse current provides a non-plating period in which the plating current is not supplied to the entire plating process, the metal ion concentration of the plating solution in the perforation is restored during the non-plating period, thereby preventing the plating film from being formed such as a void. defect. In the plating process, as the perforations gradually fill the plating film, the substantial aspect ratio of the perforations also changes. When the substantial high aspect ratio of the perforations is changed, it is possible to efficiently fill the perforations with the plating film by increasing the average cathode current density of the plating process in a manner that matches the substantially high aspect ratio of the perforations. As a result, the time required to plate the substrate can be further shortened.

隨著鍍覆製程的進展而逐步增加鍍覆電流密度為本技藝所習知。不過,在鍍覆電流密度由低鍍覆電流密度至高鍍覆電流密度的整個範圍內難以抑制單價銅的產生。根據此實施例,由於陰極電流密度有恆定的峰值以抑制單價銅的產生,因此可防止鍍覆液劣化。It is well known in the art to gradually increase the plating current density as the plating process progresses. However, it is difficult to suppress the generation of monovalent copper in the entire range of the plating current density from the low plating current density to the high plating current density. According to this embodiment, since the cathode current density has a constant peak to suppress the generation of the monovalent copper, the plating solution can be prevented from being deteriorated.

第26圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之另一鍍覆電流實施例的陰極電流密度與時間關係圖。第26圖的實施例與第25圖實施例不同的地方在於藉由施加脈衝間距P4各在0.1至10毫秒之間(在0.5至1.0毫秒之間為較佳)的兩個脈衝來實施圖示於第23圖的逆向電解製程B1,而不是用例如脈衝間距P3在0.1至10毫秒之間(0.5至1毫秒之間為較佳)的單一脈衝來實施第25圖逆向電解製程B。Figure 26 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). The difference between the embodiment of Fig. 26 and the embodiment of Fig. 25 is that the image is applied by applying two pulses each having a pulse pitch P 4 of between 0.1 and 10 milliseconds (preferably between 0.5 and 1.0 milliseconds). The reverse electrolysis process B 1 shown in Fig. 23, instead of performing the reverse electrolysis process B of Fig. 25, with a single pulse such as a pulse pitch P 3 of between 0.1 and 10 msec (preferably between 0.5 and 1 msec) .

第27圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之又一鍍覆電流實施例的陰極電流密度與時間關係圖。第27圖的實施例與第25圖實施例不同的地方在於第一、第二及第三鍍覆製程A1、A2、A3有彼此相等的加工時間,第一鍍覆製程A1之開/關脈衝電流的脈衝間距P5小於第二鍍覆製程A2之開/關脈衝電流的脈衝間距P6(P5<P6),第二鍍覆製程A2之開/關脈衝電流的脈衝間距P6小於第三鍍覆製程A3之開/關脈衝電流的脈衝間距P7(P6<P7),第一鍍覆製程A1之開/關脈衝電流的關機間距P8大於第二鍍覆製程A2之開/關脈衝電流的關機間距P9(P8>P9),以及第二鍍覆製程A2之開/關脈衝電流的關機間距P9大於第三鍍覆製程A3之開/關脈衝電流的關機間距P10(P9>P10)。因此,陰極電流密度的平均值會逐步增加。Figure 27 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). The difference between the embodiment of Fig. 27 and the embodiment of Fig. 25 is that the first, second and third plating processes A 1 , A 2 , A 3 have processing times equal to each other, and the first plating process A 1 pulse interval on / off pulse current P 5 is smaller than the second plating process a the opening 2 of the / pulse interval off pulse current P 6 (P 5 <P 6 ), a second plating process a 2 of the on / off pulse current The pulse pitch P 6 is smaller than the pulse pitch P 7 (P 6 <P 7 ) of the on/off pulse current of the third plating process A 3 , and the shutdown pitch P 8 of the on/off pulse current of the first plating process A 1 shut off the pitch distance apart greater than the second plating process of 2 a / off pulse current P 9 (P 8> P 9 ), and a second plating process a 2 of the opening / closing of the pulse current is greater than the third plating P 9 The shutdown interval P 10 (P 9 > P 10 ) of the on/off pulse current of the process A 3 is overwritten. Therefore, the average value of the cathode current density is gradually increased.

第28圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之另一鍍覆電流實施例的陰極電流密度與時間關係圖。第28圖的實施例與第25圖實施例不同的地方在於使用組合脈衝式電源來供給例如正值陰極電流密度D1在1至3 ASD之間的第一鍍覆電流,以及例如正值陰極電流密度D4在0.1至0.5 ASD之間的第二鍍覆電流,而不是藉由重覆地供給及不供給正向流動(亦即,鍍覆方向)以及正值陰極電流密度D1在1至3 ASD之間的鍍覆電流來供給開/關脈衝電流的電源。Figure 28 illustrates a graph of cathode current density versus time for another plated current embodiment applied between the surface of substrate W and insoluble anode 52 (configured to face the surface of substrate W). 28 embodiment of the first embodiment of FIG. 25 where a different embodiment of FIG embodiment is characterized by using a combination of a pulsed power supply, for example, to a cathode current density value D 1 of the first plating current between 1 and 3 ASD, and a cathode value e.g. The second plating current of the current density D 4 is between 0.1 and 0.5 ASD, instead of being supplied by the repeated supply and not supplying the forward flow (ie, the plating direction) and the positive cathode current density D 1 at 1 A plating current between 3 ASDs to supply a power source for turning on/off the pulse current.

由於組合脈衝式電源用來持續地供給例如在0.1至0.5 ASD之間的弱電流,而不是停止供給鍍覆電流,鍍覆膜在鍍覆製程中會持續成長。因此,可防止鍍覆膜溶入鍍覆製程的鍍覆液。Since the combined pulsed power supply is used to continuously supply a weak current, for example, between 0.1 and 0.5 ASD, instead of stopping the supply of the plating current, the plating film continues to grow during the plating process. Therefore, it is possible to prevent the plating film from being dissolved in the plating solution of the plating process.

第29圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之又一鍍覆電流實施例的陰極電流密度與時間關係圖。第29圖的實施例與第25圖實施例不同的地方在於PR脈衝電流的供給係藉由重覆實施例如正值陰極電流密度D1在1至3 ASD之間的正常電解周期,以及例如負值陰極電流密度D2在-0.05至-4 ASD之間的逆向電解周期,而不是藉由重覆供給及不供給例如正值陰極電流密度在1至3 ASD之間的鍍覆電流來供給開/關脈衝電流。Figure 29 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). The difference between the embodiment of Fig. 29 and the embodiment of Fig. 25 is that the supply of the PR pulse current is repeated by performing, for example, a normal electrolysis period of a positive cathode current density D 1 between 1 and 3 ASD, and for example, negative The value of the cathode current density D 2 is in the reverse electrolysis cycle between -0.05 and -4 ASD, rather than being supplied by re-feeding and not supplying a plating current such as a positive cathode current density between 1 and 3 ASD. / off pulse current.

第30圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之另一鍍覆電流實施例的陰極電流密度與時間關係圖。第30圖的實施例與第25圖實施例不同的地方在於它藉由供給例如正值陰極電流密度D1在1至3 ASD之間的直流鍍覆電流來依序實施第一、第二及第三鍍覆製程A1、A2、A3,第一、第二及第三鍍覆製程A1、A2、A3有依序加長的加工時間(A1<A2<A3)。Figure 30 illustrates a graph of cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). The difference between the embodiment of Fig. 30 and the embodiment of Fig. 25 is that it sequentially implements the first and second sums by supplying a DC plating current such as a positive cathode current density D 1 between 1 and 3 ASD. The third plating process A 1 , A 2 , A 3 , the first, second and third plating processes A 1 , A 2 , A 3 have sequential processing times (A 1 <A 2 <A 3 ) .

取決於穿孔的高深寬比,鍍覆底層的結構,鍍覆液的本質、等等,在逆向電解製程之間可能不需要提供靜止期。如果不需要靜止期,則基板W表面、不溶陽極52可供給鍍覆電流以實現第30圖中陰極電流密度與時間的關係從而縮短完成鍍覆製程所需時間以有效率地將鍍覆膜填入穿孔。Depending on the high aspect ratio of the perforations, the structure of the underlying plating, the nature of the plating solution, and the like, it may not be necessary to provide a stationary period between the reverse electrolysis processes. If the stationary period is not required, the surface of the substrate W and the insoluble anode 52 can supply a plating current to achieve the relationship between the cathode current density and time in FIG. 30, thereby shortening the time required to complete the plating process to efficiently fill the plating film. Into the perforation.

第31圖圖示供給於基板W表面、不溶陽極52(經配置成面對著基板W表面)間之又一鍍覆電流實施例的陰極電流密度與時間關係圖。第31圖的實施例與第20圖實施例不同的地方在於當鍍覆膜106穿孔100a的凹處108嵌入預定厚度時,如第1D圖所示,藉此減少夾止的危險,例如,逆向電解製程B之後,藉由供給例如正值陰極電流密度D1在1至3 ASD之間的直流鍍覆電流來實施鍍覆製程A4。在減少夾止危險的階段,大體完成鍍覆膜嵌入基板W的穿孔100a,如第1D圖所示,以及最終要填滿留在基板表面上的凹窩(dimple)。此時,不需要供給直流鍍覆電流以使陰極電流密度與先前的脈衝尖峰電流密度相等,但是可供給直流鍍覆電流以使陰極電流密度高於先前脈衝尖峰電流密度,從而縮短完成鍍覆製程所需時間。Figure 31 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (which is disposed to face the surface of the substrate W). The embodiment of Fig. 31 differs from the embodiment of Fig. 20 in that when the recess 108 of the perforation 100a of the plating film 106 is embedded in a predetermined thickness, as shown in Fig. 1D, thereby reducing the risk of pinching, for example, reverse After the electrolytic process B, the plating process A 4 is carried out by supplying a DC plating current of, for example, a positive cathode current density D 1 of between 1 and 3 ASD. At the stage of reducing the risk of pinching, the perforations 100a of the plating film embedded in the substrate W are substantially completed, as shown in Fig. 1D, and finally filled with dimples remaining on the surface of the substrate. At this time, it is not necessary to supply a DC plating current to make the cathode current density equal to the previous pulse peak current density, but a DC plating current can be supplied to make the cathode current density higher than the previous pulse peak current density, thereby shortening the completion of the plating process. Time required.

第32圖圖示供給於基板W表面與不溶陽極52(經配置成面對著基板W表面)間之另一鍍覆電流實施例的陰極電流密度與時間關係圖。第32圖的實施例與第27圖實施例不同的地方在於藉由供給例如正值陰極電流密度D1在1至3 ASD之間的直流鍍覆電流來進行第三鍍覆製程A3,從而縮短完成鍍覆製程所需時間。Figure 32 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). The difference between the embodiment of Fig. 32 and the embodiment of Fig. 27 is that the third plating process A 3 is performed by supplying a DC plating current of, for example, a positive cathode current density D 1 of between 1 and 3 ASD, thereby Shorten the time required to complete the plating process.

儘管已圖示及詳述本發明的一些較佳具體實施例,然而應瞭解,仍可做出各種改變及修改而不脫離隨附申請專利範圍的範疇。While the preferred embodiment of the present invention has been shown and described, it is understood that various modifications and changes may be made without departing from the scope of the appended claims.

10...基板固持件10. . . Substrate holder

11...第一固持構件11. . . First holding member

11a、12a...圓孔11a, 12a. . . Round hole

12...第二固持構件12. . . Second holding member

13...樞接機構13. . . Pivot mechanism

13-1...鉤13-1. . . hook

13-2...鉤銷13-2. . . Hook pin

14...T形掛架14. . . T-shaped rack

15、16...夾鉗15,16. . . clamp

15a、16a...凹槽15a, 16a. . . Groove

17、18...插銷17, 18. . . plug

19、20...密封環19, 20. . . Sealing ring

19a、20a...隆脊19a, 20a. . . Ridge

21...基板導銷twenty one. . . Substrate guide pin

22...導電板twenty two. . . Conductive plate

23...導電針腳twenty three. . . Conductive pin

25...電線插槽25. . . Wire slot

26...絕緣包覆電線26. . . Insulated covered wire

27、28...端子板27, 28. . . Terminal board

27a、27b、27c、28a、28b、28c...電極端子27a, 27b, 27c, 28a, 28b, 28c. . . Electrode terminal

29...O環29. . . O ring

30...電線夾持器30. . . Wire holder

50...電鍍設備50. . . Plating equipment

51...鍍覆槽51. . . Plating tank

52...不溶陽極52. . . Insoluble anode

53...鍍覆電源53. . . Plating power supply

54...鍍覆液循環泵54. . . Plating liquid circulation pump

55...恆溫單元55. . . Thermostatic unit

56...濾器56. . . filter

57...外槽57. . . Outer slot

58...陽極固持器58. . . Anode holder

59...控制器59. . . Controller

60...調整板60. . . Adjustment board

61a、61b...電線61a, 61b. . . wire

62...攪拌漿62. . . Stirring slurry

70...固持器主體70. . . Holder body

70a...中心孔70a. . . Center hole

72...封閉板72. . . Closed plate

74...圓形支撐板74. . . Circular support plate

74a...通道74a. . . aisle

76...環形陽極遮蔽物76. . . Annular anode shield

78...導電板78. . . Conductive plate

80...隔離薄膜80. . . Isolation film

82...螺絲82. . . Screw

90、92...彈性導電板90, 92. . . Elastic conductive plate

94、96...密封環固持器94, 96. . . Seal ring retainer

97、98...導齒97, 98. . . Guide tooth

97a、98a...錐形表面97a, 98a. . . Conical surface

100...基部100. . . Base

100a...垂直穿孔100a. . . Vertical perforation

102...阻障層102. . . Barrier layer

104...種子層104. . . Seed layer

106、106a...鍍覆膜106, 106a. . . Plating film

108...凹處108. . . Recess

112...過度溶解區112. . . Excessive zone

114...貓眼空洞114. . . Cat's eye cavity

A1、A2、A3...鍍覆製程A 1 , A 2 , A 3 . . . Plating process

Bx...逆向電解製程Bx. . . Reverse electrolysis process

D1...正值陰極電流密度D 1 . . . Positive cathode current density

D2...負值陰極電流密度D 2 . . . Negative cathode current density

D3...負值陰極電流密度D 3 . . . Negative cathode current density

D4...正值陰極電流密度D 4 . . . Positive cathode current density

L...水平面L. . . level

P1-P7...脈衝間距P 1 -P 7 . . . Pulse spacing

P8-P10...關機間距P 8 -P 10 . . . Shutdown interval

Q...鍍覆液Q. . . Plating solution

W...基板W. . . Substrate

第1A圖至第1D圖所示的製程步驟序列係圖解說明用以將鍍覆膜填入定義於基板之穿孔以於其中形成通孔的方法;The sequence of process steps shown in FIGS. 1A to 1D illustrate a method for filling a plating film into a perforation defined in a substrate to form a via hole therein;

第2圖的垂直剖面正視圖示意圖示用於實施本發明電鍍方法的電鍍設備;2 is a vertical cross-sectional front view schematically showing an electroplating apparatus for carrying out the electroplating method of the present invention;

第3圖為第2圖電鍍設備中之基板固持件的正視圖;Figure 3 is a front elevational view of the substrate holder in the electroplating apparatus of Figure 2;

第4圖為第2圖電鍍設備中之基板固持件的平面圖;Figure 4 is a plan view of the substrate holder in the electroplating apparatus of Figure 2;

第5圖為第2圖電鍍設備中之基板固持件的仰視圖;Figure 5 is a bottom view of the substrate holder in the electroplating apparatus of Figure 2;

第6圖為沿著第3圖之直線K-K繪出的橫截面圖;Figure 6 is a cross-sectional view taken along line K-K of Figure 3;

第7圖圖示以第6圖之箭頭A為視線繪出的基板固持件;Figure 7 is a diagram showing a substrate holder drawn by the arrow A of Figure 6;

第8圖圖示以第6圖之箭頭B為視線繪出的基板固持件;Figure 8 is a diagram showing a substrate holder drawn by the arrow B of Figure 6;

第9圖圖示以第6圖之箭頭C為視線繪出的基板固持件;Figure 9 is a view showing the substrate holder drawn by the arrow C of Figure 6;

第10圖為沿著第7圖之直線D-D繪出的橫截面圖;Figure 10 is a cross-sectional view taken along line D-D of Figure 7;

第11圖為沿著第7圖之直線E-E繪出的橫截面圖;Figure 11 is a cross-sectional view taken along line E-E of Figure 7;

第12圖為沿著第3圖之直線F-F繪出的橫截面圖;Figure 12 is a cross-sectional view taken along line F-F of Figure 3;

第13圖為沿著第7圖之直線G-G繪出的橫截面圖;Figure 13 is a cross-sectional view taken along line G-G of Figure 7;

第14圖為沿著第8圖之直線H-H繪出的橫截面圖;Figure 14 is a cross-sectional view taken along line H-H of Figure 8;

第15圖的正視圖圖示第2圖電鍍設備中固持不溶陽極於其中的陽極固持器;Figure 15 is a front elevational view showing the anode holder in which the insoluble anode is held in the electroplating apparatus of Figure 2;

第16圖的橫截面圖圖示第2圖電鍍設備中固持不溶陽極於其中的陽極固持器;Figure 16 is a cross-sectional view showing the anode holder in which the insoluble anode is held in the electroplating apparatus of Figure 2;

第17圖的放大橫截面圖圖示另一基板固持件的主要部份;Figure 17 is an enlarged cross-sectional view showing the main portion of another substrate holder;

第18圖的放大橫截面圖圖示第17圖之基板固持件的主要部份;Figure 18 is an enlarged cross-sectional view showing the main portion of the substrate holder of Figure 17;

第19圖的放大橫截面圖圖示第17圖之基板固持件的主要部份;Figure 19 is an enlarged cross-sectional view showing the main portion of the substrate holder of Figure 17;

第20圖圖示供給於基板表面、陽極間之鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 20 is a graph showing a relationship between a cathode current density and a time of an embodiment of a plating current supplied between a substrate surface and an anode;

第21圖的放大局部橫截面圖圖示在鍍覆製程後執行逆向電解製程時在穿孔沿著深度方向的中央處優先成長鍍覆膜的方式;FIG. 21 is an enlarged partial cross-sectional view showing a manner of preferentially growing a plating film at a center of a perforation along a depth direction when performing a reverse electrolysis process after a plating process;

第22圖的放大局部橫截面圖示意圖示鍍覆製程中由鍍覆膜微觀表面之異常沉積產生的精細不規則性;Figure 22 is an enlarged partial cross-sectional view showing the fine irregularity caused by the abnormal deposition of the microscopic surface of the plating film in the plating process;

第23圖圖示供給於基板表面與陽極間之另一鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 23 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode;

第24A圖與第24B圖的放大局部橫截面圖示意圖示嵌入穿孔之鍍覆膜過度溶入鍍覆液直到最終在鍍覆膜中形成空洞的方式;24A and 24B are schematic enlarged cross-sectional views showing the manner in which the plating film embedded in the perforation is excessively dissolved into the plating solution until a void is finally formed in the plating film;

第25圖圖示供給於基板表面與陽極間之又一鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 25 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode;

第26圖圖示供給於基板表面與陽極間之另一鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 26 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode;

第27圖圖示供給於基板表面與陽極間之又一鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 27 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode;

第28圖圖示供給於基板表面與陽極間之另一鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 28 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode;

第29圖圖示供給於基板表面與陽極間之又一鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 29 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode;

第30圖圖示供給於基板表面與陽極間之另一鍍覆電流實施例的陰極電流密度與時間關係圖;Figure 30 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode;

第31圖圖示供給於基板表面與陽極間之又一鍍覆電流實施例的陰極電流密度與時間關係圖;以及Figure 31 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate and the anode;

第32圖圖示供給於基板表面與陽極間之另一鍍覆電流實施例的陰極電流密度與時間關係圖。Figure 32 is a graph showing cathode current density versus time for another embodiment of plating current supplied between the surface of the substrate and the anode.

10...基板固持件10. . . Substrate holder

14...T形掛架14. . . T-shaped rack

27、28...端子板27, 28. . . Terminal board

50...電鍍設備50. . . Plating equipment

51...鍍覆槽51. . . Plating tank

52...不溶陽極52. . . Insoluble anode

53...鍍覆電源53. . . Plating power supply

54...鍍覆液循環泵54. . . Plating liquid circulation pump

55...恆溫單元55. . . Thermostatic unit

56...濾器56. . . filter

57...外槽57. . . Outer slot

58...陽極固持器58. . . Anode holder

59...控制器59. . . Controller

60...調整板60. . . Adjustment board

61a、61b...電線61a, 61b. . . wire

62...攪拌漿62. . . Stirring slurry

L...水平面L. . . level

Q...鍍覆液Q. . . Plating solution

W...基板W. . . Substrate

Claims (11)

一種電鍍方法,其係包含下列步驟:將有穿孔定義於其中的基板浸入在鍍覆槽中的鍍覆液;將在該鍍覆槽之該鍍覆液中的一對陽極配置成分別與在該鍍覆液中之該基板的正、反面面對面;於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間,進行將脈衝電流以峰值恆定的預定電流密度正向流動而將金屬填入前述穿孔的內部之正常電解周期、與將脈衝電流以第1電流密度逆向流動而防止於前述金屬的表面產生的精細不規則性之第1逆向電解製程,而隨著鍍覆進展,以逐漸增加平均電流密度的方式執行對基板的正、反面進行各自持續一預定時段的複數個鍍覆製程;以及在該等鍍覆製程的相鄰製程之間,於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間,進行將電流以第2電流密度逆向流動而溶解沉積於前述穿孔角落之前述金屬之第2逆向電解製程;前述第2電流密度大於前述第1電流密度。 An electroplating method comprising the steps of: immersing a substrate having a perforation defined therein in a plating solution in a plating bath; and configuring a pair of anodes in the plating solution of the plating tank to be respectively The front and back sides of the substrate in the plating solution face each other; between the front surface of the substrate and one of the front surfaces of the anode facing the substrate, and the opposite side of the substrate and the anode Between the other of the opposite sides of the substrate, a normal electrolysis period in which a pulse current flows forward at a predetermined current density at a constant peak to fill a metal inside the perforation, and a pulse current is reversed at a first current density a first reverse electrolysis process that prevents fine irregularities generated on the surface of the aforementioned metal, and as the plating progresses, the positive and negative faces of the substrate are each performed for a predetermined period of time in a manner of gradually increasing the average current density. a plurality of plating processes; and between adjacent ones of the substrates, between the front side of the substrate and one of the front faces of the substrate facing the substrate, and Between the opposite side of the substrate and the other of the opposite sides of the substrate facing the substrate, a second reverse electrolysis process for dissolving the current in the second current density to dissolve the metal deposited in the perforated corner is performed; The second current density is greater than the first current density. 如申請專利範圍第1項所述之電鍍方法,其中,在前述正常電解周期之前及之後,多次執行前述第2逆向電解 製程。 The electroplating method according to claim 1, wherein the second reverse electrolysis is performed a plurality of times before and after the normal electrolysis cycle. Process. 一種電鍍方法,其係包含下列步驟:將有穿孔定義於其中的基板浸入在鍍覆槽中的鍍覆液;將在該鍍覆槽之該鍍覆液中的一對陽極配置成分別與在該鍍覆液中之該基板的正、反面面對面;於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間,各自供給峰值恆定的脈衝電流,隨著鍍覆進展加長前述脈衝電流的流動時間,以對基板的正、反面進行各自持續一預定時段的複數個鍍覆製程;以及在該等鍍覆製程的相鄰製程之間,進行於該基板之該正面與該等陽極中面對該基板之該正面的一個之間,以及於該基板之該反面與該等陽極中面對該基板之該反面的另一個之間各自供給與鍍覆時相反的電流之逆向電解製程。 An electroplating method comprising the steps of: immersing a substrate having a perforation defined therein in a plating solution in a plating bath; and configuring a pair of anodes in the plating solution of the plating tank to be respectively The front and back sides of the substrate in the plating solution face each other; between the front surface of the substrate and one of the front surfaces of the anode facing the substrate, and the opposite side of the substrate and the anode Between each other of the opposite sides of the substrate, a pulse current having a constant peak value is supplied, and as the plating progresses, the flow time of the pulse current is lengthened to perform a plurality of plating for each of the front and back surfaces of the substrate for a predetermined period of time. Between the adjacent processes of the plating process, between the front side of the substrate and one of the front faces of the substrate facing the substrate, and the opposite side of the substrate A reverse electrolysis process in which an opposite current to the plating is applied to the other of the opposite sides of the substrate in the anode is supplied. 如申請專利範圍第3項所述之電鍍方法,其中該等脈衝電流中之每一包含以正向流動電流與反向流動電流之交替重覆呈現的PR脈衝電流。 The electroplating method of claim 3, wherein each of the pulse currents comprises a PR pulse current that is represented by an alternating repetition of a forward flow current and a reverse flow current. 如申請專利範圍第3項所述之電鍍方法,其中該等脈衝電流中之每一包含以供給及不供給正向流動鍍覆電流之交替重覆呈現的開/關脈衝電流。 The electroplating method of claim 3, wherein each of the pulse currents comprises an on/off pulse current presented in alternating repetitions of supply current and no supply of forward flow plating current. 如申請專利範圍第3項所述之電鍍方法,其中該等脈衝 電流中之每一包含以有不同電流值之兩個脈衝電流之一組合呈現的組合脈衝電流。 An electroplating method as described in claim 3, wherein the pulses Each of the currents comprises a combined pulse current presented in combination of one of two pulsed currents having different current values. 如申請專利範圍第3項所述之電鍍方法,其中係隨著該基板的鍍覆進展,在前述逆向電解製程之前及之後,以逐漸增加平均電流密度的方式執行該等鍍覆製程。 The electroplating method according to claim 3, wherein the plating process is performed in such a manner as to gradually increase the average current density before and after the reverse electrolysis process as the plating progress of the substrate progresses. 如申請專利範圍第3項所述之電鍍方法,其中在以正向供給脈衝電流的正常電解周期之前及之後,多次執行該逆向電解製程。 The electroplating method according to claim 3, wherein the reverse electrolysis process is performed a plurality of times before and after a normal electrolysis cycle in which a pulse current is supplied in the forward direction. 如申請專利範圍第5項所述之電鍍方法,其中係隨鍍覆進展而縮短前述正向電流不供給之時間。 The electroplating method according to claim 5, wherein the time during which the forward current is not supplied is shortened as the plating progresses. 如申請專利範圍第5項所述之電鍍方法,其中係隨鍍覆進展而加長前述正向電流供給之時間。 The electroplating method according to claim 5, wherein the time of the forward current supply is lengthened as the plating progresses. 如申請專利範圍第10項所述之電鍍方法,其中前述正向電流不供給之時間為恆定。 The electroplating method according to claim 10, wherein the time during which the forward current is not supplied is constant.
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